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                  AXI-Stream FIFO 参考设计阅读指南
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目标器件：GW2A-LV55PG484C8/I7
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文件列表
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.
| -- docs
|    `-- readme.txt										-->	自述文件
| -- project
|    |-- 1_Board_project_AXI4_LITE_32bit
|         | `--IP_TEST.gprj								-->	参考设计工程1
|         |-- impl
|         |--src
|		      | `--AXI_Stream_FIFO_TB.v					-->	工程1顶层模块
|	          | `--AXI_test.cst
|			  | `--AXI_test.rao
|			  | `--clk_constraints.sdc
|			  |--axi_stream_fifo
|	    		  | `--axi_stream_fifo.v
|	    		  | `--axi_stream_fifo.ipc						
|	    		  | `--axi_stream_fifo.vo				-->	仿真使用vo文件1
|    |-- 2_Board_project_AXI4_FULL_32bit
|         | `--IP_TEST.gprj								-->	参考设计工程2
|         |-- impl
|         |--src
|			  | `--AXI_Stream_FIFO_TB.v					-->	工程2顶层模块
|			  | `--AXI_test.cst
|			  | `--AXI_test.rao
|		 	  | `--clk_constraints.sdc
|			  |--axi_stream_fifo
|	    		  | `--axi_stream_fifo.v
|	    		  | `--axi_stream_fifo.ipc
|	    		  | `--axi_stream_fifo.vo				-->	仿真使用vo文件2
|    |-- 3_Board_project_AXI4_FULL_64bit
|         | `--IP_TEST.gprj								-->	参考设计工程3
|         |-- impl
|         |--src
|			  | `--AXI_Stream_FIFO_TB.v					-->	工程3顶层模块
|			  | `--AXI_test.cst
|			  | `--AXI_test.rao
|			  | `--clk_constraints.sdc
|			  |--axi_stream_fifo
|	    		  | `--axi_stream_fifo.v
|	    		  | `--axi_stream_fifo.ipc
|	    		  | `--axi_stream_fifo.vo				-->	仿真使用vo文件3
| -- simulation
|    |-- Modelsim
|         |-- 1_simulation_axi4_lite_32bit
|              | `--cmd.do								-->	modelsim仿真1脚本
|              | `--master_define.v						-->	参数配置文件1
|         |-- 2_simulation_axi4_full_32bit
|              | `--cmd.do								-->	modelsim仿真2脚本
|              | `--master_define.v						-->	参数配置文件2
|         |-- 3_simulation_axi4_full_64bit
|              | `--cmd.do								-->	modelsim仿真3脚本
|              | `--master_define.v						-->	参数配置文件3
|    |-- VCS
|         |-- 1_simulation_axi4_lite_32bit
|              | `--makefile							-->	VCS仿真1脚本
|              | `--master_define.v						-->	参数配置文件1
|         |-- 2_simulation_axi4_full_32bit
|              | `--makefile							-->	VCS仿真2脚本
|              | `--master_define.v						-->	参数配置文件2
|         |-- 3_simulation_axi4_full_64bit
|              | `--makefile							-->	VCS仿真3脚本
|              | `--master_define.v						-->	参数配置文件3
| --tb
|    `--AXI_Stream_FIFO_TB.v							-->	仿真testbench
|    `--prim_sim.v										-->	仿真源语库

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使用说明：
	1、板测：使用云源软件打开上述文件中IP_TEST.gprj，设置工程顶层模块，综合；根据所使用器件设置约束和gao.v后布局布线后下载测试。使用GAO抓取数据。
	2、modelsim仿真：仿真脚本存放于Modelsim文件夹中。
	3、vcs仿真：仿真脚本存放于VCS文件夹中

	注：tb文件夹下prim_sim.v仅供参考，建议用户根据情况在仿真时使用最新版替换。

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                  Example AXI-Stream FIFO Design Readme
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Object device:GW2A-LV55PG484C8/I7
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File List:
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.
| -- docs
|    `-- readme.txt										-->	Read Me file (this file)
| -- project
|    |-- 1_Board_project_AXI4_LITE_32bit
|         | `--IP_TEST.gprj								-->	Gowin Project File for Example Design 1st
|         |-- impl
|         |--src
|			  | `--AXI_Stream_FIFO_TB.v					-->	Top file for Gowin Project 1st
|			  | `--AXI_test.cst
|			  | `--AXI_test.rao
|			  | `--clk_constraints.sdc
|			  |--axi_stream_fifo
|	    		  | `--axi_stream_fifo.v
|	    		  | `--axi_stream_fifo.ipc
|	    		  | `--axi_stream_fifo.vo				-->	Verilog simulation File for tb 1st
|    |-- 2_Board_project_AXI4_FULL_32bit
|         | `--IP_TEST.gprj								-->	Gowin Project File for Example Design 2nd
|         |-- impl
|         |--src
|			  | `--AXI_Stream_FIFO_TB.v					-->	Top file for Gowin Project 2nd
|			  | `--AXI_test.cst
|			  | `--AXI_test.rao
|			  | `--clk_constraints.sdc
|			  |--axi_stream_fifo
|	    		  | `--axi_stream_fifo.v
|	    		  | `--axi_stream_fifo.ipc
|	    		  | `--axi_stream_fifo.vo				-->	Verilog simulation File for tb 2nd
|    |-- 3_Board_project_AXI4_FULL_64bit
|         | `--IP_TEST.gprj			-->	Gowin Project File for Example Design 3rd
|         |-- impl
|         |--src
|			  | `--AXI_Stream_FIFO_TB.v					-->	Top file for Gowin Project 3rd
|			  | `--AXI_test.cst
|			  | `--AXI_test.rao
|			  | `--clk_constraints.sdc
|			  |--axi_stream_fifo
|	    		  | `--axi_stream_fifo.v
|	    		  | `--axi_stream_fifo.ipc
|	    		  | `--axi_stream_fifo.vo				-->	Verilog simulation File for tb 3rd
| -- simulation
|    |-- Modelsim
|         |-- 1_simulation_axi4_lite_32bit
|              | `--cmd.do								-->	Modelsim simulation script 1st
|              | `--master_define.v						-->	Parameter configuration file 1st
|         |-- 2_simulation_axi4_full_32bit
|              | `--cmd.do								-->	Modelsim simulation script 2nd
|              | `--master_define.v						-->	Parameter configuration file 2nd
|         |-- 3_simulation_axi4_full_64bit
|              | `--cmd.do								-->	Modelsim simulation script 3rd
|              | `--master_define.v						-->	Parameter configuration file 3rd
|    |-- VCS
|         |-- 1_simulation_axi4_lite_32bit
|              | `--makefile							-->	VCS simulation script 1st
|              | `--master_define.v						-->	Parameter configuration file 1st
|         |-- 2_simulation_axi4_full_32bit
|              | `--makefile							-->	VCS simulation script 2nd
|              | `--master_define.v						-->	Parameter configuration file 2nd
|         |-- 3_simulation_axi4_full_64bit
|              | `--makefile							-->	VCS simulation script 3rd
|              | `--master_define.v						-->	Parameter configuration file 3rd
| --tb
|    `--AXI_Stream_FIFO_TB.v							-->	TestBench for simulation
|    `--prim_sim.v										-->	Verilog functional simulation library
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Instructions:
	1.Onboard test: Launch GOWIN FPGA Designer and select "File -> Open -> Project", set Top Module and Include Path. After Sythesize, cofigure Physical Constraints and GAO Config Files.
	2.Modelsim simulation: Please use script in Modelsim folder.
	3.VCS simulation:Use script in VCS folder.

	Note:The prim_sim.v under the tb folder is for reference only. It is recommended that users replace it with the latest version during simulation.