Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_Float_to_Fixed_RefDesign\Proj\impl\gwsynthesis\Float_Fix.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_Float_to_Fixed_RefDesign\Proj\src\Float_to_Fixed.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_Float_to_Fixed_RefDesign\Proj\src\Float_to_Fixed.sdc
Tool Version	V1.9.11 (64-bit)
Part Number	GW2A-LV55PG484C8/I7
Device	GW2A-55
Created Time	Tue Dec 24 09:09:08 2024
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	1447
Numbers of Endpoints Analyzed	1762
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk	Base	20.000	50.000	0.000	10.000			clk
2	tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	65.881(MHz)	12	TOP
2	tck_pad_i	20.000(MHz)	149.083(MHz)	6	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.457	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	3.363	5.110
2	1.752	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	4.816
3	1.752	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	4.816
4	1.863	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	4.704
5	1.918	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	4.649
6	2.021	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	4.547
7	2.106	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	4.462
8	2.106	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	4.462
9	2.112	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	4.456
10	2.117	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	4.450
11	2.447	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_13_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	3.363	4.120
12	2.591	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_13_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	3.976
13	2.769	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_13_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	3.363	3.799
14	2.782	gw_gao_inst_0/u_la0_top/capture_windows_num_4_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	3.785
15	2.817	gw_gao_inst_0/u_la0_top/capture_windows_num_4_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	3.750
16	2.880	gw_gao_inst_0/u_la0_top/capture_windows_num_9_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	3.687
17	2.909	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	3.659
18	2.970	gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	3.598
19	3.208	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	3.363	3.359
20	3.517	gw_gao_inst_0/u_la0_top/capture_windows_num_9_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	3.051
21	3.673	gw_gao_inst_0/u_la0_top/capture_windows_num_9_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_4_s0/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	2.894
22	3.700	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_3_s0/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	2.867
23	3.860	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	2.707
24	3.860	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	2.707
25	3.947	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D	tck_pad_i:[R]	clk:[R]	10.000	3.363	2.620

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.076	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]	clk:[R]	clk:[R]	0.000	0.000	0.325
2	0.076	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1]	clk:[R]	clk:[R]	0.000	0.000	0.325
3	0.192	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
4	0.192	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
5	0.192	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
6	0.192	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
7	0.192	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
8	0.202	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[7]	clk:[R]	clk:[R]	0.000	0.000	0.451
9	0.202	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2]	clk:[R]	clk:[R]	0.000	0.000	0.451
10	0.202	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0]	clk:[R]	clk:[R]	0.000	0.000	0.451
11	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[13]	clk:[R]	clk:[R]	0.000	0.000	0.462
12	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[8]	clk:[R]	clk:[R]	0.000	0.000	0.462
13	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[6]	clk:[R]	clk:[R]	0.000	0.000	0.462
14	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[5]	clk:[R]	clk:[R]	0.000	0.000	0.462
15	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[4]	clk:[R]	clk:[R]	0.000	0.000	0.462
16	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3]	clk:[R]	clk:[R]	0.000	0.000	0.462
17	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_67_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[3]	clk:[R]	clk:[R]	0.000	0.000	0.474
18	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_68_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[4]	clk:[R]	clk:[R]	0.000	0.000	0.584
19	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[15]	clk:[R]	clk:[R]	0.000	0.000	0.584
20	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11]	clk:[R]	clk:[R]	0.000	0.000	0.584
21	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[10]	clk:[R]	clk:[R]	0.000	0.000	0.584
22	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[9]	clk:[R]	clk:[R]	0.000	0.000	0.584
23	0.347	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]	clk:[R]	clk:[R]	0.000	0.000	0.596
24	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_70_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[6]	clk:[R]	clk:[R]	0.000	0.000	0.612
25	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[5]	clk:[R]	clk:[R]	0.000	0.000	0.612

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.750	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.986
2	6.750	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.986
3	6.750	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.986
4	6.761	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.975
5	7.247	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.489
6	7.253	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.483
7	7.264	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.472
8	7.270	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.466
9	7.270	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.466
10	7.495	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	10.000	0.229	2.241
11	7.495	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.241
12	7.495	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.241
13	7.495	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.241
14	7.507	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.229
15	7.512	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.223
16	7.524	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.212
17	7.524	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.212
18	7.597	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	2.139
19	7.744	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	1.992
20	7.744	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	1.992
21	7.744	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	1.992
22	7.744	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	1.992
23	7.755	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.229	1.981
24	7.998	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	10.000	0.229	1.738
25	8.071	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk:[F]	clk:[R]	10.000	0.229	1.665

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	10.614	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.473
2	10.614	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.473
3	10.732	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.591
4	10.732	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.591
5	10.736	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.595
6	10.854	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.713
7	10.858	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.717
8	10.860	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.719
9	10.860	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.719
10	10.860	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.719
11	10.860	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.719
12	10.861	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.720
13	10.861	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.720
14	10.861	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.720
15	10.861	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.720
16	10.864	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.723
17	10.864	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.723
18	10.864	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.723
19	10.864	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.723
20	10.864	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.723
21	11.104	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.963
22	11.110	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.969
23	11.110	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.969
24	11.110	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.969
25	11.110	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.152	0.969

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	7.315	8.315	1.000	Low Pulse Width	clk	i_data_5_s0
2	7.315	8.315	1.000	Low Pulse Width	clk	i_data_3_s0
3	7.315	8.315	1.000	Low Pulse Width	clk	start_s0
4	7.315	8.315	1.000	Low Pulse Width	clk	Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_25_s0
5	7.315	8.315	1.000	Low Pulse Width	clk	Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_9_s0
6	7.315	8.315	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
7	7.315	8.315	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_14_s0
8	7.315	8.315	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
9	7.315	8.315	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
10	7.315	8.315	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_15_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.457
Data Arrival Time	62.832
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q
59.049	1.095	tNET	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
59.502	0.453	tINS	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
60.065	0.563	tNET	FF	1	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
60.635	0.570	tINS	FR	2	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
60.811	0.176	tNET	RR	1	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
61.381	0.570	tINS	RR	10	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
61.560	0.179	tNET	RR	1	R23C48[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
62.109	0.549	tINS	RR	1	R23C48[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
62.832	0.724	tNET	RR	1	R23C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R23C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
64.289	-0.035	tSu		1	R23C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 2.142, 41.915%; route: 2.736, 53.545%; tC2Q: 0.232, 4.540%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path2

Path Summary:

Slack	1.752
Data Arrival Time	62.538
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q
59.049	1.095	tNET	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
59.502	0.453	tINS	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
60.065	0.563	tNET	FF	1	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
60.635	0.570	tINS	FR	2	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
60.811	0.176	tNET	RR	1	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
61.366	0.555	tINS	RF	10	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
61.968	0.602	tNET	FF	1	R24C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n582_s1/I3
62.538	0.570	tINS	FR	1	R24C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n582_s1/F
62.538	0.000	tNET	RR	1	R24C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R24C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
64.289	-0.035	tSu		1	R24C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 2.148, 44.606%; route: 2.436, 50.576%; tC2Q: 0.232, 4.818%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path3

Path Summary:

Slack	1.752
Data Arrival Time	62.538
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q
59.049	1.095	tNET	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
59.502	0.453	tINS	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
60.065	0.563	tNET	FF	1	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
60.635	0.570	tINS	FR	2	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
60.811	0.176	tNET	RR	1	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
61.366	0.555	tINS	RF	10	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
61.968	0.602	tNET	FF	1	R24C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n580_s1/I3
62.538	0.570	tINS	FR	1	R24C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n580_s1/F
62.538	0.000	tNET	RR	1	R24C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R24C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
64.289	-0.035	tSu		1	R24C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 2.148, 44.606%; route: 2.436, 50.576%; tC2Q: 0.232, 4.818%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path4

Path Summary:

Slack	1.863
Data Arrival Time	62.427
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q
59.049	1.095	tNET	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
59.502	0.453	tINS	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
60.065	0.563	tNET	FF	1	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
60.635	0.570	tINS	FR	2	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
60.811	0.176	tNET	RR	1	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
61.366	0.555	tINS	RF	10	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
61.878	0.512	tNET	FF	1	R21C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n583_s1/I2
62.427	0.549	tINS	FR	1	R21C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n583_s1/F
62.427	0.000	tNET	RR	1	R21C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R21C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
64.289	-0.035	tSu		1	R21C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 2.127, 45.212%; route: 2.345, 49.856%; tC2Q: 0.232, 4.931%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path5

Path Summary:

Slack	1.918
Data Arrival Time	62.371
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q
59.049	1.095	tNET	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
59.502	0.453	tINS	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
60.065	0.563	tNET	FF	1	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
60.635	0.570	tINS	FR	2	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
60.811	0.176	tNET	RR	1	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
61.366	0.555	tINS	RF	10	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
61.801	0.435	tNET	FF	1	R25C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n576_s1/I3
62.371	0.570	tINS	FR	1	R25C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n576_s1/F
62.371	0.000	tNET	RR	1	R25C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R25C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
64.289	-0.035	tSu		1	R25C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 2.148, 46.206%; route: 2.269, 48.804%; tC2Q: 0.232, 4.991%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path6

Path Summary:

Slack	2.021
Data Arrival Time	62.269
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q
59.049	1.095	tNET	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
59.502	0.453	tINS	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
60.065	0.563	tNET	FF	1	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
60.635	0.570	tINS	FR	2	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
60.811	0.176	tNET	RR	1	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
61.366	0.555	tINS	RF	10	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
61.807	0.441	tNET	FF	1	R25C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n577_s1/I3
62.269	0.462	tINS	FR	1	R25C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n577_s1/F
62.269	0.000	tNET	RR	1	R25C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R25C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
64.289	-0.035	tSu		1	R25C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 2.040, 44.870%; route: 2.275, 50.028%; tC2Q: 0.232, 5.103%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path7

Path Summary:

Slack	2.106
Data Arrival Time	62.184
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q
59.049	1.095	tNET	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
59.502	0.453	tINS	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
60.065	0.563	tNET	FF	1	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
60.635	0.570	tINS	FR	2	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
60.811	0.176	tNET	RR	1	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
61.366	0.555	tINS	RF	10	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
61.635	0.269	tNET	FF	1	R21C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n581_s1/I3
62.184	0.549	tINS	FR	1	R21C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n581_s1/F
62.184	0.000	tNET	RR	1	R21C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R21C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
64.289	-0.035	tSu		1	R21C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 2.127, 47.672%; route: 2.103, 47.128%; tC2Q: 0.232, 5.200%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path8

Path Summary:

Slack	2.106
Data Arrival Time	62.184
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q
59.049	1.095	tNET	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
59.502	0.453	tINS	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
60.065	0.563	tNET	FF	1	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
60.635	0.570	tINS	FR	2	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
60.811	0.176	tNET	RR	1	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
61.366	0.555	tINS	RF	10	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
61.635	0.269	tNET	FF	1	R22C47[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n578_s1/I3
62.184	0.549	tINS	FR	1	R22C47[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n578_s1/F
62.184	0.000	tNET	RR	1	R22C47[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R22C47[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
64.289	-0.035	tSu		1	R22C47[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 2.127, 47.672%; route: 2.103, 47.128%; tC2Q: 0.232, 5.200%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path9

Path Summary:

Slack	2.112
Data Arrival Time	62.178
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q
59.049	1.095	tNET	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
59.502	0.453	tINS	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
60.065	0.563	tNET	FF	1	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
60.635	0.570	tINS	FR	2	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
60.811	0.176	tNET	RR	1	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
61.366	0.555	tINS	RF	10	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
61.807	0.441	tNET	FF	1	R25C47[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s2/I3
62.178	0.371	tINS	FF	1	R25C47[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s2/F
62.178	0.000	tNET	FF	1	R25C47[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R25C47[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
64.289	-0.035	tSu		1	R25C47[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.949, 43.744%; route: 2.275, 51.049%; tC2Q: 0.232, 5.207%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path10

Path Summary:

Slack	2.117
Data Arrival Time	62.172
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q
59.049	1.095	tNET	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
59.502	0.453	tINS	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
60.065	0.563	tNET	FF	1	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
60.635	0.570	tINS	FR	2	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
60.811	0.176	tNET	RR	1	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/I1
61.366	0.555	tINS	RF	10	R23C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s4/F
61.801	0.435	tNET	FF	1	R24C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n579_s1/I3
62.172	0.371	tINS	FF	1	R24C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n579_s1/F
62.172	0.000	tNET	FF	1	R24C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R24C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
64.289	-0.035	tSu		1	R24C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.949, 43.800%; route: 2.269, 50.986%; tC2Q: 0.232, 5.214%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path11

Path Summary:

Slack	2.447
Data Arrival Time	61.842
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_13_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R22C59[1][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_13_s0/CLK
57.954	0.232	tC2Q	RF	2	R22C59[1][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_13_s0/Q
58.960	1.006	tNET	FF	1	R22C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/I1
59.515	0.555	tINS	FF	1	R22C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/F
60.171	0.656	tNET	FF	1	R22C49[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I1
60.726	0.555	tINS	FF	3	R22C49[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
61.149	0.423	tNET	FF	1	R24C48[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/I1
61.698	0.549	tINS	FR	1	R24C48[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/F
61.842	0.144	tNET	RR	1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
64.289	-0.035	tSu		1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.659, 40.267%; route: 2.229, 54.102%; tC2Q: 0.232, 5.631%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path12

Path Summary:

Slack	2.591
Data Arrival Time	61.698
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_13_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R22C59[1][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_13_s0/CLK
57.954	0.232	tC2Q	RF	2	R22C59[1][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_13_s0/Q
58.960	1.006	tNET	FF	1	R22C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/I1
59.515	0.555	tINS	FF	1	R22C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/F
60.171	0.656	tNET	FF	1	R22C49[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I1
60.726	0.555	tINS	FF	3	R22C49[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
61.149	0.423	tNET	FF	1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s3/I1
61.698	0.549	tINS	FR	1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s3/F
61.698	0.000	tNET	RR	1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
64.289	-0.035	tSu		1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.659, 41.727%; route: 2.085, 52.437%; tC2Q: 0.232, 5.835%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path13

Path Summary:

Slack	2.769
Data Arrival Time	61.521
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_13_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R22C59[1][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_13_s0/CLK
57.954	0.232	tC2Q	RF	2	R22C59[1][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_13_s0/Q
58.960	1.006	tNET	FF	1	R22C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/I1
59.515	0.555	tINS	FF	1	R22C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/F
60.171	0.656	tNET	FF	1	R22C49[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I1
60.741	0.570	tINS	FR	3	R22C49[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
60.914	0.174	tNET	RR	1	R22C48[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I0
61.376	0.462	tINS	RR	1	R22C48[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
61.521	0.144	tNET	RR	1	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
64.289	-0.035	tSu		1	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.587, 41.779%; route: 1.980, 52.114%; tC2Q: 0.232, 6.108%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path14

Path Summary:

Slack	2.782
Data Arrival Time	61.507
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_windows_num_4_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C57[1][B]	gw_gao_inst_0/u_la0_top/capture_windows_num_4_s0/CLK
57.954	0.232	tC2Q	RF	8	R21C57[1][B]	gw_gao_inst_0/u_la0_top/capture_windows_num_4_s0/Q
58.972	1.018	tNET	FF	1	R23C46[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I1
59.489	0.517	tINS	FF	4	R23C46[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F
59.903	0.414	tNET	FF	1	R25C46[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s13/I3
60.473	0.570	tINS	FR	1	R25C46[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s13/F
60.474	0.001	tNET	RR	1	R25C46[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s11/I2
61.044	0.570	tINS	RR	1	R25C46[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s11/F
61.045	0.001	tNET	RR	1	R25C46[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/I2
61.507	0.462	tINS	RR	1	R25C46[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/F
61.507	0.000	tNET	RR	1	R25C46[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R25C46[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0
64.289	-0.035	tSu		1	R25C46[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 2.119, 55.982%; route: 1.434, 37.889%; tC2Q: 0.232, 6.129%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path15

Path Summary:

Slack	2.817
Data Arrival Time	61.472
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_windows_num_4_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C57[1][B]	gw_gao_inst_0/u_la0_top/capture_windows_num_4_s0/CLK
57.954	0.232	tC2Q	RF	8	R21C57[1][B]	gw_gao_inst_0/u_la0_top/capture_windows_num_4_s0/Q
58.972	1.018	tNET	FF	1	R23C46[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I1
59.521	0.549	tINS	FR	4	R23C46[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F
59.696	0.175	tNET	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/I3
60.266	0.570	tINS	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/F
60.268	0.001	tNET	RR	1	R22C46[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/I2
60.730	0.462	tINS	RR	1	R22C46[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/F
60.902	0.172	tNET	RR	1	R22C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I1
61.472	0.570	tINS	RR	1	R22C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F
61.472	0.000	tNET	RR	1	R22C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R22C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
64.289	-0.035	tSu		1	R22C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 2.151, 57.361%; route: 1.367, 36.452%; tC2Q: 0.232, 6.187%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path16

Path Summary:

Slack	2.880
Data Arrival Time	61.409
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_windows_num_9_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R23C58[2][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_9_s0/CLK
57.954	0.232	tC2Q	RF	7	R23C58[2][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_9_s0/Q
58.881	0.927	tNET	FF	1	R23C46[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_3_s7/I3
59.436	0.555	tINS	FF	4	R23C46[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_3_s7/F
60.097	0.660	tNET	FF	1	R24C46[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s11/I1
60.667	0.570	tINS	FR	1	R24C46[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s11/F
60.839	0.172	tNET	RR	1	R25C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s8/I3
61.409	0.570	tINS	RR	1	R25C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s8/F
61.409	0.000	tNET	RR	1	R25C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R25C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0
64.289	-0.035	tSu		1	R25C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.695, 45.973%; route: 1.760, 47.734%; tC2Q: 0.232, 6.292%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path17

Path Summary:

Slack	2.909
Data Arrival Time	61.381
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R21C56[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q
59.049	1.095	tNET	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/I3
59.502	0.453	tINS	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s11/F
60.065	0.563	tNET	FF	1	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/I2
60.635	0.570	tINS	FR	2	R22C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n575_s6/F
60.811	0.176	tNET	RR	1	R23C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n584_s2/I2
61.381	0.570	tINS	RR	1	R23C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n584_s2/F
61.381	0.000	tNET	RR	1	R23C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R23C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
64.289	-0.035	tSu		1	R23C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.593, 43.540%; route: 1.834, 50.119%; tC2Q: 0.232, 6.341%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path18

Path Summary:

Slack	2.970
Data Arrival Time	61.320
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R22C56[2][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/CLK
57.954	0.232	tC2Q	RF	5	R22C56[2][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/Q
58.624	0.670	tNET	FF	2	R25C57[1][A]	gw_gao_inst_0/u_la0_top/n2910_s21/I0
59.173	0.549	tINS	FR	1	R25C57[1][A]	gw_gao_inst_0/u_la0_top/n2910_s21/COUT
59.173	0.000	tNET	RR	2	R25C57[1][B]	gw_gao_inst_0/u_la0_top/n2910_s22/CIN
59.209	0.035	tINS	RF	1	R25C57[1][B]	gw_gao_inst_0/u_la0_top/n2910_s22/COUT
59.209	0.000	tNET	FF	2	R25C57[2][A]	gw_gao_inst_0/u_la0_top/n2910_s23/CIN
59.244	0.035	tINS	FF	1	R25C57[2][A]	gw_gao_inst_0/u_la0_top/n2910_s23/COUT
59.244	0.000	tNET	FF	2	R25C57[2][B]	gw_gao_inst_0/u_la0_top/n2910_s24/CIN
59.279	0.035	tINS	FF	1	R25C57[2][B]	gw_gao_inst_0/u_la0_top/n2910_s24/COUT
59.279	0.000	tNET	FF	2	R25C58[0][A]	gw_gao_inst_0/u_la0_top/n2910_s25/CIN
59.314	0.035	tINS	FF	1	R25C58[0][A]	gw_gao_inst_0/u_la0_top/n2910_s25/COUT
59.314	0.000	tNET	FF	2	R25C58[0][B]	gw_gao_inst_0/u_la0_top/n2910_s26/CIN
59.349	0.035	tINS	FF	1	R25C58[0][B]	gw_gao_inst_0/u_la0_top/n2910_s26/COUT
59.349	0.000	tNET	FF	2	R25C58[1][A]	gw_gao_inst_0/u_la0_top/n2910_s27/CIN
59.385	0.035	tINS	FF	1	R25C58[1][A]	gw_gao_inst_0/u_la0_top/n2910_s27/COUT
59.385	0.000	tNET	FF	2	R25C58[1][B]	gw_gao_inst_0/u_la0_top/n2910_s28/CIN
59.420	0.035	tINS	FF	2	R25C58[1][B]	gw_gao_inst_0/u_la0_top/n2910_s28/COUT
60.307	0.888	tNET	FF	1	R24C57[3][A]	gw_gao_inst_0/u_la0_top/start_reg1_s1/I1
60.856	0.549	tINS	FR	1	R24C57[3][A]	gw_gao_inst_0/u_la0_top/start_reg1_s1/F
60.858	0.001	tNET	RR	1	R24C57[2][A]	gw_gao_inst_0/u_la0_top/start_reg1_s0/I0
61.320	0.462	tINS	RR	1	R24C57[2][A]	gw_gao_inst_0/u_la0_top/start_reg1_s0/F
61.320	0.000	tNET	RR	1	R24C57[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R24C57[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/start_reg_s0
64.289	-0.035	tSu		1	R24C57[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.806, 50.210%; route: 1.559, 43.341%; tC2Q: 0.232, 6.449%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path19

Path Summary:

Slack	3.208
Data Arrival Time	61.081
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R24C59[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R24C59[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q
58.612	0.658	tNET	FF	2	R25C56[1][B]	gw_gao_inst_0/u_la0_top/n2938_s0/I1
59.182	0.570	tINS	FR	1	R25C56[1][B]	gw_gao_inst_0/u_la0_top/n2938_s0/COUT
59.182	0.000	tNET	RR	2	R25C56[2][A]	gw_gao_inst_0/u_la0_top/n2939_s0/CIN
59.217	0.035	tINS	RF	6	R25C56[2][A]	gw_gao_inst_0/u_la0_top/n2939_s0/COUT
59.705	0.488	tNET	FF	1	R25C56[3][A]	gw_gao_inst_0/u_la0_top/n2980_s1/I0
60.254	0.549	tINS	FR	1	R25C56[3][A]	gw_gao_inst_0/u_la0_top/n2980_s1/F
60.426	0.172	tNET	RR	1	R24C56[2][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
60.753	0.327	tINS	RR	1	R24C56[2][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
61.081	0.328	tNET	RR	1	R26C56[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R26C56[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
64.289	-0.035	tSu		1	R26C56[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.481, 44.094%; route: 1.646, 49.000%; tC2Q: 0.232, 6.906%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path20

Path Summary:

Slack	3.517
Data Arrival Time	60.773
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_windows_num_9_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R23C58[2][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_9_s0/CLK
57.954	0.232	tC2Q	RF	7	R23C58[2][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_9_s0/Q
58.881	0.927	tNET	FF	1	R23C46[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_3_s7/I3
59.451	0.570	tINS	FR	4	R23C46[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_3_s7/F
59.631	0.180	tNET	RR	1	R22C46[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s8/I1
60.201	0.570	tINS	RR	1	R22C46[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s8/F
60.203	0.001	tNET	RR	1	R22C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s7/I2
60.773	0.570	tINS	RR	1	R22C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s7/F
60.773	0.000	tNET	RR	1	R22C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R22C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0
64.289	-0.035	tSu		1	R22C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.710, 56.054%; route: 1.109, 36.342%; tC2Q: 0.232, 7.605%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path21

Path Summary:

Slack	3.673
Data Arrival Time	60.616
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_windows_num_9_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_4_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R23C58[2][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_9_s0/CLK
57.954	0.232	tC2Q	RF	7	R23C58[2][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_9_s0/Q
58.822	0.868	tNET	FF	1	R24C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_2_s2/I1
59.377	0.555	tINS	FF	3	R24C47[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_2_s2/F
60.046	0.669	tNET	FF	1	R21C46[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_4_s5/I3
60.616	0.570	tINS	FR	1	R21C46[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_4_s5/F
60.616	0.000	tNET	RR	1	R21C46[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R21C46[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_4_s0/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_4_s0
64.289	-0.035	tSu		1	R21C46[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_4_s0

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.125, 38.871%; route: 1.537, 53.113%; tC2Q: 0.232, 8.016%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path22

Path Summary:

Slack	3.700
Data Arrival Time	60.589
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_3_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R21C57[2][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/CLK
57.954	0.232	tC2Q	RF	8	R21C57[2][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q
59.147	1.193	tNET	FF	1	R24C46[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_2_s3/I0
59.600	0.453	tINS	FF	5	R24C46[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_2_s3/F
60.019	0.419	tNET	FF	1	R22C46[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_3_s5/I2
60.589	0.570	tINS	FR	1	R22C46[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_3_s5/F
60.589	0.000	tNET	RR	1	R22C46[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R22C46[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_3_s0/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_3_s0
64.289	-0.035	tSu		1	R22C46[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_3_s0

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.023, 35.677%; route: 1.612, 56.232%; tC2Q: 0.232, 8.091%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path23

Path Summary:

Slack	3.860
Data Arrival Time	60.429
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R24C59[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R24C59[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q
58.612	0.658	tNET	FF	2	R25C56[1][B]	gw_gao_inst_0/u_la0_top/n2938_s0/I1
59.182	0.570	tINS	FR	1	R25C56[1][B]	gw_gao_inst_0/u_la0_top/n2938_s0/COUT
59.182	0.000	tNET	RR	2	R25C56[2][A]	gw_gao_inst_0/u_la0_top/n2939_s0/CIN
59.217	0.035	tINS	RF	6	R25C56[2][A]	gw_gao_inst_0/u_la0_top/n2939_s0/COUT
59.880	0.663	tNET	FF	1	R25C55[2][A]	gw_gao_inst_0/u_la0_top/n2961_s3/I0
60.429	0.549	tINS	FR	1	R25C55[2][A]	gw_gao_inst_0/u_la0_top/n2961_s3/F
60.429	0.000	tNET	RR	1	R25C55[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R25C55[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
64.289	-0.035	tSu		1	R25C55[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.154, 42.639%; route: 1.321, 48.790%; tC2Q: 0.232, 8.571%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path24

Path Summary:

Slack	3.860
Data Arrival Time	60.429
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R24C59[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R24C59[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q
58.612	0.658	tNET	FF	2	R25C56[1][B]	gw_gao_inst_0/u_la0_top/n2938_s0/I1
59.182	0.570	tINS	FR	1	R25C56[1][B]	gw_gao_inst_0/u_la0_top/n2938_s0/COUT
59.182	0.000	tNET	RR	2	R25C56[2][A]	gw_gao_inst_0/u_la0_top/n2939_s0/CIN
59.217	0.035	tINS	RF	6	R25C56[2][A]	gw_gao_inst_0/u_la0_top/n2939_s0/COUT
59.880	0.663	tNET	FF	1	R25C55[2][B]	gw_gao_inst_0/u_la0_top/n2980_s2/I1
60.429	0.549	tINS	FR	1	R25C55[2][B]	gw_gao_inst_0/u_la0_top/n2980_s2/F
60.429	0.000	tNET	RR	1	R25C55[2][B]	gw_gao_inst_0/u_la0_top/triger_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R25C55[2][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_s0
64.289	-0.035	tSu		1	R25C55[2][B]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.154, 42.639%; route: 1.321, 48.790%; tC2Q: 0.232, 8.571%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path25

Path Summary:

Slack	3.947
Data Arrival Time	60.342
Data Required Time	64.289
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/I
54.230	4.230	tINS	RR	1	IOR43[A]	gw_gao_inst_0/tck_ibuf/O
54.230	0.000	tNET	RR	1	R45C87	gw_gao_inst_0/u_gw_jtag/tck_pad_i
54.912	0.683	tINS	RR	380	R45C87	gw_gao_inst_0/u_gw_jtag/tck_o
57.722	2.810	tNET	RR	1	R24C59[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/CLK
57.954	0.232	tC2Q	RF	2	R24C59[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q
58.612	0.658	tNET	FF	2	R25C56[1][B]	gw_gao_inst_0/u_la0_top/n2938_s0/I1
59.182	0.570	tINS	FR	1	R25C56[1][B]	gw_gao_inst_0/u_la0_top/n2938_s0/COUT
59.182	0.000	tNET	RR	2	R25C56[2][A]	gw_gao_inst_0/u_la0_top/n2939_s0/CIN
59.217	0.035	tINS	RF	6	R25C56[2][A]	gw_gao_inst_0/u_la0_top/n2939_s0/COUT
59.880	0.663	tNET	FF	1	R25C55[0][A]	gw_gao_inst_0/u_la0_top/n2960_s1/I3
60.342	0.462	tINS	FR	1	R25C55[0][A]	gw_gao_inst_0/u_la0_top/n2960_s1/F
60.342	0.000	tNET	RR	1	R25C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					clk
60.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
62.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
64.359	2.271	tNET	RR	1	R25C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
64.324	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
64.289	-0.035	tSu		1	R25C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-3.363
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay	cell: 1.067, 40.734%; route: 1.321, 50.410%; tC2Q: 0.232, 8.855%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.076
Data Arrival Time	3.228
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R12C44[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/CLK
3.105	0.202	tC2Q	RR	1	R12C44[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q
3.228	0.123	tNET	RR	1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path2

Path Summary:

Slack	0.076
Data Arrival Time	3.228
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R12C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/CLK
3.105	0.202	tC2Q	RR	1	R12C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q
3.228	0.123	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path3

Path Summary:

Slack	0.192
Data Arrival Time	3.105
Data Required Time	2.913
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
3.105	0.202	tC2Q	RR	12	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
3.105	0.000	tNET	RR	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
2.913	0.010	tHld		1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path4

Path Summary:

Slack	0.192
Data Arrival Time	3.105
Data Required Time	2.913
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
3.105	0.202	tC2Q	RR	12	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
3.105	0.000	tNET	RR	1	BSRAM_R36[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R36[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
2.913	0.010	tHld		1	BSRAM_R36[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path5

Path Summary:

Slack	0.192
Data Arrival Time	3.105
Data Required Time	2.913
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
3.105	0.202	tC2Q	RR	12	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
3.105	0.000	tNET	RR	1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
2.913	0.010	tHld		1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path6

Path Summary:

Slack	0.192
Data Arrival Time	3.105
Data Required Time	2.913
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
3.105	0.202	tC2Q	RR	12	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
3.105	0.000	tNET	RR	1	BSRAM_R36[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R36[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
2.913	0.010	tHld		1	BSRAM_R36[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path7

Path Summary:

Slack	0.192
Data Arrival Time	3.105
Data Required Time	2.913
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
3.105	0.202	tC2Q	RR	12	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
3.105	0.000	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
2.913	0.010	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path8

Path Summary:

Slack	0.202
Data Arrival Time	3.354
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R12C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/CLK
3.105	0.202	tC2Q	RR	1	R12C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/Q
3.354	0.249	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path9

Path Summary:

Slack	0.202
Data Arrival Time	3.354
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R12C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/CLK
3.105	0.202	tC2Q	RR	1	R12C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q
3.354	0.249	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path10

Path Summary:

Slack	0.202
Data Arrival Time	3.354
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R12C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK
3.105	0.202	tC2Q	RR	1	R12C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q
3.354	0.249	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path11

Path Summary:

Slack	0.213
Data Arrival Time	3.366
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R11C40[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/CLK
3.105	0.202	tC2Q	RR	1	R11C40[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q
3.366	0.260	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path12

Path Summary:

Slack	0.213
Data Arrival Time	3.366
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R12C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/CLK
3.105	0.202	tC2Q	RR	1	R12C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/Q
3.366	0.260	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path13

Path Summary:

Slack	0.213
Data Arrival Time	3.366
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R11C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/CLK
3.105	0.202	tC2Q	RR	1	R11C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/Q
3.366	0.260	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path14

Path Summary:

Slack	0.213
Data Arrival Time	3.366
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R11C40[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0/CLK
3.105	0.202	tC2Q	RR	1	R11C40[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0/Q
3.366	0.260	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path15

Path Summary:

Slack	0.213
Data Arrival Time	3.366
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R11C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/CLK
3.105	0.202	tC2Q	RR	1	R11C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q
3.366	0.260	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path16

Path Summary:

Slack	0.213
Data Arrival Time	3.366
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R11C40[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/CLK
3.105	0.202	tC2Q	RR	1	R11C40[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q
3.366	0.260	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path17

Path Summary:

Slack	0.225
Data Arrival Time	3.378
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_67_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R11C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_67_s0/CLK
3.105	0.202	tC2Q	RR	1	R11C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_67_s0/Q
3.378	0.272	tNET	RR	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path18

Path Summary:

Slack	0.335
Data Arrival Time	3.488
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_68_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R11C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_68_s0/CLK
3.105	0.202	tC2Q	RR	1	R11C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_68_s0/Q
3.488	0.382	tNET	RR	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path19

Path Summary:

Slack	0.335
Data Arrival Time	3.488
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R11C39[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/CLK
3.105	0.202	tC2Q	RR	1	R11C39[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q
3.488	0.382	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path20

Path Summary:

Slack	0.335
Data Arrival Time	3.488
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R11C39[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/CLK
3.105	0.202	tC2Q	RR	1	R11C39[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q
3.488	0.382	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path21

Path Summary:

Slack	0.335
Data Arrival Time	3.488
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R11C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/CLK
3.105	0.202	tC2Q	RR	1	R11C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q
3.488	0.382	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path22

Path Summary:

Slack	0.335
Data Arrival Time	3.488
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R11C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/CLK
3.105	0.202	tC2Q	RR	1	R11C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q
3.488	0.382	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path23

Path Summary:

Slack	0.347
Data Arrival Time	3.500
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R24C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/CLK
3.105	0.202	tC2Q	RR	1	R24C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q
3.500	0.394	tNET	RR	1	BSRAM_R36[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R36[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
3.152	0.249	tHld		1	BSRAM_R36[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path24

Path Summary:

Slack	0.363
Data Arrival Time	3.515
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_70_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R11C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_70_s0/CLK
3.105	0.202	tC2Q	RR	1	R11C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_70_s0/Q
3.515	0.410	tNET	RR	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path25

Path Summary:

Slack	0.363
Data Arrival Time	3.515
Data Required Time	3.152
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R11C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/CLK
3.105	0.202	tC2Q	RR	1	R11C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/Q
3.515	0.410	tNET	RR	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
3.152	0.249	tHld		1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.750
Data Arrival Time	17.574
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
17.574	2.754	tNET	FF	1	R25C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R25C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
24.324	-0.035	tSu		1	R25C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.754, 92.230%; tC2Q: 0.232, 7.770%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path2

Path Summary:

Slack	6.750
Data Arrival Time	17.574
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
17.574	2.754	tNET	FF	1	R25C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R25C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
24.324	-0.035	tSu		1	R25C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.754, 92.230%; tC2Q: 0.232, 7.770%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path3

Path Summary:

Slack	6.750
Data Arrival Time	17.574
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
17.574	2.754	tNET	FF	1	R25C47[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R25C47[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
24.324	-0.035	tSu		1	R25C47[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.754, 92.230%; tC2Q: 0.232, 7.770%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path4

Path Summary:

Slack	6.761
Data Arrival Time	17.563
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
17.563	2.743	tNET	FF	1	R24C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R24C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
24.324	-0.035	tSu		1	R24C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.743, 92.201%; tC2Q: 0.232, 7.799%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path5

Path Summary:

Slack	7.247
Data Arrival Time	17.078
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
17.078	2.257	tNET	FF	1	R23C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R23C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
24.324	-0.035	tSu		1	R23C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.257, 90.679%; tC2Q: 0.232, 9.321%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path6

Path Summary:

Slack	7.253
Data Arrival Time	17.072
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
17.072	2.251	tNET	FF	1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
24.324	-0.035	tSu		1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.251, 90.658%; tC2Q: 0.232, 9.342%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path7

Path Summary:

Slack	7.264
Data Arrival Time	17.060
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
17.060	2.240	tNET	FF	1	R23C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R23C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
24.324	-0.035	tSu		1	R23C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.240, 90.615%; tC2Q: 0.232, 9.385%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path8

Path Summary:

Slack	7.270
Data Arrival Time	17.055
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
17.055	2.234	tNET	FF	1	R24C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R24C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
24.324	-0.035	tSu		1	R24C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.234, 90.593%; tC2Q: 0.232, 9.407%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path9

Path Summary:

Slack	7.270
Data Arrival Time	17.055
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
17.055	2.234	tNET	FF	1	R24C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R24C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
24.324	-0.035	tSu		1	R24C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.234, 90.593%; tC2Q: 0.232, 9.407%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path10

Path Summary:

Slack	7.495
Data Arrival Time	16.829
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.829	2.009	tNET	FF	1	R22C48[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R22C48[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
24.324	-0.035	tSu		1	R22C48[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.009, 89.646%; tC2Q: 0.232, 10.354%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path11

Path Summary:

Slack	7.495
Data Arrival Time	16.829
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.829	2.009	tNET	FF	1	R22C48[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R22C48[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
24.324	-0.035	tSu		1	R22C48[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.009, 89.646%; tC2Q: 0.232, 10.354%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path12

Path Summary:

Slack	7.495
Data Arrival Time	16.829
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.829	2.009	tNET	FF	1	R22C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R22C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
24.324	-0.035	tSu		1	R22C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.009, 89.646%; tC2Q: 0.232, 10.354%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path13

Path Summary:

Slack	7.495
Data Arrival Time	16.829
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.829	2.009	tNET	FF	1	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
24.324	-0.035	tSu		1	R22C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.009, 89.646%; tC2Q: 0.232, 10.354%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path14

Path Summary:

Slack	7.507
Data Arrival Time	16.818
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.818	1.997	tNET	FF	1	R22C47[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R22C47[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
24.324	-0.035	tSu		1	R22C47[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.997, 89.593%; tC2Q: 0.232, 10.407%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path15

Path Summary:

Slack	7.512
Data Arrival Time	16.812
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.812	1.991	tNET	FF	1	R22C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R22C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
24.324	-0.035	tSu		1	R22C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.991, 89.566%; tC2Q: 0.232, 10.434%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path16

Path Summary:

Slack	7.524
Data Arrival Time	16.800
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.800	1.980	tNET	FF	1	R21C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R21C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
24.324	-0.035	tSu		1	R21C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.980, 89.512%; tC2Q: 0.232, 10.488%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path17

Path Summary:

Slack	7.524
Data Arrival Time	16.800
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.800	1.980	tNET	FF	1	R21C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R21C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
24.324	-0.035	tSu		1	R21C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.980, 89.512%; tC2Q: 0.232, 10.488%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path18

Path Summary:

Slack	7.597
Data Arrival Time	16.727
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.727	1.907	tNET	FF	1	R21C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R21C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
24.324	-0.035	tSu		1	R21C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.907, 89.154%; tC2Q: 0.232, 10.846%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path19

Path Summary:

Slack	7.744
Data Arrival Time	16.581
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.581	1.760	tNET	FF	1	R21C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R21C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
24.324	-0.035	tSu		1	R21C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.760, 88.355%; tC2Q: 0.232, 11.645%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path20

Path Summary:

Slack	7.744
Data Arrival Time	16.581
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.581	1.760	tNET	FF	1	R21C48[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R21C48[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
24.324	-0.035	tSu		1	R21C48[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.760, 88.355%; tC2Q: 0.232, 11.645%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path21

Path Summary:

Slack	7.744
Data Arrival Time	16.581
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.581	1.760	tNET	FF	1	R21C48[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R21C48[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
24.324	-0.035	tSu		1	R21C48[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.760, 88.355%; tC2Q: 0.232, 11.645%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path22

Path Summary:

Slack	7.744
Data Arrival Time	16.581
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.581	1.760	tNET	FF	1	R21C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R21C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
24.324	-0.035	tSu		1	R21C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.760, 88.355%; tC2Q: 0.232, 11.645%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path23

Path Summary:

Slack	7.755
Data Arrival Time	16.569
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.569	1.749	tNET	FF	1	R21C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R21C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
24.324	-0.035	tSu		1	R21C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.749, 88.287%; tC2Q: 0.232, 11.713%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path24

Path Summary:

Slack	7.998
Data Arrival Time	16.326
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.326	1.506	tNET	FF	1	R21C46[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R21C46[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
24.324	-0.035	tSu		1	R21C46[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.506, 86.651%; tC2Q: 0.232, 13.349%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Path25

Path Summary:

Slack	8.071
Data Arrival Time	16.253
Data Required Time	24.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
12.314	2.314	tINS	FF	257	IOR44[A]	clk_ibuf/O
14.588	2.274	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
14.820	0.232	tC2Q	FF	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.253	1.433	tNET	FF	1	R21C55[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
22.088	2.088	tINS	RR	257	IOR44[A]	clk_ibuf/O
24.359	2.271	tNET	RR	1	R21C55[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
24.324	-0.035	tSu		1	R21C55[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	-0.229
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 2.314, 50.432%; route: 2.274, 49.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.433, 86.066%; tC2Q: 0.232, 13.934%
Required Clock Path Delay	cell: 2.088, 47.897%; route: 2.271, 52.103%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	10.614
Data Arrival Time	13.528
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.528	0.271	tNET	RR	1	R24C57[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R24C57[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
2.914	0.011	tHld		1	R24C57[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.259%; tC2Q: 0.202, 42.741%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path2

Path Summary:

Slack	10.614
Data Arrival Time	13.528
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.528	0.271	tNET	RR	1	R24C57[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R24C57[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
2.914	0.011	tHld		1	R24C57[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.259%; tC2Q: 0.202, 42.741%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path3

Path Summary:

Slack	10.732
Data Arrival Time	13.646
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.646	0.389	tNET	RR	1	R23C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R23C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
2.914	0.011	tHld		1	R23C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.389, 65.817%; tC2Q: 0.202, 34.183%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path4

Path Summary:

Slack	10.732
Data Arrival Time	13.646
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.646	0.389	tNET	RR	1	R23C56[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R23C56[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
2.914	0.011	tHld		1	R23C56[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.389, 65.817%; tC2Q: 0.202, 34.183%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path5

Path Summary:

Slack	10.736
Data Arrival Time	13.650
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.650	0.393	tNET	RR	1	R24C56[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R24C56[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
2.914	0.011	tHld		1	R24C56[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.393, 66.028%; tC2Q: 0.202, 33.972%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path6

Path Summary:

Slack	10.854
Data Arrival Time	13.768
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.768	0.511	tNET	RR	1	R21C56[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R21C56[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
2.914	0.011	tHld		1	R21C56[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.511, 71.667%; tC2Q: 0.202, 28.333%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path7

Path Summary:

Slack	10.858
Data Arrival Time	13.772
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.772	0.515	tNET	RR	1	R26C56[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R26C56[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
2.914	0.011	tHld		1	R26C56[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.515, 71.812%; tC2Q: 0.202, 28.188%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path8

Path Summary:

Slack	10.860
Data Arrival Time	13.774
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.774	0.517	tNET	RR	1	R22C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R22C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
2.914	0.011	tHld		1	R22C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.517, 71.903%; tC2Q: 0.202, 28.097%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path9

Path Summary:

Slack	10.860
Data Arrival Time	13.774
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.774	0.517	tNET	RR	1	R22C56[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R22C56[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
2.914	0.011	tHld		1	R22C56[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.517, 71.903%; tC2Q: 0.202, 28.097%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path10

Path Summary:

Slack	10.860
Data Arrival Time	13.774
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.774	0.517	tNET	RR	1	R22C56[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R22C56[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
2.914	0.011	tHld		1	R22C56[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.517, 71.903%; tC2Q: 0.202, 28.097%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path11

Path Summary:

Slack	10.860
Data Arrival Time	13.774
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.774	0.517	tNET	RR	1	R22C56[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R22C56[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
2.914	0.011	tHld		1	R22C56[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.517, 71.903%; tC2Q: 0.202, 28.097%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path12

Path Summary:

Slack	10.861
Data Arrival Time	13.775
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.775	0.518	tNET	RR	1	R22C55[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R22C55[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
2.914	0.011	tHld		1	R22C55[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.518, 71.929%; tC2Q: 0.202, 28.071%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path13

Path Summary:

Slack	10.861
Data Arrival Time	13.775
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.775	0.518	tNET	RR	1	R22C55[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R22C55[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
2.914	0.011	tHld		1	R22C55[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.518, 71.929%; tC2Q: 0.202, 28.071%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path14

Path Summary:

Slack	10.861
Data Arrival Time	13.775
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.775	0.518	tNET	RR	1	R22C55[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R22C55[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
2.914	0.011	tHld		1	R22C55[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.518, 71.929%; tC2Q: 0.202, 28.071%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path15

Path Summary:

Slack	10.861
Data Arrival Time	13.775
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.775	0.518	tNET	RR	1	R22C55[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R22C55[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
2.914	0.011	tHld		1	R22C55[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.518, 71.929%; tC2Q: 0.202, 28.071%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path16

Path Summary:

Slack	10.864
Data Arrival Time	13.778
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.778	0.521	tNET	RR	1	R25C55[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R25C55[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
2.914	0.011	tHld		1	R25C55[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.521, 72.046%; tC2Q: 0.202, 27.954%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path17

Path Summary:

Slack	10.864
Data Arrival Time	13.778
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.778	0.521	tNET	RR	1	R25C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R25C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
2.914	0.011	tHld		1	R25C55[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.521, 72.046%; tC2Q: 0.202, 27.954%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path18

Path Summary:

Slack	10.864
Data Arrival Time	13.778
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.778	0.521	tNET	RR	1	R25C55[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R25C55[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
2.914	0.011	tHld		1	R25C55[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.521, 72.046%; tC2Q: 0.202, 27.954%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path19

Path Summary:

Slack	10.864
Data Arrival Time	13.778
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.778	0.521	tNET	RR	1	R25C55[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R25C55[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
2.914	0.011	tHld		1	R25C55[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.521, 72.046%; tC2Q: 0.202, 27.954%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path20

Path Summary:

Slack	10.864
Data Arrival Time	13.778
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.778	0.521	tNET	RR	1	R25C55[2][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R25C55[2][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
2.914	0.011	tHld		1	R25C55[2][B]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.521, 72.046%; tC2Q: 0.202, 27.954%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path21

Path Summary:

Slack	11.104
Data Arrival Time	14.018
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.018	0.761	tNET	RR	1	R21C54[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R21C54[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
2.914	0.011	tHld		1	R21C54[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.761, 79.023%; tC2Q: 0.202, 20.977%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path22

Path Summary:

Slack	11.110
Data Arrival Time	14.024
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.024	0.767	tNET	RR	1	R21C55[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R21C55[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
2.914	0.011	tHld		1	R21C55[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.767, 79.153%; tC2Q: 0.202, 20.847%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path23

Path Summary:

Slack	11.110
Data Arrival Time	14.024
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.024	0.767	tNET	RR	1	R21C55[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R21C55[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
2.914	0.011	tHld		1	R21C55[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.767, 79.153%; tC2Q: 0.202, 20.847%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path24

Path Summary:

Slack	11.110
Data Arrival Time	14.024
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.024	0.767	tNET	RR	1	R21C55[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R21C55[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
2.914	0.011	tHld		1	R21C55[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.767, 79.153%; tC2Q: 0.202, 20.847%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path25

Path Summary:

Slack	11.110
Data Arrival Time	14.024
Data Required Time	2.914
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
11.542	1.542	tINS	FF	257	IOR44[A]	clk_ibuf/O
13.056	1.514	tNET	FF	1	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.258	0.202	tC2Q	FR	53	R25C59[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.024	0.767	tNET	RR	1	R21C55[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
1.392	1.392	tINS	RR	257	IOR44[A]	clk_ibuf/O
2.903	1.511	tNET	RR	1	R21C55[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
2.914	0.011	tHld		1	R21C55[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	-0.152
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.542, 50.466%; route: 1.514, 49.534%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.767, 79.153%; tC2Q: 0.202, 20.847%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	7.315
Actual Width:	8.315
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	i_data_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.314	2.314	tINS	FF	clk_ibuf/O
14.588	2.274	tNET	FF	i_data_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
21.392	1.392	tINS	RR	clk_ibuf/O
22.903	1.511	tNET	RR	i_data_5_s0/CLK

MPW2

MPW Summary:

Slack:	7.315
Actual Width:	8.315
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	i_data_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.314	2.314	tINS	FF	clk_ibuf/O
14.588	2.274	tNET	FF	i_data_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
21.392	1.392	tINS	RR	clk_ibuf/O
22.903	1.511	tNET	RR	i_data_3_s0/CLK

MPW3

MPW Summary:

Slack:	7.315
Actual Width:	8.315
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	start_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.314	2.314	tINS	FF	clk_ibuf/O
14.588	2.274	tNET	FF	start_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
21.392	1.392	tINS	RR	clk_ibuf/O
22.903	1.511	tNET	RR	start_s0/CLK

MPW4

MPW Summary:

Slack:	7.315
Actual Width:	8.315
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_25_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.314	2.314	tINS	FF	clk_ibuf/O
14.588	2.274	tNET	FF	Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_25_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
21.392	1.392	tINS	RR	clk_ibuf/O
22.903	1.511	tNET	RR	Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_25_s0/CLK

MPW5

MPW Summary:

Slack:	7.315
Actual Width:	8.315
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.314	2.314	tINS	FF	clk_ibuf/O
14.588	2.274	tNET	FF	Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
21.392	1.392	tINS	RR	clk_ibuf/O
22.903	1.511	tNET	RR	Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_9_s0/CLK

MPW6

MPW Summary:

Slack:	7.315
Actual Width:	8.315
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.314	2.314	tINS	FF	clk_ibuf/O
14.588	2.274	tNET	FF	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
21.392	1.392	tINS	RR	clk_ibuf/O
22.903	1.511	tNET	RR	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK

MPW7

MPW Summary:

Slack:	7.315
Actual Width:	8.315
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_14_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.314	2.314	tINS	FF	clk_ibuf/O
14.588	2.274	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_14_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
21.392	1.392	tINS	RR	clk_ibuf/O
22.903	1.511	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_14_s0/CLK

MPW8

MPW Summary:

Slack:	7.315
Actual Width:	8.315
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.314	2.314	tINS	FF	clk_ibuf/O
14.588	2.274	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
21.392	1.392	tINS	RR	clk_ibuf/O
22.903	1.511	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK

MPW9

MPW Summary:

Slack:	7.315
Actual Width:	8.315
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.314	2.314	tINS	FF	clk_ibuf/O
14.588	2.274	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
21.392	1.392	tINS	RR	clk_ibuf/O
22.903	1.511	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK

MPW10

MPW Summary:

Slack:	7.315
Actual Width:	8.315
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_15_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.314	2.314	tINS	FF	clk_ibuf/O
14.588	2.274	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_15_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
21.392	1.392	tINS	RR	clk_ibuf/O
22.903	1.511	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_15_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
380	control0[0]	1.457	2.925
257	clk_d	4.821	2.274
96	n20_3	46.090	1.870
83	data_a_d[23]	6.377	4.256
76	data_out_shift_reg_73_7	43.544	2.965
66	n897_4	43.292	1.565
66	n897_5	44.527	1.459
62	data_a_d[24]	6.721	1.951
55	jtag_strobe_i	43.765	1.889
53	rst_ao	6.750	2.754

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R22C58	88.89%
R22C55	87.50%
R22C56	87.50%
R21C35	86.11%
R22C57	84.72%
R11C47	83.33%
R25C55	83.33%
R11C42	83.33%
R21C49	83.33%
R22C49	81.94%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]