Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_Float_to_Fixed_RefDesign\Proj\src\float_to_fixed\float_to_fixed.v E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_Float_to_Fixed_RefDesign\Proj\src\top.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_Float_to_Fixed_RefDesign\Proj\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11 (64-bit) |
| Part Number | GW2A-LV55PG484C8/I7 |
| Device | GW2A-55 |
| Created Time | Tue Dec 24 09:08:57 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.382s, Peak memory usage = 828.586MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 828.586MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 828.586MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 828.586MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 828.586MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 828.586MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 828.586MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 828.586MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 828.586MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 828.586MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 828.586MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 828.586MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.107s, Peak memory usage = 828.586MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 828.586MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 828.586MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 70 |
| I/O Buf | 70 |
| IBUF | 5 |
| OBUF | 65 |
| Register | 576 |
| DFF | 156 |
| DFFR | 1 |
| DFFP | 3 |
| DFFPE | 33 |
| DFFC | 67 |
| DFFCE | 316 |
| LUT | 851 |
| LUT2 | 81 |
| LUT3 | 201 |
| LUT4 | 569 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 19 |
| ALU | 19 |
| INV | 6 |
| INV | 6 |
| BSRAM | 6 |
| SDPB | 5 |
| pROM | 1 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 884(865 LUT, 19 ALU) / 54720 | 2% |
| Register | 576 / 42000 | 2% |
| --Register as Latch | 0 / 42000 | 0% |
| --Register as FF | 576 / 42000 | 2% |
| BSRAM | 6 / 140 | 5% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 100.000(MHz) | 71.695(MHz) | 12 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -3.948 |
| Data Arrival Time | 14.273 |
| Data Required Time | 10.325 |
| From | mem_data_1_mem_data_1_0_0_s |
| To | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_17_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 257 | clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 32 | mem_data_1_mem_data_1_0_0_s/CLK |
| 2.620 | 2.260 | tC2Q | RF | 6 | mem_data_1_mem_data_1_0_0_s/DO[16] |
| 3.094 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n8_s2/I1 |
| 3.649 | 0.555 | tINS | FF | 6 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n8_s2/F |
| 4.123 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s5/I1 |
| 4.678 | 0.555 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s5/F |
| 5.152 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s3/I1 |
| 5.707 | 0.555 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s3/F |
| 6.181 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n885_s16/I2 |
| 6.634 | 0.453 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n885_s16/F |
| 7.108 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s5/I1 |
| 7.663 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s5/F |
| 8.137 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s3/I0 |
| 8.654 | 0.517 | tINS | FF | 5 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s3/F |
| 9.128 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s16/I1 |
| 9.683 | 0.555 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s16/F |
| 10.157 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s13/I1 |
| 10.712 | 0.555 | tINS | FF | 6 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s13/F |
| 11.186 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n888_s6/I1 |
| 11.741 | 0.555 | tINS | FF | 4 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n888_s6/F |
| 12.215 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n891_s3/I1 |
| 12.770 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n891_s3/F |
| 13.244 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n891_s2/I1 |
| 13.799 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n891_s2/F |
| 14.273 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_17_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 257 | clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_17_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_17_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 5.965, 42.873%; route: 5.688, 40.883%; tC2Q: 2.260, 16.244% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | -3.948 |
| Data Arrival Time | 14.273 |
| Data Required Time | 10.325 |
| From | mem_data_1_mem_data_1_0_0_s |
| To | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_18_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 257 | clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 32 | mem_data_1_mem_data_1_0_0_s/CLK |
| 2.620 | 2.260 | tC2Q | RF | 6 | mem_data_1_mem_data_1_0_0_s/DO[16] |
| 3.094 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n8_s2/I1 |
| 3.649 | 0.555 | tINS | FF | 6 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n8_s2/F |
| 4.123 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s5/I1 |
| 4.678 | 0.555 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s5/F |
| 5.152 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s3/I1 |
| 5.707 | 0.555 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s3/F |
| 6.181 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n885_s16/I2 |
| 6.634 | 0.453 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n885_s16/F |
| 7.108 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s5/I1 |
| 7.663 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s5/F |
| 8.137 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s3/I0 |
| 8.654 | 0.517 | tINS | FF | 5 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s3/F |
| 9.128 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s16/I1 |
| 9.683 | 0.555 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s16/F |
| 10.157 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s13/I1 |
| 10.712 | 0.555 | tINS | FF | 6 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s13/F |
| 11.186 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n888_s6/I1 |
| 11.741 | 0.555 | tINS | FF | 4 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n888_s6/F |
| 12.215 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n890_s13/I1 |
| 12.770 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n890_s13/F |
| 13.244 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n890_s2/I1 |
| 13.799 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n890_s2/F |
| 14.273 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_18_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 257 | clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_18_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_18_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 5.965, 42.873%; route: 5.688, 40.883%; tC2Q: 2.260, 16.244% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | -3.948 |
| Data Arrival Time | 14.273 |
| Data Required Time | 10.325 |
| From | mem_data_1_mem_data_1_0_0_s |
| To | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_20_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 257 | clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 32 | mem_data_1_mem_data_1_0_0_s/CLK |
| 2.620 | 2.260 | tC2Q | RF | 6 | mem_data_1_mem_data_1_0_0_s/DO[16] |
| 3.094 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n8_s2/I1 |
| 3.649 | 0.555 | tINS | FF | 6 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n8_s2/F |
| 4.123 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s5/I1 |
| 4.678 | 0.555 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s5/F |
| 5.152 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s3/I1 |
| 5.707 | 0.555 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s3/F |
| 6.181 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n885_s16/I2 |
| 6.634 | 0.453 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n885_s16/F |
| 7.108 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s5/I1 |
| 7.663 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s5/F |
| 8.137 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s3/I0 |
| 8.654 | 0.517 | tINS | FF | 5 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s3/F |
| 9.128 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s16/I1 |
| 9.683 | 0.555 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s16/F |
| 10.157 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s13/I1 |
| 10.712 | 0.555 | tINS | FF | 6 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s13/F |
| 11.186 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n888_s6/I1 |
| 11.741 | 0.555 | tINS | FF | 4 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n888_s6/F |
| 12.215 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n888_s3/I1 |
| 12.770 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n888_s3/F |
| 13.244 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n888_s2/I1 |
| 13.799 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n888_s2/F |
| 14.273 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_20_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 257 | clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_20_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_20_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 5.965, 42.873%; route: 5.688, 40.883%; tC2Q: 2.260, 16.244% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | -3.846 |
| Data Arrival Time | 14.171 |
| Data Required Time | 10.325 |
| From | mem_data_1_mem_data_1_0_0_s |
| To | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_27_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 257 | clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 32 | mem_data_1_mem_data_1_0_0_s/CLK |
| 2.620 | 2.260 | tC2Q | RF | 6 | mem_data_1_mem_data_1_0_0_s/DO[16] |
| 3.094 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n8_s2/I1 |
| 3.649 | 0.555 | tINS | FF | 6 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n8_s2/F |
| 4.123 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s5/I1 |
| 4.678 | 0.555 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s5/F |
| 5.152 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s3/I1 |
| 5.707 | 0.555 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n88_s3/F |
| 6.181 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n885_s16/I2 |
| 6.634 | 0.453 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n885_s16/F |
| 7.108 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s5/I1 |
| 7.663 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s5/F |
| 8.137 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s3/I0 |
| 8.654 | 0.517 | tINS | FF | 5 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n901_s3/F |
| 9.128 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s16/I1 |
| 9.683 | 0.555 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s16/F |
| 10.157 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s13/I1 |
| 10.712 | 0.555 | tINS | FF | 6 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n877_s13/F |
| 11.186 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n880_s8/I2 |
| 11.639 | 0.453 | tINS | FF | 7 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n880_s8/F |
| 12.113 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n881_s3/I1 |
| 12.668 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n881_s3/F |
| 13.142 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n881_s2/I1 |
| 13.697 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n881_s2/F |
| 14.171 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_27_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 257 | clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_27_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_27_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 5.863, 42.451%; route: 5.688, 41.185%; tC2Q: 2.260, 16.364% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | -3.828 |
| Data Arrival Time | 14.153 |
| Data Required Time | 10.325 |
| From | mem_data_1_mem_data_1_0_0_s |
| To | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_14_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 257 | clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 32 | mem_data_1_mem_data_1_0_0_s/CLK |
| 2.620 | 2.260 | tC2Q | RF | 6 | mem_data_1_mem_data_1_0_0_s/DO[16] |
| 3.094 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n8_s2/I1 |
| 3.649 | 0.555 | tINS | FF | 6 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n8_s2/F |
| 4.123 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n66_s4/I1 |
| 4.678 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n66_s4/F |
| 5.152 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n66_s3/I3 |
| 5.523 | 0.371 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n66_s3/F |
| 5.997 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n879_s29/I1 |
| 6.552 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n879_s29/F |
| 7.026 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n879_s22/I1 |
| 7.581 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n879_s22/F |
| 8.055 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n879_s11/I0 |
| 8.572 | 0.517 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n879_s11/F |
| 9.046 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n879_s7/I1 |
| 9.601 | 0.555 | tINS | FF | 3 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n879_s7/F |
| 10.075 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n879_s3/I1 |
| 10.630 | 0.555 | tINS | FF | 21 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n879_s3/F |
| 11.104 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n894_s13/I0 |
| 11.621 | 0.517 | tINS | FF | 2 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n894_s13/F |
| 12.095 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n894_s3/I1 |
| 12.650 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n894_s3/F |
| 13.124 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n894_s2/I1 |
| 13.679 | 0.555 | tINS | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/n894_s2/F |
| 14.153 | 0.474 | tNET | FF | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_14_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 257 | clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_14_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | Float_to_Fixed_Top_inst/Float_to_Fixed_inst/integer_reg_14_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 5.845, 42.377%; route: 5.688, 41.238%; tC2Q: 2.260, 16.385% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |