Hierarchy Module Resource

MODULE NAME REG NUMBER ALU NUMBER LUT NUMBER DSP NUMBER BSRAM NUMBER SSRAM NUMBER ROM16 NUMBER
top (E:/IP_Release/2.5G_Serial_Ethernet_Over_Serdes/1.5/Gowin_2.5G_Serial_Ethernet_RefDesign/project/src/top.v) 50 - 63 - - - -
    |--sw1 (E:/IP_Release/2.5G_Serial_Ethernet_Over_Serdes/1.5/Gowin_2.5G_Serial_Ethernet_RefDesign/project/src/top.v) 11 - 3 - - - -
    |--uart1 (E:/IP_Release/2.5G_Serial_Ethernet_Over_Serdes/1.5/Gowin_2.5G_Serial_Ethernet_RefDesign/project/src/top.v) 11 - 3 - - - -
    |--u_pll_uart (E:/IP_Release/2.5G_Serial_Ethernet_Over_Serdes/1.5/Gowin_2.5G_Serial_Ethernet_RefDesign/project/src/top.v) - - - - - - -
        |--u_pll (E:/IP_Release/2.5G_Serial_Ethernet_Over_Serdes/1.5/Gowin_2.5G_Serial_Ethernet_RefDesign/project/src/pll_uart/pll_uart.v) - - - - - - -
        |--u_pll_init (E:/IP_Release/2.5G_Serial_Ethernet_Over_Serdes/1.5/Gowin_2.5G_Serial_Ethernet_RefDesign/project/src/pll_uart/pll_uart.v) 39 16 51 - - - -
    |--u_SerDes_Top (E:/IP_Release/2.5G_Serial_Ethernet_Over_Serdes/1.5/Gowin_2.5G_Serial_Ethernet_RefDesign/project/src/top.v) - - - - - - -
        |--Two_Giga_Serial_Ethernet_Top_inst (E:/IP_Release/2.5G_Serial_Ethernet_Over_Serdes/1.5/Gowin_2.5G_Serial_Ethernet_RefDesign/project/src/serdes/serdes.v) 2120 86 2420 - - - -
    |--u_Uart_to_Bus_Top (E:/IP_Release/2.5G_Serial_Ethernet_Over_Serdes/1.5/Gowin_2.5G_Serial_Ethernet_RefDesign/project/src/top.v) 1438 40 948 - - - -
    |--u_sysreg (E:/IP_Release/2.5G_Serial_Ethernet_Over_Serdes/1.5/Gowin_2.5G_Serial_Ethernet_RefDesign/project/src/top.v) 548 - 645 - - - -
    |--u_mac_tx_model_word (E:/IP_Release/2.5G_Serial_Ethernet_Over_Serdes/1.5/Gowin_2.5G_Serial_Ethernet_RefDesign/project/src/top.v) 352 112 290 - - - -
    |--u_mac_rx_model_word (E:/IP_Release/2.5G_Serial_Ethernet_Over_Serdes/1.5/Gowin_2.5G_Serial_Ethernet_RefDesign/project/src/top.v) 822 154 830 - - - -