Timing Messages

Report Title	Timing Analysis Report
Design File	E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\fpga_project.cst
Timing Constraint File	E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\fpga_project.sdc
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW5AST-LV138FPG676AES
Device	GW5AST-138
Device Version	B
Created Time	Tue Dec 30 15:11:06 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C ES
Hold Delay Model	Fast 0.945V 85C ES
Numbers of Paths Analyzed	16978
Numbers of Endpoints Analyzed	16917
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	rx_mac_clk	Base	6.400	156.250	0.000	3.200			u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
2	tx_mac_clk	Base	6.400	156.250	0.000	3.200			u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3	clk_in	Base	19.048	52.499	0.000	10.000			u_osc/OSCOUT
4	board_clk	Base	20.000	50.000	0.000	10.000			board_clk_ibuf/I
5	clk_uart	Generated	100.000	10.000	0.000	50.000	board_clk_ibuf/I	board_clk	u_pll_uart/u_pll/PLL_inst/CLKOUT0

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	rx_mac_clk	156.250(MHz)	156.601(MHz)	5	TOP
2	tx_mac_clk	156.250(MHz)	165.383(MHz)	5	TOP
3	clk_in	52.499(MHz)	180.974(MHz)	2	TOP
4	board_clk	50.000(MHz)	309.298(MHz)	5	TOP
5	clk_uart	10.000(MHz)	67.793(MHz)	8	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
rx_mac_clk	Setup	0.000	0
rx_mac_clk	Hold	0.000	0
tx_mac_clk	Setup	0.000	0
tx_mac_clk	Hold	0.000	0
clk_in	Setup	0.000	0
clk_in	Hold	0.000	0
board_clk	Setup	0.000	0
board_clk	Hold	0.000	0
clk_uart	Setup	0.000	0
clk_uart	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.014	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_3_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1/CE	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.046	6.120
2	0.073	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_2_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	0.009	6.254
3	0.083	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/D21_5_match_d4_0_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_1_s1/CE	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.028	6.034
4	0.083	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/D21_5_match_d4_0_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s1/CE	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.028	6.034
5	0.123	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_15_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.007	6.220
6	0.124	u_mac_rx_model_word/pause_address_17_s1/Q	u_mac_rx_model_word/pause_address_22_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.017	6.230
7	0.184	u_mac_rx_model_word/pause_address_17_s1/Q	u_mac_rx_model_word/pause_address_29_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.017	6.170
8	0.185	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_d1_4_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_dv_m_clr_h_s0/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	0.006	6.145
9	0.207	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_5_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	0.002	6.128
10	0.266	u_mac_rx_model_word/pause_address_17_s1/Q	u_mac_rx_model_word/pause_address_25_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.017	6.088
11	0.275	u_mac_rx_model_word/pause_address_17_s1/Q	u_mac_rx_model_word/pause_address_44_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.015	6.076
12	0.322	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/c_state_0_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1/CE	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	0.009	5.758
13	0.331	u_mac_rx_model_word/rx_pause_state_s5/Q	u_mac_rx_model_word/shift_reg_pause_12_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	0.017	5.988
14	0.353	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_12_s1/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_less_58_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	6.400	0.017	5.719
15	0.360	u_mac_rx_model_word/pause_address_22_s1/Q	u_mac_rx_model_word/pause_address_32_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	0.047	5.929
16	0.360	u_mac_rx_model_word/pause_address_22_s1/Q	u_mac_rx_model_word/pause_address_34_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	0.047	5.929
17	0.411	u_mac_rx_model_word/pause_address_17_s1/Q	u_mac_rx_model_word/pause_address_43_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.006	5.931
18	0.414	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_1_s1/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_1_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	0.009	5.912
19	0.455	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_3_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.005	5.886
20	0.469	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/K28_5_match_d5_0_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rudi_INVALID_m_set_s0/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.056	5.924
21	0.475	u_mac_rx_model_word/pause_address_17_s1/Q	u_mac_rx_model_word/pause_address_26_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.017	5.879
22	0.477	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/D21_5_match_d4_0_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_0_s3/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.028	5.888
23	0.484	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_d1_4_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_er_m_set_l_s0/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.009	5.861
24	0.486	u_mac_rx_model_word/pause_address_22_s1/Q	u_mac_rx_model_word/pause_address_33_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	0.047	5.803
25	0.491	u_mac_rx_model_word/pause_address_17_s1/Q	u_mac_rx_model_word/pause_address_28_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.006	5.851

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.275	u_mac_rx_model_word/rx_cnt_16_s3/Q	u_mac_rx_model_word/rx_cnt_16_s3/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
2	0.275	u_mac_rx_model_word/rx_error_all_check_s4/Q	u_mac_rx_model_word/rx_error_all_check_s4/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
3	0.275	u_mac_rx_model_word/rx_cnt_20_s1/Q	u_mac_rx_model_word/rx_cnt_20_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
4	0.275	u_mac_rx_model_word/rx_data_cnt_pause_3_s1/Q	u_mac_rx_model_word/rx_data_cnt_pause_3_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
5	0.275	u_mac_rx_model_word/rx_data_cnt_pause_5_s1/Q	u_mac_rx_model_word/rx_data_cnt_pause_5_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
6	0.275	u_mac_rx_model_word/shift_reg_pause_10_s1/Q	u_mac_rx_model_word/shift_reg_pause_10_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
7	0.275	u_mac_rx_model_word/pause_address_21_s1/Q	u_mac_rx_model_word/pause_address_21_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
8	0.275	u_mac_rx_model_word/pause_address_28_s1/Q	u_mac_rx_model_word/pause_address_28_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
9	0.275	u_mac_rx_model_word/pause_address_35_s1/Q	u_mac_rx_model_word/pause_address_35_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
10	0.275	u_mac_rx_model_word/pause_address_47_s1/Q	u_mac_rx_model_word/pause_address_47_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
11	0.275	u_mac_rx_model_word/pause_value_0_s1/Q	u_mac_rx_model_word/pause_value_0_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
12	0.275	u_mac_rx_model_word/pause_value_1_s1/Q	u_mac_rx_model_word/pause_value_1_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
13	0.275	u_mac_rx_model_word/pause_value_5_s1/Q	u_mac_rx_model_word/pause_value_5_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
14	0.275	u_mac_rx_model_word/rx_data_cnt_1_s1/Q	u_mac_rx_model_word/rx_data_cnt_1_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
15	0.275	u_mac_rx_model_word/data_increase_add_1_0_s1/Q	u_mac_rx_model_word/data_increase_add_1_0_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
16	0.275	u_mac_rx_model_word/data_increase_add_1_7_s1/Q	u_mac_rx_model_word/data_increase_add_1_7_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
17	0.275	u_mac_rx_model_word/data_increase_0_s1/Q	u_mac_rx_model_word/data_increase_0_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
18	0.275	u_mac_rx_model_word/shift_reg_0_s1/Q	u_mac_rx_model_word/shift_reg_0_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
19	0.275	u_mac_rx_model_word/shift_reg_2_s1/Q	u_mac_rx_model_word/shift_reg_2_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
20	0.275	u_mac_rx_model_word/shift_reg_4_s1/Q	u_mac_rx_model_word/shift_reg_4_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
21	0.275	u_mac_rx_model_word/shift_reg_9_s1/Q	u_mac_rx_model_word/shift_reg_9_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
22	0.275	u_mac_rx_model_word/shift_reg_11_s1/Q	u_mac_rx_model_word/shift_reg_11_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
23	0.275	u_mac_rx_model_word/shift_reg_15_s1/Q	u_mac_rx_model_word/shift_reg_15_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
24	0.275	u_mac_rx_model_word/shift_reg_19_s1/Q	u_mac_rx_model_word/shift_reg_19_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
25	0.275	u_mac_rx_model_word/shift_reg_25_s1/Q	u_mac_rx_model_word/shift_reg_25_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.005	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_5_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.008	6.055
2	0.005	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_11_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.008	6.055
3	0.005	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_12_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.008	6.055
4	0.005	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_13_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.008	6.055
5	0.005	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_15_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.008	6.055
6	0.177	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_2_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.007	5.883
7	0.177	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_6_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.007	5.883
8	0.177	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_14_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.007	5.883
9	0.218	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_13_s3/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.022	5.856
10	0.218	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_14_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.022	5.856
11	0.218	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_15_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.022	5.856
12	0.218	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_16_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.022	5.856
13	0.218	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_17_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.022	5.856
14	0.221	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_2_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.005	5.836
15	0.221	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_6_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.005	5.836
16	0.221	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_7_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.005	5.836
17	0.231	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_5_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.014	5.836
18	0.231	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_10_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.014	5.836
19	0.231	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_11_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.014	5.836
20	0.231	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_12_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.014	5.836
21	0.231	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_13_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.014	5.836
22	0.231	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_15_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.014	5.836
23	0.387	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_4_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.007	5.673
24	0.387	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_20_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.007	5.673
25	0.387	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_36_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	6.400	-0.007	5.673

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.284	u_pll_uart/u_pll_init/enable_r_1_s0/Q	u_pll_uart/u_pll_init/RomAddr_3_s1/CLEAR	board_clk:[R]	board_clk:[R]	0.000	0.000	0.231
2	0.304	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/data_length_next_7_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.008	0.259
3	0.304	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/data_length_next_8_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.008	0.259
4	0.304	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/data_length_next_9_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.008	0.259
5	0.304	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/data_length_next_10_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.008	0.259
6	0.304	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/data_length_next_11_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.008	0.259
7	0.304	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/data_length_next_12_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.008	0.259
8	0.306	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/rx_cnt_13_s3/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.008	0.261
9	0.306	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/rx_cnt_5_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.008	0.261
10	0.306	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/rx_cnt_14_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.008	0.261
11	0.310	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/data_length_13_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.004	0.261
12	0.380	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/shift_reg_pause_63_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.011	0.316
13	0.380	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/shift_reg_pause_77_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.011	0.316
14	0.380	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/shift_reg_pause_79_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.011	0.316
15	0.380	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/shift_reg_pause_80_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.011	0.316
16	0.382	u_pll_uart/u_pll_init/enable_r_1_s0/Q	u_pll_uart/u_pll_init/RomAddr_1_s1/CLEAR	board_clk:[R]	board_clk:[R]	0.000	-0.004	0.333
17	0.382	u_pll_uart/u_pll_init/enable_r_1_s0/Q	u_pll_uart/u_pll_init/RomAddr_2_s1/CLEAR	board_clk:[R]	board_clk:[R]	0.000	-0.004	0.333
18	0.383	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/shift_reg_pause_15_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.015	0.316
19	0.383	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/pause_data_3_15_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.015	0.316
20	0.383	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/pause_data_2_15_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.015	0.316
21	0.383	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/pause_data_2_29_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.015	0.316
22	0.383	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/pause_data_2_31_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.015	0.316
23	0.383	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/pause_data_2_32_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.015	0.316
24	0.385	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/shift_reg_pause_143_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.018	0.314
25	0.385	rx_mac_rst_n_s0/Q	u_mac_rx_model_word/rx_frm_cnt_0_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.018	0.314

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	0.791	1.041	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/gmii_rxd_int_12_s0
2	0.791	1.041	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/flow_ctrl_dest_addr_reg_s0
3	0.791	1.041	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/flow_ctrl_op_reg_s0
4	0.791	1.041	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/gmii_rxd_int_9_s0
5	0.791	1.041	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rxd_preamble_m_set_h_s0
6	0.791	1.041	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_46_s1
7	0.791	1.041	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_45_s1
8	0.791	1.041	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_44_s1
9	0.791	1.041	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_43_s1
10	0.791	1.041	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_23_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.014
Data Arrival Time	10.011
Data Required Time	10.025
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_3_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.891	3.891	tNET	RR	1	R17C121[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_3_s0/CLK
4.273	0.382	tC2Q	RR	17	R17C121[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_3_s0/Q
4.883	0.610	tNET	RR	1	R15C124[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1843_s9/I1
5.451	0.567	tINS	RR	10	R15C124[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1843_s9/F
6.264	0.814	tNET	RR	1	R15C121[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s7/I3
6.832	0.567	tINS	RR	5	R15C121[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s7/F
8.186	1.354	tNET	RR	1	R20C126[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s4/I1
8.753	0.567	tINS	RR	1	R20C126[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s4/F
8.756	0.003	tNET	RR	1	R20C126[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s3/I0
9.212	0.456	tINS	RR	1	R20C126[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s3/F
10.011	0.799	tNET	RR	1	R20C126[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.336	3.936	tNET	RR	1	R20C126[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1/CLK
10.025	-0.311	tSu		1	R20C126[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1

Path Statistics:

Clock Skew	0.046
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.891, 100.000%
Arrival Data Path Delay	cell: 2.159, 35.274%; route: 3.579, 58.476%; tC2Q: 0.382, 6.250%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.936, 100.000%

Path2

Path Summary:

Slack	0.073
Data Arrival Time	10.170
Data Required Time	10.244
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_2_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.917	3.917	tNET	RR	1	R26C138[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1/CLK
4.299	0.382	tC2Q	RR	25	R26C138[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1/Q
7.128	2.829	tNET	RR	1	R23C133[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n702_s11/I1
7.695	0.567	tINS	RR	4	R23C133[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n702_s11/F
8.082	0.386	tNET	RR	1	R24C134[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n702_s14/I0
8.660	0.579	tINS	RR	1	R24C134[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n702_s14/F
8.833	0.172	tNET	RR	1	R24C133[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n702_s4/I3
9.380	0.548	tINS	RR	1	R24C133[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n702_s4/F
9.592	0.211	tNET	RR	1	R24C132[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n702_s2/I1
10.170	0.579	tINS	RR	1	R24C132[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n702_s2/F
10.170	0.000	tNET	RR	1	R24C132[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.308	3.908	tNET	RR	1	R24C132[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_2_s1/CLK
10.244	-0.064	tSu		1	R24C132[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_2_s1

Path Statistics:

Clock Skew	-0.009
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.917, 100.000%
Arrival Data Path Delay	cell: 2.273, 36.338%; route: 3.599, 57.545%; tC2Q: 0.382, 6.116%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%

Path3

Path Summary:

Slack	0.083
Data Arrival Time	9.923
Data Required Time	10.006
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/D21_5_match_d4_0_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_1_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.889	3.889	tNET	RR	1	R16C125[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/D21_5_match_d4_0_s0/CLK
4.271	0.382	tC2Q	RR	3	R16C125[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/D21_5_match_d4_0_s0/Q
5.015	0.744	tNET	RR	1	R16C121[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s8/I0
5.583	0.567	tINS	RR	4	R16C121[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s8/F
6.329	0.746	tNET	RR	1	R18C124[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/idle_cnt_1_s6/I3
6.896	0.567	tINS	RR	1	R18C124[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/idle_cnt_1_s6/F
6.899	0.003	tNET	RR	1	R18C124[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/idle_cnt_1_s4/I0
7.466	0.567	tINS	RR	2	R18C124[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/idle_cnt_1_s4/F
8.358	0.891	tNET	RR	1	R21C121[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s4/I2
8.814	0.456	tINS	RR	2	R21C121[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s4/F
9.198	0.384	tNET	RR	1	R24C121[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s15/I1
9.771	0.574	tINS	RR	2	R24C121[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s15/F
9.923	0.151	tNET	RR	1	R24C121[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.317	3.917	tNET	RR	1	R24C121[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_1_s1/CLK
10.006	-0.311	tSu		1	R24C121[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_1_s1

Path Statistics:

Clock Skew	0.028
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.889, 100.000%
Arrival Data Path Delay	cell: 2.733, 45.287%; route: 2.919, 48.374%; tC2Q: 0.382, 6.339%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.917, 100.000%

Path4

Path Summary:

Slack	0.083
Data Arrival Time	9.923
Data Required Time	10.006
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/D21_5_match_d4_0_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.889	3.889	tNET	RR	1	R16C125[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/D21_5_match_d4_0_s0/CLK
4.271	0.382	tC2Q	RR	3	R16C125[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/D21_5_match_d4_0_s0/Q
5.015	0.744	tNET	RR	1	R16C121[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s8/I0
5.583	0.567	tINS	RR	4	R16C121[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s8/F
6.329	0.746	tNET	RR	1	R18C124[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/idle_cnt_1_s6/I3
6.896	0.567	tINS	RR	1	R18C124[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/idle_cnt_1_s6/F
6.899	0.003	tNET	RR	1	R18C124[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/idle_cnt_1_s4/I0
7.466	0.567	tINS	RR	2	R18C124[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/idle_cnt_1_s4/F
8.358	0.891	tNET	RR	1	R21C121[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s4/I2
8.814	0.456	tINS	RR	2	R21C121[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s4/F
9.198	0.384	tNET	RR	1	R24C121[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s15/I1
9.771	0.574	tINS	RR	2	R24C121[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s15/F
9.923	0.151	tNET	RR	1	R24C121[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.317	3.917	tNET	RR	1	R24C121[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s1/CLK
10.006	-0.311	tSu		1	R24C121[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s1

Path Statistics:

Clock Skew	0.028
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.889, 100.000%
Arrival Data Path Delay	cell: 2.733, 45.287%; route: 2.919, 48.374%; tC2Q: 0.382, 6.339%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.917, 100.000%

Path5

Path Summary:

Slack	0.123
Data Arrival Time	10.137
Data Required Time	10.260
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_15_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.917	3.917	tNET	RR	1	R26C138[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1/CLK
4.299	0.382	tC2Q	RR	25	R26C138[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1/Q
7.128	2.829	tNET	RR	1	R23C133[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n702_s11/I1
7.695	0.567	tINS	RR	4	R23C133[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n702_s11/F
8.082	0.386	tNET	RR	1	R24C134[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n689_s8/I2
8.660	0.579	tINS	RR	1	R24C134[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n689_s8/F
8.812	0.151	tNET	RR	1	R24C134[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n689_s4/I2
9.385	0.574	tINS	RR	1	R24C134[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n689_s4/F
9.558	0.172	tNET	RR	1	R25C134[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n689_s2/I1
10.137	0.579	tINS	RR	1	R25C134[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n689_s2/F
10.137	0.000	tNET	RR	1	R25C134[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.324	3.924	tNET	RR	1	R25C134[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_15_s1/CLK
10.260	-0.064	tSu		1	R25C134[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_15_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.917, 100.000%
Arrival Data Path Delay	cell: 2.299, 36.957%; route: 3.539, 56.893%; tC2Q: 0.382, 6.150%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.924, 100.000%

Path6

Path Summary:

Slack	0.124
Data Arrival Time	10.072
Data Required Time	10.196
From	u_mac_rx_model_word/pause_address_17_s1
To	u_mac_rx_model_word/pause_address_22_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.842	3.842	tNET	RR	1	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/CLK
4.224	0.382	tC2Q	RR	5	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/Q
4.744	0.520	tNET	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/I2
5.252	0.507	tINS	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/F
5.821	0.569	tNET	RR	1	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/I3
6.112	0.291	tINS	RR	2	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/F
6.853	0.741	tNET	RR	1	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/I2
7.309	0.456	tINS	RR	27	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/F
9.504	2.195	tNET	RR	1	R20C153[1][A]	u_mac_rx_model_word/n1615_s0/I0
10.072	0.567	tINS	RR	1	R20C153[1][A]	u_mac_rx_model_word/n1615_s0/F
10.072	0.000	tNET	RR	1	R20C153[1][A]	u_mac_rx_model_word/pause_address_22_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.259	3.859	tNET	RR	1	R20C153[1][A]	u_mac_rx_model_word/pause_address_22_s1/CLK
10.196	-0.064	tSu		1	R20C153[1][A]	u_mac_rx_model_word/pause_address_22_s1

Path Statistics:

Clock Skew	0.017
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.842, 100.000%
Arrival Data Path Delay	cell: 1.822, 29.254%; route: 4.025, 64.607%; tC2Q: 0.382, 6.140%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.859, 100.000%

Path7

Path Summary:

Slack	0.184
Data Arrival Time	10.012
Data Required Time	10.196
From	u_mac_rx_model_word/pause_address_17_s1
To	u_mac_rx_model_word/pause_address_29_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.842	3.842	tNET	RR	1	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/CLK
4.224	0.382	tC2Q	RR	5	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/Q
4.744	0.520	tNET	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/I2
5.252	0.507	tINS	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/F
5.821	0.569	tNET	RR	1	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/I3
6.112	0.291	tINS	RR	2	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/F
6.853	0.741	tNET	RR	1	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/I2
7.309	0.456	tINS	RR	27	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/F
9.504	2.195	tNET	RR	1	R20C153[0][B]	u_mac_rx_model_word/n1608_s0/I0
10.012	0.507	tINS	RR	1	R20C153[0][B]	u_mac_rx_model_word/n1608_s0/F
10.012	0.000	tNET	RR	1	R20C153[0][B]	u_mac_rx_model_word/pause_address_29_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.259	3.859	tNET	RR	1	R20C153[0][B]	u_mac_rx_model_word/pause_address_29_s1/CLK
10.196	-0.064	tSu		1	R20C153[0][B]	u_mac_rx_model_word/pause_address_29_s1

Path Statistics:

Clock Skew	0.017
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.842, 100.000%
Arrival Data Path Delay	cell: 1.763, 28.566%; route: 4.025, 65.235%; tC2Q: 0.382, 6.199%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.859, 100.000%

Path8

Path Summary:

Slack	0.185
Data Arrival Time	10.032
Data Required Time	10.217
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_d1_4_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_dv_m_clr_h_s0
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.887	3.887	tNET	RR	1	R15C125[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_d1_4_s0/CLK
4.269	0.382	tC2Q	RR	14	R15C125[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_d1_4_s0/Q
5.542	1.273	tNET	RR	1	R20C122[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s7/I1
6.109	0.567	tINS	RR	5	R20C122[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s7/F
6.117	0.008	tNET	RR	1	R20C122[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2191_s5/I3
6.624	0.507	tINS	RR	9	R20C122[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2191_s5/F
8.296	1.671	tNET	RR	1	R14C127[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2146_s22/I2
8.874	0.579	tINS	RR	1	R14C127[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2146_s22/F
8.877	0.003	tNET	RR	1	R14C127[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2146_s13/I2
9.451	0.574	tINS	RR	1	R14C127[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2146_s13/F
9.453	0.003	tNET	RR	1	R14C127[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2146_s10/I2
10.032	0.579	tINS	RR	1	R14C127[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2146_s10/F
10.032	0.000	tNET	RR	1	R14C127[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_dv_m_clr_h_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.281	3.881	tNET	RR	1	R14C127[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_dv_m_clr_h_s0/CLK
10.217	-0.064	tSu		1	R14C127[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_dv_m_clr_h_s0

Path Statistics:

Clock Skew	-0.006
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.887, 100.000%
Arrival Data Path Delay	cell: 2.806, 45.667%; route: 2.956, 48.108%; tC2Q: 0.382, 6.225%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.881, 100.000%

Path9

Path Summary:

Slack	0.207
Data Arrival Time	10.044
Data Required Time	10.251
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_5_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.917	3.917	tNET	RR	1	R26C138[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1/CLK
4.299	0.382	tC2Q	RR	25	R26C138[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1/Q
7.327	3.028	tNET	RR	1	R24C135[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n694_s6/I0
7.894	0.567	tINS	RR	2	R24C135[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n694_s6/F
8.445	0.551	tNET	RR	1	R25C131[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n699_s6/I3
8.953	0.507	tINS	RR	1	R25C131[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n699_s6/F
8.955	0.003	tNET	RR	1	R25C131[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n699_s3/I2
9.534	0.579	tINS	RR	1	R25C131[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n699_s3/F
9.537	0.003	tNET	RR	1	R25C131[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n699_s2/I0
10.044	0.507	tINS	RR	1	R25C131[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n699_s2/F
10.044	0.000	tNET	RR	1	R25C131[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.314	3.914	tNET	RR	1	R25C131[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_5_s1/CLK
10.251	-0.064	tSu		1	R25C131[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_5_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.917, 100.000%
Arrival Data Path Delay	cell: 2.161, 35.271%; route: 3.584, 58.486%; tC2Q: 0.382, 6.242%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.914, 100.000%

Path10

Path Summary:

Slack	0.266
Data Arrival Time	9.929
Data Required Time	10.196
From	u_mac_rx_model_word/pause_address_17_s1
To	u_mac_rx_model_word/pause_address_25_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.842	3.842	tNET	RR	1	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/CLK
4.224	0.382	tC2Q	RR	5	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/Q
4.744	0.520	tNET	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/I2
5.252	0.507	tINS	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/F
5.821	0.569	tNET	RR	1	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/I3
6.112	0.291	tINS	RR	2	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/F
6.853	0.741	tNET	RR	1	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/I2
7.309	0.456	tINS	RR	27	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/F
9.351	2.041	tNET	RR	1	R20C153[0][A]	u_mac_rx_model_word/n1612_s0/I0
9.929	0.579	tINS	RR	1	R20C153[0][A]	u_mac_rx_model_word/n1612_s0/F
9.929	0.000	tNET	RR	1	R20C153[0][A]	u_mac_rx_model_word/pause_address_25_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.259	3.859	tNET	RR	1	R20C153[0][A]	u_mac_rx_model_word/pause_address_25_s1/CLK
10.196	-0.064	tSu		1	R20C153[0][A]	u_mac_rx_model_word/pause_address_25_s1

Path Statistics:

Clock Skew	0.017
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.842, 100.000%
Arrival Data Path Delay	cell: 1.834, 30.123%; route: 3.871, 63.593%; tC2Q: 0.382, 6.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.859, 100.000%

Path11

Path Summary:

Slack	0.275
Data Arrival Time	9.918
Data Required Time	10.193
From	u_mac_rx_model_word/pause_address_17_s1
To	u_mac_rx_model_word/pause_address_44_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.842	3.842	tNET	RR	1	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/CLK
4.224	0.382	tC2Q	RR	5	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/Q
4.744	0.520	tNET	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/I2
5.252	0.507	tINS	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/F
5.821	0.569	tNET	RR	1	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/I3
6.112	0.291	tINS	RR	2	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/F
6.853	0.741	tNET	RR	1	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/I2
7.309	0.456	tINS	RR	27	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/F
9.351	2.041	tNET	RR	1	R21C155[2][A]	u_mac_rx_model_word/n1593_s0/I0
9.918	0.567	tINS	RR	1	R21C155[2][A]	u_mac_rx_model_word/n1593_s0/F
9.918	0.000	tNET	RR	1	R21C155[2][A]	u_mac_rx_model_word/pause_address_44_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.257	3.857	tNET	RR	1	R21C155[2][A]	u_mac_rx_model_word/pause_address_44_s1/CLK
10.193	-0.064	tSu		1	R21C155[2][A]	u_mac_rx_model_word/pause_address_44_s1

Path Statistics:

Clock Skew	0.015
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.842, 100.000%
Arrival Data Path Delay	cell: 1.822, 29.994%; route: 3.871, 63.711%; tC2Q: 0.382, 6.295%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.857, 100.000%

Path12

Path Summary:

Slack	0.322
Data Arrival Time	9.659
Data Required Time	9.981
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/c_state_0_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.902	3.902	tNET	RR	1	R18C146[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/c_state_0_s0/CLK
4.284	0.382	tC2Q	RR	18	R18C146[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/c_state_0_s0/Q
5.026	0.741	tNET	RR	1	R21C145[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n419_s5/I0
5.599	0.574	tINS	RR	2	R21C145[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n419_s5/F
6.319	0.720	tNET	RR	1	R18C146[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n419_s3/I3
6.608	0.289	tINS	RR	3	R18C146[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n419_s3/F
6.973	0.365	tNET	RR	1	R18C148[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n419_s2/I0
7.552	0.579	tINS	RR	21	R18C148[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n419_s2/F
8.079	0.528	tNET	RR	1	R20C147[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
8.536	0.456	tINS	RR	21	R20C147[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
9.659	1.124	tNET	RR	1	R18C145[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.293	3.893	tNET	RR	1	R18C145[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1/CLK
9.981	-0.311	tSu		1	R18C145[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1

Path Statistics:

Clock Skew	-0.009
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.902, 100.000%
Arrival Data Path Delay	cell: 1.898, 32.957%; route: 3.478, 60.399%; tC2Q: 0.382, 6.644%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.893, 100.000%

Path13

Path Summary:

Slack	0.331
Data Arrival Time	9.845
Data Required Time	10.176
From	u_mac_rx_model_word/rx_pause_state_s5
To	u_mac_rx_model_word/shift_reg_pause_12_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.857	3.857	tNET	RR	1	R21C159[0][B]	u_mac_rx_model_word/rx_pause_state_s5/CLK
4.239	0.382	tC2Q	RR	162	R21C159[0][B]	u_mac_rx_model_word/rx_pause_state_s5/Q
9.338	5.098	tNET	RR	1	R8C155[2][A]	u_mac_rx_model_word/n2117_s0/I3
9.845	0.507	tINS	RR	1	R8C155[2][A]	u_mac_rx_model_word/n2117_s0/F
9.845	0.000	tNET	RR	1	R8C155[2][A]	u_mac_rx_model_word/shift_reg_pause_12_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.240	3.840	tNET	RR	1	R8C155[2][A]	u_mac_rx_model_word/shift_reg_pause_12_s1/CLK
10.176	-0.064	tSu		1	R8C155[2][A]	u_mac_rx_model_word/shift_reg_pause_12_s1

Path Statistics:

Clock Skew	-0.017
Setup Relationship	6.400
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.857, 100.000%
Arrival Data Path Delay	cell: 0.507, 8.475%; route: 5.098, 85.137%; tC2Q: 0.382, 6.388%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%

Path14

Path Summary:

Slack	0.353
Data Arrival Time	9.370
Data Required Time	9.723
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_12_s1
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_less_58_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	1310	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.651	3.651	tNET	RR	1	R11C131[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_12_s1/CLK
4.034	0.382	tC2Q	RR	5	R11C131[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_12_s1/Q
4.548	0.514	tNET	RR	1	R9C131[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_equa_16_s6/I0
5.004	0.456	tINS	RR	1	R9C131[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_equa_16_s6/F
5.684	0.680	tNET	RR	1	R11C129[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_equa_16_s4/I2
5.973	0.289	tINS	RR	3	R11C129[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_equa_16_s4/F
6.508	0.535	tNET	RR	1	R12C130[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_less_58_s4/I2
7.075	0.567	tINS	RR	2	R12C130[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_less_58_s4/F
7.993	0.918	tNET	RR	1	R12C143[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_less_58_s3/I1
8.571	0.579	tINS	RR	1	R12C143[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_less_58_s3/F
9.370	0.799	tNET	RR	1	R12C143[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_less_58_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					tx_mac_clk
6.400	0.000	tCL	RR	1310	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
10.035	3.635	tNET	RR	1	R12C143[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_less_58_s1/CLK
9.723	-0.311	tSu		1	R12C143[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/frm_byte_cnt_less_58_s1

Path Statistics:

Clock Skew	-0.017
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.651, 100.000%
Arrival Data Path Delay	cell: 1.891, 33.071%; route: 3.445, 60.240%; tC2Q: 0.382, 6.689%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.635, 100.000%

Path15

Path Summary:

Slack	0.360
Data Arrival Time	9.788
Data Required Time	10.148
From	u_mac_rx_model_word/pause_address_22_s1
To	u_mac_rx_model_word/pause_address_32_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.859	3.859	tNET	RR	1	R20C153[1][A]	u_mac_rx_model_word/pause_address_22_s1/CLK
4.242	0.382	tC2Q	RR	5	R20C153[1][A]	u_mac_rx_model_word/pause_address_22_s1/Q
4.699	0.457	tNET	RR	1	R18C153[1][B]	u_mac_rx_model_word/n1612_s1/I2
5.207	0.507	tINS	RR	3	R18C153[1][B]	u_mac_rx_model_word/n1612_s1/F
5.951	0.744	tNET	RR	1	R20C155[1][A]	u_mac_rx_model_word/n1599_s2/I3
6.518	0.567	tINS	RR	7	R20C155[1][A]	u_mac_rx_model_word/n1599_s2/F
7.882	1.364	tNET	RR	1	R9C161[3][B]	u_mac_rx_model_word/n1600_s3/I2
8.338	0.456	tINS	RR	6	R9C161[3][B]	u_mac_rx_model_word/n1600_s3/F
9.281	0.942	tNET	RR	1	R16C156[1][A]	u_mac_rx_model_word/n1605_s0/I1
9.788	0.507	tINS	RR	1	R16C156[1][A]	u_mac_rx_model_word/n1605_s0/F
9.788	0.000	tNET	RR	1	R16C156[1][A]	u_mac_rx_model_word/pause_address_32_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.212	3.812	tNET	RR	1	R16C156[1][A]	u_mac_rx_model_word/pause_address_32_s1/CLK
10.148	-0.064	tSu		1	R16C156[1][A]	u_mac_rx_model_word/pause_address_32_s1

Path Statistics:

Clock Skew	-0.047
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.859, 100.000%
Arrival Data Path Delay	cell: 2.039, 34.388%; route: 3.508, 59.161%; tC2Q: 0.382, 6.452%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.812, 100.000%

Path16

Path Summary:

Slack	0.360
Data Arrival Time	9.788
Data Required Time	10.148
From	u_mac_rx_model_word/pause_address_22_s1
To	u_mac_rx_model_word/pause_address_34_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.859	3.859	tNET	RR	1	R20C153[1][A]	u_mac_rx_model_word/pause_address_22_s1/CLK
4.242	0.382	tC2Q	RR	5	R20C153[1][A]	u_mac_rx_model_word/pause_address_22_s1/Q
4.699	0.457	tNET	RR	1	R18C153[1][B]	u_mac_rx_model_word/n1612_s1/I2
5.207	0.507	tINS	RR	3	R18C153[1][B]	u_mac_rx_model_word/n1612_s1/F
5.951	0.744	tNET	RR	1	R20C155[1][A]	u_mac_rx_model_word/n1599_s2/I3
6.518	0.567	tINS	RR	7	R20C155[1][A]	u_mac_rx_model_word/n1599_s2/F
7.882	1.364	tNET	RR	1	R9C161[3][B]	u_mac_rx_model_word/n1600_s3/I2
8.338	0.456	tINS	RR	6	R9C161[3][B]	u_mac_rx_model_word/n1600_s3/F
9.281	0.942	tNET	RR	1	R16C156[1][B]	u_mac_rx_model_word/n1603_s0/I2
9.788	0.507	tINS	RR	1	R16C156[1][B]	u_mac_rx_model_word/n1603_s0/F
9.788	0.000	tNET	RR	1	R16C156[1][B]	u_mac_rx_model_word/pause_address_34_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.212	3.812	tNET	RR	1	R16C156[1][B]	u_mac_rx_model_word/pause_address_34_s1/CLK
10.148	-0.064	tSu		1	R16C156[1][B]	u_mac_rx_model_word/pause_address_34_s1

Path Statistics:

Clock Skew	-0.047
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.859, 100.000%
Arrival Data Path Delay	cell: 2.039, 34.388%; route: 3.508, 59.161%; tC2Q: 0.382, 6.452%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.812, 100.000%

Path17

Path Summary:

Slack	0.411
Data Arrival Time	9.773
Data Required Time	10.184
From	u_mac_rx_model_word/pause_address_17_s1
To	u_mac_rx_model_word/pause_address_43_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.842	3.842	tNET	RR	1	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/CLK
4.224	0.382	tC2Q	RR	5	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/Q
4.744	0.520	tNET	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/I2
5.252	0.507	tINS	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/F
5.821	0.569	tNET	RR	1	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/I3
6.112	0.291	tINS	RR	2	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/F
6.853	0.741	tNET	RR	1	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/I2
7.309	0.456	tINS	RR	27	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/F
9.266	1.956	tNET	RR	1	R21C156[1][A]	u_mac_rx_model_word/n1594_s0/I0
9.773	0.507	tINS	RR	1	R21C156[1][A]	u_mac_rx_model_word/n1594_s0/F
9.773	0.000	tNET	RR	1	R21C156[1][A]	u_mac_rx_model_word/pause_address_43_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.248	3.848	tNET	RR	1	R21C156[1][A]	u_mac_rx_model_word/pause_address_43_s1/CLK
10.184	-0.064	tSu		1	R21C156[1][A]	u_mac_rx_model_word/pause_address_43_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.842, 100.000%
Arrival Data Path Delay	cell: 1.763, 29.715%; route: 3.786, 63.836%; tC2Q: 0.382, 6.449%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.848, 100.000%

Path18

Path Summary:

Slack	0.414
Data Arrival Time	9.813
Data Required Time	10.227
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_1_s1
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_1_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C142[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_1_s1/CLK
4.283	0.382	tC2Q	RR	10	R17C142[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_1_s1/Q
5.853	1.570	tNET	RR	2	R24C141[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1052_s0/I0
6.448	0.595	tINS	RF	1	R24C141[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1052_s0/COUT
6.448	0.000	tNET	FF	2	R24C141[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1053_s0/CIN
6.498	0.050	tINS	FR	1	R24C141[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1053_s0/COUT
6.498	0.000	tNET	RR	2	R24C141[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1054_s0/CIN
6.548	0.050	tINS	RR	1	R24C141[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1054_s0/COUT
6.548	0.000	tNET	RR	2	R24C141[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1055_s0/CIN
6.598	0.050	tINS	RR	1	R24C141[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1055_s0/COUT
6.598	0.000	tNET	RR	2	R24C141[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1056_s0/CIN
6.648	0.050	tINS	RR	1	R24C141[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1056_s0/COUT
6.648	0.000	tNET	RR	2	R24C142[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1057_s0/CIN
6.698	0.050	tINS	RR	1	R24C142[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1057_s0/COUT
6.698	0.000	tNET	RR	2	R24C142[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1058_s0/CIN
6.748	0.050	tINS	RR	1	R24C142[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1058_s0/COUT
6.748	0.000	tNET	RR	2	R24C142[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1059_s0/CIN
6.798	0.050	tINS	RR	1	R24C142[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1059_s0/COUT
6.798	0.000	tNET	RR	2	R24C142[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1060_s0/CIN
6.848	0.050	tINS	RR	1	R24C142[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1060_s0/COUT
6.848	0.000	tNET	RR	2	R24C142[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1061_s0/CIN
6.898	0.050	tINS	RR	1	R24C142[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1061_s0/COUT
6.898	0.000	tNET	RR	2	R24C142[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1062_s0/CIN
6.948	0.050	tINS	RR	1	R24C142[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1062_s0/COUT
6.948	0.000	tNET	RR	2	R24C143[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1063_s0/CIN
6.998	0.050	tINS	RR	1	R24C143[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1063_s0/COUT
6.998	0.000	tNET	RR	2	R24C143[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1064_s0/CIN
7.048	0.050	tINS	RR	1	R24C143[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1064_s0/COUT
7.048	0.000	tNET	RR	2	R24C143[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1065_s0/CIN
7.098	0.050	tINS	RR	1	R24C143[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1065_s0/COUT
7.098	0.000	tNET	RR	2	R24C143[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1066_s0/CIN
7.148	0.050	tINS	RR	1	R24C143[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1066_s0/COUT
7.603	0.455	tNET	RR	1	R22C143[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1103_s3/I0
7.891	0.289	tINS	RR	16	R22C143[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1103_s3/F
9.356	1.465	tNET	RR	1	R17C135[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1102_s2/I3
9.813	0.456	tINS	RR	1	R17C135[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/n1102_s2/F
9.813	0.000	tNET	RR	1	R17C135[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.291	3.891	tNET	RR	1	R17C135[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_1_s1/CLK
10.227	-0.064	tSu		1	R17C135[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_1_s1

Path Statistics:

Clock Skew	-0.009
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 2.040, 34.503%; route: 3.490, 59.027%; tC2Q: 0.382, 6.469%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.891, 100.000%

Path19

Path Summary:

Slack	0.455
Data Arrival Time	9.803
Data Required Time	10.258
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_3_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.917	3.917	tNET	RR	1	R26C138[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1/CLK
4.299	0.382	tC2Q	RR	25	R26C138[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_7_s1/Q
7.339	3.040	tNET	RR	1	R22C133[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n701_s8/I1
7.907	0.567	tINS	RR	1	R22C133[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n701_s8/F
8.118	0.211	tNET	RR	1	R22C131[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n701_s5/I3
8.685	0.567	tINS	RR	1	R22C131[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n701_s5/F
8.837	0.151	tNET	RR	1	R22C131[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n701_s3/I1
9.293	0.456	tINS	RR	1	R22C131[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n701_s3/F
9.295	0.003	tNET	RR	1	R22C131[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n701_s2/I2
9.803	0.507	tINS	RR	1	R22C131[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n701_s2/F
9.803	0.000	tNET	RR	1	R22C131[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.322	3.922	tNET	RR	1	R22C131[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_3_s1/CLK
10.258	-0.064	tSu		1	R22C131[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_3_s1

Path Statistics:

Clock Skew	0.005
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.917, 100.000%
Arrival Data Path Delay	cell: 2.099, 35.655%; route: 3.405, 57.847%; tC2Q: 0.382, 6.498%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.922, 100.000%

Path20

Path Summary:

Slack	0.469
Data Arrival Time	9.801
Data Required Time	10.270
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/K28_5_match_d5_0_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rudi_INVALID_m_set_s0
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.878	3.878	tNET	RR	1	R15C124[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/K28_5_match_d5_0_s0/CLK
4.260	0.382	tC2Q	RR	11	R15C124[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/K28_5_match_d5_0_s0/Q
6.919	2.659	tNET	RR	1	R22C121[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s10/I2
7.375	0.456	tINS	RR	1	R22C121[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s10/F
7.378	0.003	tNET	RR	1	R22C121[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s9/I3
7.834	0.456	tINS	RR	1	R22C121[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s9/F
7.985	0.151	tNET	RR	1	R22C121[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s6/I3
8.493	0.507	tINS	RR	1	R22C121[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s6/F
8.665	0.172	tNET	RR	1	R21C121[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s2/I3
9.121	0.456	tINS	RR	1	R21C121[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s2/F
9.294	0.172	tNET	RR	1	R21C122[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s1/I0
9.801	0.507	tINS	RR	1	R21C122[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s1/F
9.801	0.000	tNET	RR	1	R21C122[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rudi_INVALID_m_set_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.334	3.934	tNET	RR	1	R21C122[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rudi_INVALID_m_set_s0/CLK
10.270	-0.064	tSu		1	R21C122[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rudi_INVALID_m_set_s0

Path Statistics:

Clock Skew	0.056
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.878, 100.000%
Arrival Data Path Delay	cell: 2.384, 40.241%; route: 3.157, 53.302%; tC2Q: 0.382, 6.457%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.934, 100.000%

Path21

Path Summary:

Slack	0.475
Data Arrival Time	9.721
Data Required Time	10.196
From	u_mac_rx_model_word/pause_address_17_s1
To	u_mac_rx_model_word/pause_address_26_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.842	3.842	tNET	RR	1	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/CLK
4.224	0.382	tC2Q	RR	5	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/Q
4.744	0.520	tNET	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/I2
5.252	0.507	tINS	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/F
5.821	0.569	tNET	RR	1	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/I3
6.112	0.291	tINS	RR	2	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/F
6.853	0.741	tNET	RR	1	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/I2
7.309	0.456	tINS	RR	27	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/F
9.142	1.832	tNET	RR	1	R20C155[0][A]	u_mac_rx_model_word/n1611_s0/I0
9.721	0.579	tINS	RR	1	R20C155[0][A]	u_mac_rx_model_word/n1611_s0/F
9.721	0.000	tNET	RR	1	R20C155[0][A]	u_mac_rx_model_word/pause_address_26_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.259	3.859	tNET	RR	1	R20C155[0][A]	u_mac_rx_model_word/pause_address_26_s1/CLK
10.196	-0.064	tSu		1	R20C155[0][A]	u_mac_rx_model_word/pause_address_26_s1

Path Statistics:

Clock Skew	0.017
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.842, 100.000%
Arrival Data Path Delay	cell: 1.834, 31.193%; route: 3.663, 62.301%; tC2Q: 0.382, 6.506%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.859, 100.000%

Path22

Path Summary:

Slack	0.477
Data Arrival Time	9.776
Data Required Time	10.253
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/D21_5_match_d4_0_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_0_s3
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.889	3.889	tNET	RR	1	R16C125[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/D21_5_match_d4_0_s0/CLK
4.271	0.382	tC2Q	RR	3	R16C125[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/D21_5_match_d4_0_s0/Q
5.015	0.744	tNET	RR	1	R16C121[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s8/I0
5.583	0.567	tINS	RR	4	R16C121[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s8/F
6.329	0.746	tNET	RR	1	R18C124[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/idle_cnt_1_s6/I3
6.896	0.567	tINS	RR	1	R18C124[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/idle_cnt_1_s6/F
6.899	0.003	tNET	RR	1	R18C124[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/idle_cnt_1_s4/I0
7.466	0.567	tINS	RR	2	R18C124[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/idle_cnt_1_s4/F
8.358	0.891	tNET	RR	1	R21C121[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s4/I2
8.814	0.456	tINS	RR	2	R21C121[3][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s4/F
9.198	0.384	tNET	RR	1	R24C121[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n695_s4/I2
9.776	0.579	tINS	RR	1	R24C121[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n695_s4/F
9.776	0.000	tNET	RR	1	R24C121[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.317	3.917	tNET	RR	1	R24C121[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_0_s3/CLK
10.253	-0.064	tSu		1	R24C121[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_0_s3

Path Statistics:

Clock Skew	0.028
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.889, 100.000%
Arrival Data Path Delay	cell: 2.738, 46.497%; route: 2.768, 47.006%; tC2Q: 0.382, 6.497%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.917, 100.000%

Path23

Path Summary:

Slack	0.484
Data Arrival Time	9.748
Data Required Time	10.233
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_d1_4_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_er_m_set_l_s0
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.887	3.887	tNET	RR	1	R15C125[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_d1_4_s0/CLK
4.269	0.382	tC2Q	RR	14	R15C125[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_d1_4_s0/Q
5.542	1.273	tNET	RR	1	R20C122[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s7/I1
6.109	0.567	tINS	RR	5	R20C122[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1601_s7/F
6.117	0.008	tNET	RR	1	R20C122[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2191_s5/I3
6.624	0.507	tINS	RR	9	R20C122[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2191_s5/F
8.084	1.460	tNET	RR	1	R16C127[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2188_s7/I0
8.373	0.289	tINS	RR	1	R16C127[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2188_s7/F
8.546	0.172	tNET	RR	1	R16C126[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2188_s1/I3
9.002	0.456	tINS	RR	1	R16C126[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2188_s1/F
9.174	0.172	tNET	RR	1	R15C126[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2188_s8/I0
9.748	0.574	tINS	RR	1	R15C126[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2188_s8/F
9.748	0.000	tNET	RR	1	R15C126[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_er_m_set_l_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.296	3.896	tNET	RR	1	R15C126[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_er_m_set_l_s0/CLK
10.233	-0.064	tSu		1	R15C126[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_er_m_set_l_s0

Path Statistics:

Clock Skew	0.009
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.887, 100.000%
Arrival Data Path Delay	cell: 2.394, 40.840%; route: 3.085, 52.634%; tC2Q: 0.382, 6.526%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.896, 100.000%

Path24

Path Summary:

Slack	0.486
Data Arrival Time	9.662
Data Required Time	10.148
From	u_mac_rx_model_word/pause_address_22_s1
To	u_mac_rx_model_word/pause_address_33_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.859	3.859	tNET	RR	1	R20C153[1][A]	u_mac_rx_model_word/pause_address_22_s1/CLK
4.242	0.382	tC2Q	RR	5	R20C153[1][A]	u_mac_rx_model_word/pause_address_22_s1/Q
4.699	0.457	tNET	RR	1	R18C153[1][B]	u_mac_rx_model_word/n1612_s1/I2
5.207	0.507	tINS	RR	3	R18C153[1][B]	u_mac_rx_model_word/n1612_s1/F
5.951	0.744	tNET	RR	1	R20C155[1][A]	u_mac_rx_model_word/n1599_s2/I3
6.518	0.567	tINS	RR	7	R20C155[1][A]	u_mac_rx_model_word/n1599_s2/F
7.882	1.364	tNET	RR	1	R9C161[3][B]	u_mac_rx_model_word/n1600_s3/I2
8.338	0.456	tINS	RR	6	R9C161[3][B]	u_mac_rx_model_word/n1600_s3/F
9.373	1.035	tNET	RR	1	R16C156[2][A]	u_mac_rx_model_word/n1604_s0/I2
9.662	0.289	tINS	RR	1	R16C156[2][A]	u_mac_rx_model_word/n1604_s0/F
9.662	0.000	tNET	RR	1	R16C156[2][A]	u_mac_rx_model_word/pause_address_33_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.212	3.812	tNET	RR	1	R16C156[2][A]	u_mac_rx_model_word/pause_address_33_s1/CLK
10.148	-0.064	tSu		1	R16C156[2][A]	u_mac_rx_model_word/pause_address_33_s1

Path Statistics:

Clock Skew	-0.047
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.859, 100.000%
Arrival Data Path Delay	cell: 1.820, 31.366%; route: 3.600, 62.042%; tC2Q: 0.382, 6.592%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.812, 100.000%

Path25

Path Summary:

Slack	0.491
Data Arrival Time	9.693
Data Required Time	10.184
From	u_mac_rx_model_word/pause_address_17_s1
To	u_mac_rx_model_word/pause_address_28_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.842	3.842	tNET	RR	1	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/CLK
4.224	0.382	tC2Q	RR	5	R9C162[0][B]	u_mac_rx_model_word/pause_address_17_s1/Q
4.744	0.520	tNET	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/I2
5.252	0.507	tINS	RR	1	R12C162[0][B]	u_mac_rx_model_word/n1617_s4/F
5.821	0.569	tNET	RR	1	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/I3
6.112	0.291	tINS	RR	2	R14C160[3][B]	u_mac_rx_model_word/n1617_s1/F
6.853	0.741	tNET	RR	1	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/I2
7.309	0.456	tINS	RR	27	R17C159[3][A]	u_mac_rx_model_word/n1590_s1/F
9.114	1.805	tNET	RR	1	R21C156[0][A]	u_mac_rx_model_word/n1609_s0/I0
9.693	0.579	tINS	RR	1	R21C156[0][A]	u_mac_rx_model_word/n1609_s0/F
9.693	0.000	tNET	RR	1	R21C156[0][A]	u_mac_rx_model_word/pause_address_28_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.248	3.848	tNET	RR	1	R21C156[0][A]	u_mac_rx_model_word/pause_address_28_s1/CLK
10.184	-0.064	tSu		1	R21C156[0][A]	u_mac_rx_model_word/pause_address_28_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.842, 100.000%
Arrival Data Path Delay	cell: 1.834, 31.339%; route: 3.635, 62.123%; tC2Q: 0.382, 6.537%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.848, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.275
Data Arrival Time	1.747
Data Required Time	1.472
From	u_mac_rx_model_word/rx_cnt_16_s3
To	u_mac_rx_model_word/rx_cnt_16_s3
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.447	1.447	tNET	RR	1	R24C160[0][A]	u_mac_rx_model_word/rx_cnt_16_s3/CLK
1.588	0.141	tC2Q	RF	5	R24C160[0][A]	u_mac_rx_model_word/rx_cnt_16_s3/Q
1.594	0.006	tNET	FF	1	R24C160[0][A]	u_mac_rx_model_word/n2622_s7/I3
1.747	0.153	tINS	FF	1	R24C160[0][A]	u_mac_rx_model_word/n2622_s7/F
1.747	0.000	tNET	FF	1	R24C160[0][A]	u_mac_rx_model_word/rx_cnt_16_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.447	1.447	tNET	RR	1	R24C160[0][A]	u_mac_rx_model_word/rx_cnt_16_s3/CLK
1.472	0.025	tHld		1	R24C160[0][A]	u_mac_rx_model_word/rx_cnt_16_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.447, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.447, 100.000%

Path2

Path Summary:

Slack	0.275
Data Arrival Time	1.743
Data Required Time	1.468
From	u_mac_rx_model_word/rx_error_all_check_s4
To	u_mac_rx_model_word/rx_error_all_check_s4
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.443	1.443	tNET	RR	1	R27C154[1][A]	u_mac_rx_model_word/rx_error_all_check_s4/CLK
1.584	0.141	tC2Q	RF	2	R27C154[1][A]	u_mac_rx_model_word/rx_error_all_check_s4/Q
1.590	0.006	tNET	FF	1	R27C154[1][A]	u_mac_tx_model_word/n1072_s10/I1
1.743	0.153	tINS	FF	1	R27C154[1][A]	u_mac_tx_model_word/n1072_s10/F
1.743	0.000	tNET	FF	1	R27C154[1][A]	u_mac_rx_model_word/rx_error_all_check_s4/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.443	1.443	tNET	RR	1	R27C154[1][A]	u_mac_rx_model_word/rx_error_all_check_s4/CLK
1.468	0.025	tHld		1	R27C154[1][A]	u_mac_rx_model_word/rx_error_all_check_s4

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.443, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.443, 100.000%

Path3

Path Summary:

Slack	0.275
Data Arrival Time	1.754
Data Required Time	1.479
From	u_mac_rx_model_word/rx_cnt_20_s1
To	u_mac_rx_model_word/rx_cnt_20_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.454	1.454	tNET	RR	1	R22C157[0][A]	u_mac_rx_model_word/rx_cnt_20_s1/CLK
1.595	0.141	tC2Q	RF	4	R22C157[0][A]	u_mac_rx_model_word/rx_cnt_20_s1/Q
1.601	0.006	tNET	FF	1	R22C157[0][A]	u_mac_rx_model_word/n2618_s2/I3
1.754	0.153	tINS	FF	1	R22C157[0][A]	u_mac_rx_model_word/n2618_s2/F
1.754	0.000	tNET	FF	1	R22C157[0][A]	u_mac_rx_model_word/rx_cnt_20_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.454	1.454	tNET	RR	1	R22C157[0][A]	u_mac_rx_model_word/rx_cnt_20_s1/CLK
1.479	0.025	tHld		1	R22C157[0][A]	u_mac_rx_model_word/rx_cnt_20_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.454, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.454, 100.000%

Path4

Path Summary:

Slack	0.275
Data Arrival Time	1.740
Data Required Time	1.465
From	u_mac_rx_model_word/rx_data_cnt_pause_3_s1
To	u_mac_rx_model_word/rx_data_cnt_pause_3_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.440	1.440	tNET	RR	1	R18C162[1][A]	u_mac_rx_model_word/rx_data_cnt_pause_3_s1/CLK
1.581	0.141	tC2Q	RF	5	R18C162[1][A]	u_mac_rx_model_word/rx_data_cnt_pause_3_s1/Q
1.587	0.006	tNET	FF	1	R18C162[1][A]	u_mac_rx_model_word/n2370_s1/I2
1.740	0.153	tINS	FF	1	R18C162[1][A]	u_mac_rx_model_word/n2370_s1/F
1.740	0.000	tNET	FF	1	R18C162[1][A]	u_mac_rx_model_word/rx_data_cnt_pause_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.440	1.440	tNET	RR	1	R18C162[1][A]	u_mac_rx_model_word/rx_data_cnt_pause_3_s1/CLK
1.465	0.025	tHld		1	R18C162[1][A]	u_mac_rx_model_word/rx_data_cnt_pause_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.440, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.440, 100.000%

Path5

Path Summary:

Slack	0.275
Data Arrival Time	1.736
Data Required Time	1.461
From	u_mac_rx_model_word/rx_data_cnt_pause_5_s1
To	u_mac_rx_model_word/rx_data_cnt_pause_5_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R18C163[1][A]	u_mac_rx_model_word/rx_data_cnt_pause_5_s1/CLK
1.577	0.141	tC2Q	RF	3	R18C163[1][A]	u_mac_rx_model_word/rx_data_cnt_pause_5_s1/Q
1.583	0.006	tNET	FF	1	R18C163[1][A]	u_mac_rx_model_word/n2368_s1/I0
1.736	0.153	tINS	FF	1	R18C163[1][A]	u_mac_rx_model_word/n2368_s1/F
1.736	0.000	tNET	FF	1	R18C163[1][A]	u_mac_rx_model_word/rx_data_cnt_pause_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R18C163[1][A]	u_mac_rx_model_word/rx_data_cnt_pause_5_s1/CLK
1.461	0.025	tHld		1	R18C163[1][A]	u_mac_rx_model_word/rx_data_cnt_pause_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%

Path6

Path Summary:

Slack	0.275
Data Arrival Time	1.733
Data Required Time	1.458
From	u_mac_rx_model_word/shift_reg_pause_10_s1
To	u_mac_rx_model_word/shift_reg_pause_10_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.433	1.433	tNET	RR	1	R16C153[0][A]	u_mac_rx_model_word/shift_reg_pause_10_s1/CLK
1.574	0.141	tC2Q	RF	2	R16C153[0][A]	u_mac_rx_model_word/shift_reg_pause_10_s1/Q
1.580	0.006	tNET	FF	1	R16C153[0][A]	u_mac_rx_model_word/n2119_s0/I1
1.733	0.153	tINS	FF	1	R16C153[0][A]	u_mac_rx_model_word/n2119_s0/F
1.733	0.000	tNET	FF	1	R16C153[0][A]	u_mac_rx_model_word/shift_reg_pause_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.433	1.433	tNET	RR	1	R16C153[0][A]	u_mac_rx_model_word/shift_reg_pause_10_s1/CLK
1.458	0.025	tHld		1	R16C153[0][A]	u_mac_rx_model_word/shift_reg_pause_10_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%

Path7

Path Summary:

Slack	0.275
Data Arrival Time	1.735
Data Required Time	1.459
From	u_mac_rx_model_word/pause_address_21_s1
To	u_mac_rx_model_word/pause_address_21_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.434	1.434	tNET	RR	1	R17C153[1][A]	u_mac_rx_model_word/pause_address_21_s1/CLK
1.576	0.141	tC2Q	RF	6	R17C153[1][A]	u_mac_rx_model_word/pause_address_21_s1/Q
1.582	0.006	tNET	FF	1	R17C153[1][A]	u_mac_rx_model_word/n1616_s0/I2
1.735	0.153	tINS	FF	1	R17C153[1][A]	u_mac_rx_model_word/n1616_s0/F
1.735	0.000	tNET	FF	1	R17C153[1][A]	u_mac_rx_model_word/pause_address_21_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.434	1.434	tNET	RR	1	R17C153[1][A]	u_mac_rx_model_word/pause_address_21_s1/CLK
1.459	0.025	tHld		1	R17C153[1][A]	u_mac_rx_model_word/pause_address_21_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.434, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.434, 100.000%

Path8

Path Summary:

Slack	0.275
Data Arrival Time	1.752
Data Required Time	1.477
From	u_mac_rx_model_word/pause_address_28_s1
To	u_mac_rx_model_word/pause_address_28_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.452	1.452	tNET	RR	1	R21C156[0][A]	u_mac_rx_model_word/pause_address_28_s1/CLK
1.593	0.141	tC2Q	RF	4	R21C156[0][A]	u_mac_rx_model_word/pause_address_28_s1/Q
1.599	0.006	tNET	FF	1	R21C156[0][A]	u_mac_rx_model_word/n1609_s0/I3
1.752	0.153	tINS	FF	1	R21C156[0][A]	u_mac_rx_model_word/n1609_s0/F
1.752	0.000	tNET	FF	1	R21C156[0][A]	u_mac_rx_model_word/pause_address_28_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.452	1.452	tNET	RR	1	R21C156[0][A]	u_mac_rx_model_word/pause_address_28_s1/CLK
1.477	0.025	tHld		1	R21C156[0][A]	u_mac_rx_model_word/pause_address_28_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.452, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.452, 100.000%

Path9

Path Summary:

Slack	0.275
Data Arrival Time	1.739
Data Required Time	1.464
From	u_mac_rx_model_word/pause_address_35_s1
To	u_mac_rx_model_word/pause_address_35_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.439	1.439	tNET	RR	1	R9C159[0][A]	u_mac_rx_model_word/pause_address_35_s1/CLK
1.580	0.141	tC2Q	RF	5	R9C159[0][A]	u_mac_rx_model_word/pause_address_35_s1/Q
1.586	0.006	tNET	FF	1	R9C159[0][A]	u_mac_rx_model_word/n1602_s0/I3
1.739	0.153	tINS	FF	1	R9C159[0][A]	u_mac_rx_model_word/n1602_s0/F
1.739	0.000	tNET	FF	1	R9C159[0][A]	u_mac_rx_model_word/pause_address_35_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.439	1.439	tNET	RR	1	R9C159[0][A]	u_mac_rx_model_word/pause_address_35_s1/CLK
1.464	0.025	tHld		1	R9C159[0][A]	u_mac_rx_model_word/pause_address_35_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.439, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.439, 100.000%

Path10

Path Summary:

Slack	0.275
Data Arrival Time	1.739
Data Required Time	1.464
From	u_mac_rx_model_word/pause_address_47_s1
To	u_mac_rx_model_word/pause_address_47_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.439	1.439	tNET	RR	1	R17C154[0][A]	u_mac_rx_model_word/pause_address_47_s1/CLK
1.580	0.141	tC2Q	RF	2	R17C154[0][A]	u_mac_rx_model_word/pause_address_47_s1/Q
1.586	0.006	tNET	FF	1	R17C154[0][A]	u_mac_rx_model_word/n1590_s0/I3
1.739	0.153	tINS	FF	1	R17C154[0][A]	u_mac_rx_model_word/n1590_s0/F
1.739	0.000	tNET	FF	1	R17C154[0][A]	u_mac_rx_model_word/pause_address_47_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.439	1.439	tNET	RR	1	R17C154[0][A]	u_mac_rx_model_word/pause_address_47_s1/CLK
1.464	0.025	tHld		1	R17C154[0][A]	u_mac_rx_model_word/pause_address_47_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.439, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.439, 100.000%

Path11

Path Summary:

Slack	0.275
Data Arrival Time	1.753
Data Required Time	1.478
From	u_mac_rx_model_word/pause_value_0_s1
To	u_mac_rx_model_word/pause_value_0_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.453	1.453	tNET	RR	1	R23C159[1][A]	u_mac_rx_model_word/pause_value_0_s1/CLK
1.594	0.141	tC2Q	RF	9	R23C159[1][A]	u_mac_rx_model_word/pause_value_0_s1/Q
1.600	0.006	tNET	FF	1	R23C159[1][A]	u_mac_rx_model_word/n1518_s1/I0
1.753	0.153	tINS	FF	1	R23C159[1][A]	u_mac_rx_model_word/n1518_s1/F
1.753	0.000	tNET	FF	1	R23C159[1][A]	u_mac_rx_model_word/pause_value_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.453	1.453	tNET	RR	1	R23C159[1][A]	u_mac_rx_model_word/pause_value_0_s1/CLK
1.478	0.025	tHld		1	R23C159[1][A]	u_mac_rx_model_word/pause_value_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.453, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.453, 100.000%

Path12

Path Summary:

Slack	0.275
Data Arrival Time	1.756
Data Required Time	1.481
From	u_mac_rx_model_word/pause_value_1_s1
To	u_mac_rx_model_word/pause_value_1_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.456	1.456	tNET	RR	1	R21C155[0][A]	u_mac_rx_model_word/pause_value_1_s1/CLK
1.597	0.141	tC2Q	RF	6	R21C155[0][A]	u_mac_rx_model_word/pause_value_1_s1/Q
1.603	0.006	tNET	FF	1	R21C155[0][A]	u_mac_rx_model_word/n1517_s0/I2
1.756	0.153	tINS	FF	1	R21C155[0][A]	u_mac_rx_model_word/n1517_s0/F
1.756	0.000	tNET	FF	1	R21C155[0][A]	u_mac_rx_model_word/pause_value_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.456	1.456	tNET	RR	1	R21C155[0][A]	u_mac_rx_model_word/pause_value_1_s1/CLK
1.481	0.025	tHld		1	R21C155[0][A]	u_mac_rx_model_word/pause_value_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.456, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.456, 100.000%

Path13

Path Summary:

Slack	0.275
Data Arrival Time	1.760
Data Required Time	1.485
From	u_mac_rx_model_word/pause_value_5_s1
To	u_mac_rx_model_word/pause_value_5_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.460	1.460	tNET	RR	1	R21C154[0][A]	u_mac_rx_model_word/pause_value_5_s1/CLK
1.601	0.141	tC2Q	RF	5	R21C154[0][A]	u_mac_rx_model_word/pause_value_5_s1/Q
1.607	0.006	tNET	FF	1	R21C154[0][A]	u_mac_rx_model_word/n1513_s0/I2
1.760	0.153	tINS	FF	1	R21C154[0][A]	u_mac_rx_model_word/n1513_s0/F
1.760	0.000	tNET	FF	1	R21C154[0][A]	u_mac_rx_model_word/pause_value_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.460	1.460	tNET	RR	1	R21C154[0][A]	u_mac_rx_model_word/pause_value_5_s1/CLK
1.485	0.025	tHld		1	R21C154[0][A]	u_mac_rx_model_word/pause_value_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.460, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.460, 100.000%

Path14

Path Summary:

Slack	0.275
Data Arrival Time	1.724
Data Required Time	1.449
From	u_mac_rx_model_word/rx_data_cnt_1_s1
To	u_mac_rx_model_word/rx_data_cnt_1_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.424	1.424	tNET	RR	1	R13C161[1][A]	u_mac_rx_model_word/rx_data_cnt_1_s1/CLK
1.565	0.141	tC2Q	RF	5	R13C161[1][A]	u_mac_rx_model_word/rx_data_cnt_1_s1/Q
1.571	0.006	tNET	FF	1	R13C161[1][A]	u_mac_rx_model_word/n1257_s1/I2
1.724	0.153	tINS	FF	1	R13C161[1][A]	u_mac_rx_model_word/n1257_s1/F
1.724	0.000	tNET	FF	1	R13C161[1][A]	u_mac_rx_model_word/rx_data_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.424	1.424	tNET	RR	1	R13C161[1][A]	u_mac_rx_model_word/rx_data_cnt_1_s1/CLK
1.449	0.025	tHld		1	R13C161[1][A]	u_mac_rx_model_word/rx_data_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.424, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.424, 100.000%

Path15

Path Summary:

Slack	0.275
Data Arrival Time	1.758
Data Required Time	1.483
From	u_mac_rx_model_word/data_increase_add_1_0_s1
To	u_mac_rx_model_word/data_increase_add_1_0_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.458	1.458	tNET	RR	1	R20C157[0][A]	u_mac_rx_model_word/data_increase_add_1_0_s1/CLK
1.599	0.141	tC2Q	RF	2	R20C157[0][A]	u_mac_rx_model_word/data_increase_add_1_0_s1/Q
1.605	0.006	tNET	FF	1	R20C157[0][A]	u_mac_rx_model_word/n1166_s0/I0
1.758	0.153	tINS	FF	1	R20C157[0][A]	u_mac_rx_model_word/n1166_s0/F
1.758	0.000	tNET	FF	1	R20C157[0][A]	u_mac_rx_model_word/data_increase_add_1_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.458	1.458	tNET	RR	1	R20C157[0][A]	u_mac_rx_model_word/data_increase_add_1_0_s1/CLK
1.483	0.025	tHld		1	R20C157[0][A]	u_mac_rx_model_word/data_increase_add_1_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path16

Path Summary:

Slack	0.275
Data Arrival Time	1.736
Data Required Time	1.461
From	u_mac_rx_model_word/data_increase_add_1_7_s1
To	u_mac_rx_model_word/data_increase_add_1_7_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R15C154[0][A]	u_mac_rx_model_word/data_increase_add_1_7_s1/CLK
1.577	0.141	tC2Q	RF	2	R15C154[0][A]	u_mac_rx_model_word/data_increase_add_1_7_s1/Q
1.583	0.006	tNET	FF	1	R15C154[0][A]	u_mac_rx_model_word/n1159_s0/I1
1.736	0.153	tINS	FF	1	R15C154[0][A]	u_mac_rx_model_word/n1159_s0/F
1.736	0.000	tNET	FF	1	R15C154[0][A]	u_mac_rx_model_word/data_increase_add_1_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R15C154[0][A]	u_mac_rx_model_word/data_increase_add_1_7_s1/CLK
1.461	0.025	tHld		1	R15C154[0][A]	u_mac_rx_model_word/data_increase_add_1_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%

Path17

Path Summary:

Slack	0.275
Data Arrival Time	1.731
Data Required Time	1.456
From	u_mac_rx_model_word/data_increase_0_s1
To	u_mac_rx_model_word/data_increase_0_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.431	1.431	tNET	RR	1	R17C156[1][A]	u_mac_rx_model_word/data_increase_0_s1/CLK
1.572	0.141	tC2Q	RF	2	R17C156[1][A]	u_mac_rx_model_word/data_increase_0_s1/Q
1.578	0.006	tNET	FF	1	R17C156[1][A]	u_mac_rx_model_word/n1116_s0/I0
1.731	0.153	tINS	FF	1	R17C156[1][A]	u_mac_rx_model_word/n1116_s0/F
1.731	0.000	tNET	FF	1	R17C156[1][A]	u_mac_rx_model_word/data_increase_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.431	1.431	tNET	RR	1	R17C156[1][A]	u_mac_rx_model_word/data_increase_0_s1/CLK
1.456	0.025	tHld		1	R17C156[1][A]	u_mac_rx_model_word/data_increase_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.431, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.431, 100.000%

Path18

Path Summary:

Slack	0.275
Data Arrival Time	1.732
Data Required Time	1.457
From	u_mac_rx_model_word/shift_reg_0_s1
To	u_mac_rx_model_word/shift_reg_0_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.432	1.432	tNET	RR	1	R15C161[1][A]	u_mac_rx_model_word/shift_reg_0_s1/CLK
1.573	0.141	tC2Q	RF	2	R15C161[1][A]	u_mac_rx_model_word/shift_reg_0_s1/Q
1.579	0.006	tNET	FF	1	R15C161[1][A]	u_mac_rx_model_word/n955_s2/I2
1.732	0.153	tINS	FF	1	R15C161[1][A]	u_mac_rx_model_word/n955_s2/F
1.732	0.000	tNET	FF	1	R15C161[1][A]	u_mac_rx_model_word/shift_reg_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.432	1.432	tNET	RR	1	R15C161[1][A]	u_mac_rx_model_word/shift_reg_0_s1/CLK
1.457	0.025	tHld		1	R15C161[1][A]	u_mac_rx_model_word/shift_reg_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.432, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.432, 100.000%

Path19

Path Summary:

Slack	0.275
Data Arrival Time	1.732
Data Required Time	1.457
From	u_mac_rx_model_word/shift_reg_2_s1
To	u_mac_rx_model_word/shift_reg_2_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.432	1.432	tNET	RR	1	R15C161[0][A]	u_mac_rx_model_word/shift_reg_2_s1/CLK
1.573	0.141	tC2Q	RF	2	R15C161[0][A]	u_mac_rx_model_word/shift_reg_2_s1/Q
1.579	0.006	tNET	FF	1	R15C161[0][A]	u_mac_rx_model_word/n953_s2/I2
1.732	0.153	tINS	FF	1	R15C161[0][A]	u_mac_rx_model_word/n953_s2/F
1.732	0.000	tNET	FF	1	R15C161[0][A]	u_mac_rx_model_word/shift_reg_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.432	1.432	tNET	RR	1	R15C161[0][A]	u_mac_rx_model_word/shift_reg_2_s1/CLK
1.457	0.025	tHld		1	R15C161[0][A]	u_mac_rx_model_word/shift_reg_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.432, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.432, 100.000%

Path20

Path Summary:

Slack	0.275
Data Arrival Time	1.751
Data Required Time	1.476
From	u_mac_rx_model_word/shift_reg_4_s1
To	u_mac_rx_model_word/shift_reg_4_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.451	1.451	tNET	RR	1	R24C161[1][A]	u_mac_rx_model_word/shift_reg_4_s1/CLK
1.592	0.141	tC2Q	RF	2	R24C161[1][A]	u_mac_rx_model_word/shift_reg_4_s1/Q
1.598	0.006	tNET	FF	1	R24C161[1][A]	u_mac_rx_model_word/n951_s2/I2
1.751	0.153	tINS	FF	1	R24C161[1][A]	u_mac_rx_model_word/n951_s2/F
1.751	0.000	tNET	FF	1	R24C161[1][A]	u_mac_rx_model_word/shift_reg_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.451	1.451	tNET	RR	1	R24C161[1][A]	u_mac_rx_model_word/shift_reg_4_s1/CLK
1.476	0.025	tHld		1	R24C161[1][A]	u_mac_rx_model_word/shift_reg_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%

Path21

Path Summary:

Slack	0.275
Data Arrival Time	1.751
Data Required Time	1.476
From	u_mac_rx_model_word/shift_reg_9_s1
To	u_mac_rx_model_word/shift_reg_9_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.451	1.451	tNET	RR	1	R24C161[0][A]	u_mac_rx_model_word/shift_reg_9_s1/CLK
1.592	0.141	tC2Q	RF	2	R24C161[0][A]	u_mac_rx_model_word/shift_reg_9_s1/Q
1.598	0.006	tNET	FF	1	R24C161[0][A]	u_mac_rx_model_word/n946_s2/I2
1.751	0.153	tINS	FF	1	R24C161[0][A]	u_mac_rx_model_word/n946_s2/F
1.751	0.000	tNET	FF	1	R24C161[0][A]	u_mac_rx_model_word/shift_reg_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.451	1.451	tNET	RR	1	R24C161[0][A]	u_mac_rx_model_word/shift_reg_9_s1/CLK
1.476	0.025	tHld		1	R24C161[0][A]	u_mac_rx_model_word/shift_reg_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%

Path22

Path Summary:

Slack	0.275
Data Arrival Time	1.753
Data Required Time	1.478
From	u_mac_rx_model_word/shift_reg_11_s1
To	u_mac_rx_model_word/shift_reg_11_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.453	1.453	tNET	RR	1	R25C162[1][A]	u_mac_rx_model_word/shift_reg_11_s1/CLK
1.594	0.141	tC2Q	RF	2	R25C162[1][A]	u_mac_rx_model_word/shift_reg_11_s1/Q
1.600	0.006	tNET	FF	1	R25C162[1][A]	u_mac_rx_model_word/n944_s1/I1
1.753	0.153	tINS	FF	1	R25C162[1][A]	u_mac_rx_model_word/n944_s1/F
1.753	0.000	tNET	FF	1	R25C162[1][A]	u_mac_rx_model_word/shift_reg_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.453	1.453	tNET	RR	1	R25C162[1][A]	u_mac_rx_model_word/shift_reg_11_s1/CLK
1.478	0.025	tHld		1	R25C162[1][A]	u_mac_rx_model_word/shift_reg_11_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.453, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.453, 100.000%

Path23

Path Summary:

Slack	0.275
Data Arrival Time	1.749
Data Required Time	1.474
From	u_mac_rx_model_word/shift_reg_15_s1
To	u_mac_rx_model_word/shift_reg_15_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R25C161[1][A]	u_mac_rx_model_word/shift_reg_15_s1/CLK
1.590	0.141	tC2Q	RF	2	R25C161[1][A]	u_mac_rx_model_word/shift_reg_15_s1/Q
1.596	0.006	tNET	FF	1	R25C161[1][A]	u_mac_rx_model_word/n940_s2/I2
1.749	0.153	tINS	FF	1	R25C161[1][A]	u_mac_rx_model_word/n940_s2/F
1.749	0.000	tNET	FF	1	R25C161[1][A]	u_mac_rx_model_word/shift_reg_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R25C161[1][A]	u_mac_rx_model_word/shift_reg_15_s1/CLK
1.474	0.025	tHld		1	R25C161[1][A]	u_mac_rx_model_word/shift_reg_15_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%

Path24

Path Summary:

Slack	0.275
Data Arrival Time	1.757
Data Required Time	1.482
From	u_mac_rx_model_word/shift_reg_19_s1
To	u_mac_rx_model_word/shift_reg_19_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.457	1.457	tNET	RR	1	R23C162[0][A]	u_mac_rx_model_word/shift_reg_19_s1/CLK
1.598	0.141	tC2Q	RF	2	R23C162[0][A]	u_mac_rx_model_word/shift_reg_19_s1/Q
1.604	0.006	tNET	FF	1	R23C162[0][A]	u_mac_rx_model_word/n936_s2/I0
1.757	0.153	tINS	FF	1	R23C162[0][A]	u_mac_rx_model_word/n936_s2/F
1.757	0.000	tNET	FF	1	R23C162[0][A]	u_mac_rx_model_word/shift_reg_19_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.457	1.457	tNET	RR	1	R23C162[0][A]	u_mac_rx_model_word/shift_reg_19_s1/CLK
1.482	0.025	tHld		1	R23C162[0][A]	u_mac_rx_model_word/shift_reg_19_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.457, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.457, 100.000%

Path25

Path Summary:

Slack	0.275
Data Arrival Time	1.749
Data Required Time	1.474
From	u_mac_rx_model_word/shift_reg_25_s1
To	u_mac_rx_model_word/shift_reg_25_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R25C161[0][A]	u_mac_rx_model_word/shift_reg_25_s1/CLK
1.590	0.141	tC2Q	RF	2	R25C161[0][A]	u_mac_rx_model_word/shift_reg_25_s1/Q
1.596	0.006	tNET	FF	1	R25C161[0][A]	u_mac_rx_model_word/n930_s2/I0
1.749	0.153	tINS	FF	1	R25C161[0][A]	u_mac_rx_model_word/n930_s2/F
1.749	0.000	tNET	FF	1	R25C161[0][A]	u_mac_rx_model_word/shift_reg_25_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R25C161[0][A]	u_mac_rx_model_word/shift_reg_25_s1/CLK
1.474	0.025	tHld		1	R25C161[0][A]	u_mac_rx_model_word/shift_reg_25_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.005
Data Arrival Time	9.955
Data Required Time	9.960
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_5_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.955	5.688	tNET	FF	1	R24C144[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.308	3.908	tNET	RR	1	R24C144[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_5_s1/CLK
9.960	-0.347	tSu		1	R24C144[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_5_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.688, 93.931%; tC2Q: 0.368, 6.069%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%

Path2

Path Summary:

Slack	0.005
Data Arrival Time	9.955
Data Required Time	9.960
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_11_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.955	5.688	tNET	FF	1	R24C144[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.308	3.908	tNET	RR	1	R24C144[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_11_s1/CLK
9.960	-0.347	tSu		1	R24C144[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_11_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.688, 93.931%; tC2Q: 0.368, 6.069%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%

Path3

Path Summary:

Slack	0.005
Data Arrival Time	9.955
Data Required Time	9.960
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_12_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.955	5.688	tNET	FF	1	R24C144[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_12_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.308	3.908	tNET	RR	1	R24C144[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_12_s1/CLK
9.960	-0.347	tSu		1	R24C144[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_12_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.688, 93.931%; tC2Q: 0.368, 6.069%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%

Path4

Path Summary:

Slack	0.005
Data Arrival Time	9.955
Data Required Time	9.960
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_13_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.955	5.688	tNET	FF	1	R24C144[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_13_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.308	3.908	tNET	RR	1	R24C144[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_13_s1/CLK
9.960	-0.347	tSu		1	R24C144[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_13_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.688, 93.931%; tC2Q: 0.368, 6.069%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%

Path5

Path Summary:

Slack	0.005
Data Arrival Time	9.955
Data Required Time	9.960
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_15_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.955	5.688	tNET	FF	1	R24C144[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_15_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.308	3.908	tNET	RR	1	R24C144[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_15_s1/CLK
9.960	-0.347	tSu		1	R24C144[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_15_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.688, 93.931%; tC2Q: 0.368, 6.069%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%

Path6

Path Summary:

Slack	0.177
Data Arrival Time	9.783
Data Required Time	9.960
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_2_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.783	5.515	tNET	FF	1	R26C143[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.307	3.907	tNET	RR	1	R26C143[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_2_s1/CLK
9.960	-0.347	tSu		1	R26C143[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_2_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.515, 93.753%; tC2Q: 0.368, 6.247%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path7

Path Summary:

Slack	0.177
Data Arrival Time	9.783
Data Required Time	9.960
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_6_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.783	5.515	tNET	FF	1	R26C143[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.307	3.907	tNET	RR	1	R26C143[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_6_s1/CLK
9.960	-0.347	tSu		1	R26C143[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_6_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.515, 93.753%; tC2Q: 0.368, 6.247%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path8

Path Summary:

Slack	0.177
Data Arrival Time	9.783
Data Required Time	9.960
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_14_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.783	5.515	tNET	FF	1	R26C143[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_14_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.307	3.907	tNET	RR	1	R26C143[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_14_s1/CLK
9.960	-0.347	tSu		1	R26C143[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_14_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.515, 93.753%; tC2Q: 0.368, 6.247%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path9

Path Summary:

Slack	0.218
Data Arrival Time	9.756
Data Required Time	9.974
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_13_s3
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.756	5.489	tNET	FF	1	R22C145[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_13_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.322	3.922	tNET	RR	1	R22C145[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_13_s3/CLK
9.974	-0.347	tSu		1	R22C145[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_13_s3

Path Statistics:

Clock Skew	0.022
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.489, 93.725%; tC2Q: 0.368, 6.275%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.922, 100.000%

Path10

Path Summary:

Slack	0.218
Data Arrival Time	9.756
Data Required Time	9.974
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_14_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.756	5.489	tNET	FF	1	R22C145[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_14_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.322	3.922	tNET	RR	1	R22C145[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_14_s1/CLK
9.974	-0.347	tSu		1	R22C145[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_14_s1

Path Statistics:

Clock Skew	0.022
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.489, 93.725%; tC2Q: 0.368, 6.275%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.922, 100.000%

Path11

Path Summary:

Slack	0.218
Data Arrival Time	9.756
Data Required Time	9.974
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_15_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.756	5.489	tNET	FF	1	R22C145[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_15_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.322	3.922	tNET	RR	1	R22C145[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_15_s1/CLK
9.974	-0.347	tSu		1	R22C145[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_15_s1

Path Statistics:

Clock Skew	0.022
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.489, 93.725%; tC2Q: 0.368, 6.275%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.922, 100.000%

Path12

Path Summary:

Slack	0.218
Data Arrival Time	9.756
Data Required Time	9.974
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_16_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.756	5.489	tNET	FF	1	R22C145[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_16_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.322	3.922	tNET	RR	1	R22C145[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_16_s1/CLK
9.974	-0.347	tSu		1	R22C145[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_16_s1

Path Statistics:

Clock Skew	0.022
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.489, 93.725%; tC2Q: 0.368, 6.275%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.922, 100.000%

Path13

Path Summary:

Slack	0.218
Data Arrival Time	9.756
Data Required Time	9.974
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_17_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.756	5.489	tNET	FF	1	R22C145[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_17_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.322	3.922	tNET	RR	1	R22C145[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_17_s1/CLK
9.974	-0.347	tSu		1	R22C145[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_17_s1

Path Statistics:

Clock Skew	0.022
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.489, 93.725%; tC2Q: 0.368, 6.275%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.922, 100.000%

Path14

Path Summary:

Slack	0.221
Data Arrival Time	9.736
Data Required Time	9.958
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_2_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.736	5.469	tNET	FF	1	R25C144[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.305	3.905	tNET	RR	1	R25C144[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_2_s1/CLK
9.958	-0.347	tSu		1	R25C144[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_2_s1

Path Statistics:

Clock Skew	0.005
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.469, 93.703%; tC2Q: 0.368, 6.297%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.905, 100.000%

Path15

Path Summary:

Slack	0.221
Data Arrival Time	9.736
Data Required Time	9.958
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_6_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.736	5.469	tNET	FF	1	R25C144[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.305	3.905	tNET	RR	1	R25C144[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_6_s1/CLK
9.958	-0.347	tSu		1	R25C144[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_6_s1

Path Statistics:

Clock Skew	0.005
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.469, 93.703%; tC2Q: 0.368, 6.297%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.905, 100.000%

Path16

Path Summary:

Slack	0.221
Data Arrival Time	9.736
Data Required Time	9.958
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_7_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.736	5.469	tNET	FF	1	R25C144[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.305	3.905	tNET	RR	1	R25C144[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_7_s1/CLK
9.958	-0.347	tSu		1	R25C144[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/type_reg_7_s1

Path Statistics:

Clock Skew	0.005
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.469, 93.703%; tC2Q: 0.368, 6.297%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.905, 100.000%

Path17

Path Summary:

Slack	0.231
Data Arrival Time	9.736
Data Required Time	9.967
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_5_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.736	5.469	tNET	FF	1	R25C143[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.314	3.914	tNET	RR	1	R25C143[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_5_s1/CLK
9.967	-0.347	tSu		1	R25C143[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_5_s1

Path Statistics:

Clock Skew	0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.469, 93.703%; tC2Q: 0.368, 6.297%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.914, 100.000%

Path18

Path Summary:

Slack	0.231
Data Arrival Time	9.736
Data Required Time	9.967
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_10_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.736	5.469	tNET	FF	1	R25C143[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.314	3.914	tNET	RR	1	R25C143[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_10_s1/CLK
9.967	-0.347	tSu		1	R25C143[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_10_s1

Path Statistics:

Clock Skew	0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.469, 93.703%; tC2Q: 0.368, 6.297%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.914, 100.000%

Path19

Path Summary:

Slack	0.231
Data Arrival Time	9.736
Data Required Time	9.967
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_11_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.736	5.469	tNET	FF	1	R25C143[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.314	3.914	tNET	RR	1	R25C143[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_11_s1/CLK
9.967	-0.347	tSu		1	R25C143[2][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_11_s1

Path Statistics:

Clock Skew	0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.469, 93.703%; tC2Q: 0.368, 6.297%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.914, 100.000%

Path20

Path Summary:

Slack	0.231
Data Arrival Time	9.736
Data Required Time	9.967
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_12_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.736	5.469	tNET	FF	1	R25C143[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_12_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.314	3.914	tNET	RR	1	R25C143[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_12_s1/CLK
9.967	-0.347	tSu		1	R25C143[2][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_12_s1

Path Statistics:

Clock Skew	0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.469, 93.703%; tC2Q: 0.368, 6.297%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.914, 100.000%

Path21

Path Summary:

Slack	0.231
Data Arrival Time	9.736
Data Required Time	9.967
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_13_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.736	5.469	tNET	FF	1	R25C143[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_13_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.314	3.914	tNET	RR	1	R25C143[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_13_s1/CLK
9.967	-0.347	tSu		1	R25C143[1][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_13_s1

Path Statistics:

Clock Skew	0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.469, 93.703%; tC2Q: 0.368, 6.297%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.914, 100.000%

Path22

Path Summary:

Slack	0.231
Data Arrival Time	9.736
Data Required Time	9.967
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_15_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.736	5.469	tNET	FF	1	R25C143[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_15_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.314	3.914	tNET	RR	1	R25C143[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_15_s1/CLK
9.967	-0.347	tSu		1	R25C143[3][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/op_reg_15_s1

Path Statistics:

Clock Skew	0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.469, 93.703%; tC2Q: 0.368, 6.297%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.914, 100.000%

Path23

Path Summary:

Slack	0.387
Data Arrival Time	9.573
Data Required Time	9.960
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_4_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.573	5.305	tNET	FF	1	R26C141[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.307	3.907	tNET	RR	1	R26C141[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_4_s1/CLK
9.960	-0.347	tSu		1	R26C141[1][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_4_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.305, 93.521%; tC2Q: 0.368, 6.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path24

Path Summary:

Slack	0.387
Data Arrival Time	9.573
Data Required Time	9.960
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_20_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.573	5.305	tNET	FF	1	R26C141[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_20_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.307	3.907	tNET	RR	1	R26C141[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_20_s1/CLK
9.960	-0.347	tSu		1	R26C141[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_20_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.305, 93.521%; tC2Q: 0.368, 6.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path25

Path Summary:

Slack	0.387
Data Arrival Time	9.573
Data Required Time	9.960
From	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0
To	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_36_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK
4.267	0.368	tC2Q	RF	1007	R17C130[0][A]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q
9.573	5.305	tNET	FF	1	R26C141[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_36_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					rx_mac_clk
6.400	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
10.307	3.907	tNET	RR	1	R26C141[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_36_s1/CLK
9.960	-0.347	tSu		1	R26C141[0][B]	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_36_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.305, 93.521%; tC2Q: 0.368, 6.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.284
Data Arrival Time	2.991
Data Required Time	2.707
From	u_pll_uart/u_pll_init/enable_r_1_s0
To	u_pll_uart/u_pll_init/RomAddr_3_s1
Launch Clk	board_clk:[R]
Latch Clk	board_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					board_clk
0.000	0.000	tCL	RR	1	IOR103[B]	board_clk_ibuf/I
0.675	0.675	tINS	RR	40	IOR103[B]	board_clk_ibuf/O
2.760	2.085	tNET	RR	1	R41C161[2][B]	u_pll_uart/u_pll_init/enable_r_1_s0/CLK
2.904	0.144	tC2Q	RR	20	R41C161[2][B]	u_pll_uart/u_pll_init/enable_r_1_s0/Q
2.991	0.087	tNET	RR	1	R41C161[0][A]	u_pll_uart/u_pll_init/RomAddr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					board_clk
0.000	0.000	tCL	RR	1	IOR103[B]	board_clk_ibuf/I
0.675	0.675	tINS	RR	40	IOR103[B]	board_clk_ibuf/O
2.760	2.085	tNET	RR	1	R41C161[0][A]	u_pll_uart/u_pll_init/RomAddr_3_s1/CLK
2.707	-0.053	tHld		1	R41C161[0][A]	u_pll_uart/u_pll_init/RomAddr_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 24.475%; route: 2.085, 75.525%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.087, 37.662%; tC2Q: 0.144, 62.338%
Required Clock Path Delay	cell: 0.675, 24.475%; route: 2.085, 75.525%

Path2

Path Summary:

Slack	0.304
Data Arrival Time	1.709
Data Required Time	1.405
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/data_length_next_7_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.709	0.115	tNET	RR	1	R22C150[0][A]	u_mac_rx_model_word/data_length_next_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.458	1.458	tNET	RR	1	R22C150[0][A]	u_mac_rx_model_word/data_length_next_7_s1/CLK
1.405	-0.053	tHld		1	R22C150[0][A]	u_mac_rx_model_word/data_length_next_7_s1

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.115, 44.402%; tC2Q: 0.144, 55.598%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path3

Path Summary:

Slack	0.304
Data Arrival Time	1.709
Data Required Time	1.405
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/data_length_next_8_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.709	0.115	tNET	RR	1	R22C150[0][B]	u_mac_rx_model_word/data_length_next_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.458	1.458	tNET	RR	1	R22C150[0][B]	u_mac_rx_model_word/data_length_next_8_s1/CLK
1.405	-0.053	tHld		1	R22C150[0][B]	u_mac_rx_model_word/data_length_next_8_s1

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.115, 44.402%; tC2Q: 0.144, 55.598%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path4

Path Summary:

Slack	0.304
Data Arrival Time	1.709
Data Required Time	1.405
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/data_length_next_9_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.709	0.115	tNET	RR	1	R22C150[1][A]	u_mac_rx_model_word/data_length_next_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.458	1.458	tNET	RR	1	R22C150[1][A]	u_mac_rx_model_word/data_length_next_9_s1/CLK
1.405	-0.053	tHld		1	R22C150[1][A]	u_mac_rx_model_word/data_length_next_9_s1

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.115, 44.402%; tC2Q: 0.144, 55.598%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path5

Path Summary:

Slack	0.304
Data Arrival Time	1.709
Data Required Time	1.405
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/data_length_next_10_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.709	0.115	tNET	RR	1	R22C150[1][B]	u_mac_rx_model_word/data_length_next_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.458	1.458	tNET	RR	1	R22C150[1][B]	u_mac_rx_model_word/data_length_next_10_s1/CLK
1.405	-0.053	tHld		1	R22C150[1][B]	u_mac_rx_model_word/data_length_next_10_s1

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.115, 44.402%; tC2Q: 0.144, 55.598%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path6

Path Summary:

Slack	0.304
Data Arrival Time	1.709
Data Required Time	1.405
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/data_length_next_11_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.709	0.115	tNET	RR	1	R22C150[2][A]	u_mac_rx_model_word/data_length_next_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.458	1.458	tNET	RR	1	R22C150[2][A]	u_mac_rx_model_word/data_length_next_11_s1/CLK
1.405	-0.053	tHld		1	R22C150[2][A]	u_mac_rx_model_word/data_length_next_11_s1

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.115, 44.402%; tC2Q: 0.144, 55.598%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path7

Path Summary:

Slack	0.304
Data Arrival Time	1.709
Data Required Time	1.405
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/data_length_next_12_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.709	0.115	tNET	RR	1	R22C150[2][B]	u_mac_rx_model_word/data_length_next_12_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.458	1.458	tNET	RR	1	R22C150[2][B]	u_mac_rx_model_word/data_length_next_12_s1/CLK
1.405	-0.053	tHld		1	R22C150[2][B]	u_mac_rx_model_word/data_length_next_12_s1

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.115, 44.402%; tC2Q: 0.144, 55.598%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path8

Path Summary:

Slack	0.306
Data Arrival Time	1.711
Data Required Time	1.405
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/rx_cnt_13_s3
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.711	0.117	tNET	RR	1	R22C154[1][B]	u_mac_rx_model_word/rx_cnt_13_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.458	1.458	tNET	RR	1	R22C154[1][B]	u_mac_rx_model_word/rx_cnt_13_s3/CLK
1.405	-0.053	tHld		1	R22C154[1][B]	u_mac_rx_model_word/rx_cnt_13_s3

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 44.828%; tC2Q: 0.144, 55.172%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path9

Path Summary:

Slack	0.306
Data Arrival Time	1.711
Data Required Time	1.405
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/rx_cnt_5_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.711	0.117	tNET	RR	1	R22C154[0][A]	u_mac_rx_model_word/rx_cnt_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.458	1.458	tNET	RR	1	R22C154[0][A]	u_mac_rx_model_word/rx_cnt_5_s1/CLK
1.405	-0.053	tHld		1	R22C154[0][A]	u_mac_rx_model_word/rx_cnt_5_s1

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 44.828%; tC2Q: 0.144, 55.172%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path10

Path Summary:

Slack	0.306
Data Arrival Time	1.711
Data Required Time	1.405
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/rx_cnt_14_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.711	0.117	tNET	RR	1	R22C154[0][B]	u_mac_rx_model_word/rx_cnt_14_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.458	1.458	tNET	RR	1	R22C154[0][B]	u_mac_rx_model_word/rx_cnt_14_s1/CLK
1.405	-0.053	tHld		1	R22C154[0][B]	u_mac_rx_model_word/rx_cnt_14_s1

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 44.828%; tC2Q: 0.144, 55.172%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path11

Path Summary:

Slack	0.310
Data Arrival Time	1.711
Data Required Time	1.401
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/data_length_13_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.711	0.117	tNET	RR	1	R22C153[0][A]	u_mac_rx_model_word/data_length_13_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.454	1.454	tNET	RR	1	R22C153[0][A]	u_mac_rx_model_word/data_length_13_s1/CLK
1.401	-0.053	tHld		1	R22C153[0][A]	u_mac_rx_model_word/data_length_13_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 44.828%; tC2Q: 0.144, 55.172%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.454, 100.000%

Path12

Path Summary:

Slack	0.380
Data Arrival Time	1.766
Data Required Time	1.387
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/shift_reg_pause_63_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.766	0.172	tNET	RR	1	R18C150[1][A]	u_mac_rx_model_word/shift_reg_pause_63_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.440	1.440	tNET	RR	1	R18C150[1][A]	u_mac_rx_model_word/shift_reg_pause_63_s1/CLK
1.387	-0.053	tHld		1	R18C150[1][A]	u_mac_rx_model_word/shift_reg_pause_63_s1

Path Statistics:

Clock Skew	-0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.172, 54.430%; tC2Q: 0.144, 45.570%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.440, 100.000%

Path13

Path Summary:

Slack	0.380
Data Arrival Time	1.766
Data Required Time	1.387
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/shift_reg_pause_77_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.766	0.172	tNET	RR	1	R18C150[0][B]	u_mac_rx_model_word/shift_reg_pause_77_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.440	1.440	tNET	RR	1	R18C150[0][B]	u_mac_rx_model_word/shift_reg_pause_77_s1/CLK
1.387	-0.053	tHld		1	R18C150[0][B]	u_mac_rx_model_word/shift_reg_pause_77_s1

Path Statistics:

Clock Skew	-0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.172, 54.430%; tC2Q: 0.144, 45.570%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.440, 100.000%

Path14

Path Summary:

Slack	0.380
Data Arrival Time	1.766
Data Required Time	1.387
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/shift_reg_pause_79_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.766	0.172	tNET	RR	1	R18C150[1][B]	u_mac_rx_model_word/shift_reg_pause_79_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.440	1.440	tNET	RR	1	R18C150[1][B]	u_mac_rx_model_word/shift_reg_pause_79_s1/CLK
1.387	-0.053	tHld		1	R18C150[1][B]	u_mac_rx_model_word/shift_reg_pause_79_s1

Path Statistics:

Clock Skew	-0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.172, 54.430%; tC2Q: 0.144, 45.570%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.440, 100.000%

Path15

Path Summary:

Slack	0.380
Data Arrival Time	1.766
Data Required Time	1.387
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/shift_reg_pause_80_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.766	0.172	tNET	RR	1	R18C150[0][A]	u_mac_rx_model_word/shift_reg_pause_80_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.440	1.440	tNET	RR	1	R18C150[0][A]	u_mac_rx_model_word/shift_reg_pause_80_s1/CLK
1.387	-0.053	tHld		1	R18C150[0][A]	u_mac_rx_model_word/shift_reg_pause_80_s1

Path Statistics:

Clock Skew	-0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.172, 54.430%; tC2Q: 0.144, 45.570%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.440, 100.000%

Path16

Path Summary:

Slack	0.382
Data Arrival Time	3.093
Data Required Time	2.711
From	u_pll_uart/u_pll_init/enable_r_1_s0
To	u_pll_uart/u_pll_init/RomAddr_1_s1
Launch Clk	board_clk:[R]
Latch Clk	board_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					board_clk
0.000	0.000	tCL	RR	1	IOR103[B]	board_clk_ibuf/I
0.675	0.675	tINS	RR	40	IOR103[B]	board_clk_ibuf/O
2.760	2.085	tNET	RR	1	R41C161[2][B]	u_pll_uart/u_pll_init/enable_r_1_s0/CLK
2.904	0.144	tC2Q	RR	20	R41C161[2][B]	u_pll_uart/u_pll_init/enable_r_1_s0/Q
3.093	0.189	tNET	RR	1	R41C162[0][A]	u_pll_uart/u_pll_init/RomAddr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					board_clk
0.000	0.000	tCL	RR	1	IOR103[B]	board_clk_ibuf/I
0.675	0.675	tINS	RR	40	IOR103[B]	board_clk_ibuf/O
2.764	2.089	tNET	RR	1	R41C162[0][A]	u_pll_uart/u_pll_init/RomAddr_1_s1/CLK
2.711	-0.053	tHld		1	R41C162[0][A]	u_pll_uart/u_pll_init/RomAddr_1_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 24.475%; route: 2.085, 75.525%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay	cell: 0.675, 24.439%; route: 2.089, 75.561%

Path17

Path Summary:

Slack	0.382
Data Arrival Time	3.093
Data Required Time	2.711
From	u_pll_uart/u_pll_init/enable_r_1_s0
To	u_pll_uart/u_pll_init/RomAddr_2_s1
Launch Clk	board_clk:[R]
Latch Clk	board_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					board_clk
0.000	0.000	tCL	RR	1	IOR103[B]	board_clk_ibuf/I
0.675	0.675	tINS	RR	40	IOR103[B]	board_clk_ibuf/O
2.760	2.085	tNET	RR	1	R41C161[2][B]	u_pll_uart/u_pll_init/enable_r_1_s0/CLK
2.904	0.144	tC2Q	RR	20	R41C161[2][B]	u_pll_uart/u_pll_init/enable_r_1_s0/Q
3.093	0.189	tNET	RR	1	R41C162[0][B]	u_pll_uart/u_pll_init/RomAddr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					board_clk
0.000	0.000	tCL	RR	1	IOR103[B]	board_clk_ibuf/I
0.675	0.675	tINS	RR	40	IOR103[B]	board_clk_ibuf/O
2.764	2.089	tNET	RR	1	R41C162[0][B]	u_pll_uart/u_pll_init/RomAddr_2_s1/CLK
2.711	-0.053	tHld		1	R41C162[0][B]	u_pll_uart/u_pll_init/RomAddr_2_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 24.475%; route: 2.085, 75.525%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay	cell: 0.675, 24.439%; route: 2.089, 75.561%

Path18

Path Summary:

Slack	0.383
Data Arrival Time	1.766
Data Required Time	1.383
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/shift_reg_pause_15_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.766	0.172	tNET	RR	1	R18C151[0][B]	u_mac_rx_model_word/shift_reg_pause_15_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R18C151[0][B]	u_mac_rx_model_word/shift_reg_pause_15_s1/CLK
1.383	-0.053	tHld		1	R18C151[0][B]	u_mac_rx_model_word/shift_reg_pause_15_s1

Path Statistics:

Clock Skew	-0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.172, 54.430%; tC2Q: 0.144, 45.570%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%

Path19

Path Summary:

Slack	0.383
Data Arrival Time	1.766
Data Required Time	1.383
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/pause_data_3_15_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.766	0.172	tNET	RR	1	R18C151[3][A]	u_mac_rx_model_word/pause_data_3_15_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R18C151[3][A]	u_mac_rx_model_word/pause_data_3_15_s1/CLK
1.383	-0.053	tHld		1	R18C151[3][A]	u_mac_rx_model_word/pause_data_3_15_s1

Path Statistics:

Clock Skew	-0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.172, 54.430%; tC2Q: 0.144, 45.570%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%

Path20

Path Summary:

Slack	0.383
Data Arrival Time	1.766
Data Required Time	1.383
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/pause_data_2_15_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.766	0.172	tNET	RR	1	R18C151[0][A]	u_mac_rx_model_word/pause_data_2_15_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R18C151[0][A]	u_mac_rx_model_word/pause_data_2_15_s1/CLK
1.383	-0.053	tHld		1	R18C151[0][A]	u_mac_rx_model_word/pause_data_2_15_s1

Path Statistics:

Clock Skew	-0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.172, 54.430%; tC2Q: 0.144, 45.570%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%

Path21

Path Summary:

Slack	0.383
Data Arrival Time	1.766
Data Required Time	1.383
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/pause_data_2_29_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.766	0.172	tNET	RR	1	R18C151[2][A]	u_mac_rx_model_word/pause_data_2_29_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R18C151[2][A]	u_mac_rx_model_word/pause_data_2_29_s1/CLK
1.383	-0.053	tHld		1	R18C151[2][A]	u_mac_rx_model_word/pause_data_2_29_s1

Path Statistics:

Clock Skew	-0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.172, 54.430%; tC2Q: 0.144, 45.570%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%

Path22

Path Summary:

Slack	0.383
Data Arrival Time	1.766
Data Required Time	1.383
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/pause_data_2_31_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.766	0.172	tNET	RR	1	R18C151[1][A]	u_mac_rx_model_word/pause_data_2_31_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R18C151[1][A]	u_mac_rx_model_word/pause_data_2_31_s1/CLK
1.383	-0.053	tHld		1	R18C151[1][A]	u_mac_rx_model_word/pause_data_2_31_s1

Path Statistics:

Clock Skew	-0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.172, 54.430%; tC2Q: 0.144, 45.570%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%

Path23

Path Summary:

Slack	0.383
Data Arrival Time	1.766
Data Required Time	1.383
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/pause_data_2_32_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.766	0.172	tNET	RR	1	R18C151[1][B]	u_mac_rx_model_word/pause_data_2_32_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R18C151[1][B]	u_mac_rx_model_word/pause_data_2_32_s1/CLK
1.383	-0.053	tHld		1	R18C151[1][B]	u_mac_rx_model_word/pause_data_2_32_s1

Path Statistics:

Clock Skew	-0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.172, 54.430%; tC2Q: 0.144, 45.570%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%

Path24

Path Summary:

Slack	0.385
Data Arrival Time	1.764
Data Required Time	1.379
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/shift_reg_pause_143_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.764	0.170	tNET	RR	1	R14C150[0][A]	u_mac_rx_model_word/shift_reg_pause_143_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.432	1.432	tNET	RR	1	R14C150[0][A]	u_mac_rx_model_word/shift_reg_pause_143_s1/CLK
1.379	-0.053	tHld		1	R14C150[0][A]	u_mac_rx_model_word/shift_reg_pause_143_s1

Path Statistics:

Clock Skew	-0.018
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.170, 54.140%; tC2Q: 0.144, 45.860%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.432, 100.000%

Path25

Path Summary:

Slack	0.385
Data Arrival Time	1.764
Data Required Time	1.379
From	rx_mac_rst_n_s0
To	u_mac_rx_model_word/rx_frm_cnt_0_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R22C152[0][B]	rx_mac_rst_n_s0/CLK
1.594	0.144	tC2Q	RR	826	R22C152[0][B]	rx_mac_rst_n_s0/Q
1.764	0.170	tNET	RR	1	R14C150[0][B]	u_mac_rx_model_word/rx_frm_cnt_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	2010	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.432	1.432	tNET	RR	1	R14C150[0][B]	u_mac_rx_model_word/rx_frm_cnt_0_s1/CLK
1.379	-0.053	tHld		1	R14C150[0][B]	u_mac_rx_model_word/rx_frm_cnt_0_s1

Path Statistics:

Clock Skew	-0.018
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.170, 54.140%; tC2Q: 0.144, 45.860%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.432, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	0.791
Actual Width:	1.041
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/gmii_rxd_int_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/gmii_rxd_int_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			rx_mac_clk
3.200	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
4.977	1.777	tNET	FF	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/gmii_rxd_int_12_s0/CLK

MPW2

MPW Summary:

Slack:	0.791
Actual Width:	1.041
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/flow_ctrl_dest_addr_reg_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/flow_ctrl_dest_addr_reg_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			rx_mac_clk
3.200	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
4.977	1.777	tNET	FF	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/flow_ctrl_dest_addr_reg_s0/CLK

MPW3

MPW Summary:

Slack:	0.791
Actual Width:	1.041
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/flow_ctrl_op_reg_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/flow_ctrl_op_reg_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			rx_mac_clk
3.200	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
4.977	1.777	tNET	FF	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/flow_ctrl_op_reg_s0/CLK

MPW4

MPW Summary:

Slack:	0.791
Actual Width:	1.041
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/gmii_rxd_int_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/gmii_rxd_int_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			rx_mac_clk
3.200	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
4.977	1.777	tNET	FF	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/gmii_rxd_int_9_s0/CLK

MPW5

MPW Summary:

Slack:	0.791
Actual Width:	1.041
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rxd_preamble_m_set_h_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rxd_preamble_m_set_h_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			rx_mac_clk
3.200	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
4.977	1.777	tNET	FF	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rxd_preamble_m_set_h_s0/CLK

MPW6

MPW Summary:

Slack:	0.791
Actual Width:	1.041
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_46_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_46_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			rx_mac_clk
3.200	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
4.977	1.777	tNET	FF	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_46_s1/CLK

MPW7

MPW Summary:

Slack:	0.791
Actual Width:	1.041
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_45_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_45_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			rx_mac_clk
3.200	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
4.977	1.777	tNET	FF	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_45_s1/CLK

MPW8

MPW Summary:

Slack:	0.791
Actual Width:	1.041
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_44_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_44_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			rx_mac_clk
3.200	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
4.977	1.777	tNET	FF	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_44_s1/CLK

MPW9

MPW Summary:

Slack:	0.791
Actual Width:	1.041
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_43_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_43_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			rx_mac_clk
3.200	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
4.977	1.777	tNET	FF	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_43_s1/CLK

MPW10

MPW Summary:

Slack:	0.791
Actual Width:	1.041
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_23_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_23_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			rx_mac_clk
3.200	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
4.977	1.777	tNET	FF	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_23_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
2010	rx_mac_clk	0.005	3.939
2005	clk_uart	85.249	3.936
1310	tx_mac_clk	0.353	3.711
956	rstn_uart	94.234	3.786
196	u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_ptr[2]	95.638	2.561
192	u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd_ptr[2]	95.365	2.339
162	u_mac_rx_model_word/rx_pause_state	0.331	5.098
159	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/crc_result_valid	2.390	1.726
148	u_mac_rx_model_word/rx_mac_valid_d3	1.437	3.400
148	u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n1465_4	0.994	3.373

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C4	100.00%
R2C5	100.00%
R2C66	100.00%
R2C68	100.00%
R2C69	100.00%
R3C17	100.00%
R4C93	100.00%
R7C65	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name rx_mac_clk -period 6.4 -waveform {0 3.2} [get_pins {u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK}]
TC_CLOCK	Actived	create_clock -name tx_mac_clk -period 6.4 -waveform {0 3.2} [get_pins {u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK}]
TC_CLOCK	Actived	create_clock -name clk_in -period 19.048 -waveform {0 10} [get_pins {u_osc/OSCOUT}]
TC_CLOCK	Actived	create_clock -name board_clk -period 20 -waveform {0 10} [get_pins {board_clk_ibuf/I}]
TC_GENERATED_CLOCK	Actived	create_generated_clock -name clk_uart -source [get_pins {board_clk_ibuf/I}] -master_clock board_clk -divide_by 65 -multiply_by 13 [get_pins {u_pll_uart/u_pll/PLL_inst/CLKOUT0}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_in clk_uart}] -to [get_clocks {tx_mac_clk rx_mac_clk}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {tx_mac_clk rx_mac_clk}] -to [get_clocks {clk_uart}]