srcfile:=	../../project/src/serdes/srio/srio.vo \
            ../../project/src/test/gowin_sdpram.v \
            ../../project/src/test/gowin_srio_maints.v \
            ../../project/src/test/gowin_srio_request_gen.v \
            ../../project/src/test/gowin_srio_response_gen.v \
            ../../project/src/fifo_sc_top/fifo_sc_top.vo


tbfile:=	../../tb/tc_srio_mod.v \
            			

vcs:
	vcs -debug_all -R -full64 -fsdb -sverilog \
	-v ../../tb/simlib/gw5a/prim_sim.v \
	$(tbfile) \
	$(srcfile) 

verdi:
	verdi -sverilog	-nologo \
	-v ../../tb/simlib/gw5a/prim_sim.v \
	$(tbfile) \
	$(srcfile) \
	-ssf tb.fsdb \
	&

clean:
	rm -rf compile  *.err *.log csrc  run.do  simv  simv.daidir  ucli.key  vc_hdrs.h  work novas.rc  nWaveLog   vcd2fsdbLog  verilog.vcd  verilog.vcd.fsdb vsim.wlf simv.vdb INCA_libs waves.shm .simvision *.rc cov_work daTaseT.asdb  fcover.acdb  library.cfg elab_file *.ucdb verdiLog inTer.vpd novas.conf wave.ses.png *.fsdb daTa

