Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\UARTTOBUS\data\uart_bus_core_encryption.v C:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\UARTTOBUS\data\uart_to_bus_top.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-3 |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Thu Aug 03 14:20:04 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Uart_to_Bus_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.448s, Peak memory usage = 51.148MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 51.148MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 51.148MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 51.148MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 51.148MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 51.148MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 51.148MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 51.148MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 51.148MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.126s, Peak memory usage = 51.148MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 51.148MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 51.148MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 64.117MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.122s, Peak memory usage = 64.117MB Generate output files: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.159s, Peak memory usage = 64.117MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 64.117MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 218 |
| I/O Buf | 218 |
| IBUF | 69 |
| OBUF | 149 |
| Register | 1831 |
| DFFRE | 1104 |
| DFFPE | 9 |
| DFFCE | 718 |
| LUT | 1157 |
| LUT2 | 187 |
| LUT3 | 720 |
| LUT4 | 250 |
| ALU | 32 |
| ALU | 32 |
| INV | 10 |
| INV | 10 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1199(1167 LUTs, 32 ALUs) / 138240 | <1% |
| Register | 1831 / 139140 | 2% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 1831 / 139140 | 2% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_i_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_i | 100.0(MHz) | 183.6(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.554 |
| Data Arrival Time | 6.273 |
| Data Required Time | 10.828 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_21_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1831 | clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_21_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_21_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s9/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s9/F |
| 2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s4/I0 |
| 2.227 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s4/O |
| 2.464 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s1/I1 |
| 2.566 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s1/O |
| 2.803 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s0/I0 |
| 2.906 | 0.103 | tINS | FF | 8 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s0/O |
| 3.143 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s54/I1 |
| 3.698 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s54/F |
| 3.935 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s43/I1 |
| 4.490 | 0.555 | tINS | FF | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s43/F |
| 4.727 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s40/I1 |
| 5.282 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s40/F |
| 5.519 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s39/I0 |
| 6.036 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s39/F |
| 6.273 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1831 | clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.046, 56.292%; route: 2.133, 39.420%; tC2Q: 0.232, 4.288% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 4.592 |
| Data Arrival Time | 6.235 |
| Data Required Time | 10.828 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_21_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1831 | clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_21_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_21_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s9/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s9/F |
| 2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s4/I0 |
| 2.227 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s4/O |
| 2.464 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s1/I1 |
| 2.566 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s1/O |
| 2.803 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s0/I0 |
| 2.906 | 0.103 | tINS | FF | 8 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n322_s0/O |
| 3.143 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s47/I1 |
| 3.698 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s47/F |
| 3.935 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s44/I0 |
| 4.452 | 0.517 | tINS | FF | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s44/F |
| 4.689 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s40/I1 |
| 5.244 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s40/F |
| 5.481 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/I0 |
| 5.998 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/F |
| 6.235 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1831 | clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.008, 55.984%; route: 2.133, 39.698%; tC2Q: 0.232, 4.318% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 4.630 |
| Data Arrival Time | 6.198 |
| Data Required Time | 10.828 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_20_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1831 | clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_20_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_20_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s9/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s9/F |
| 2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s4/I0 |
| 2.227 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s4/O |
| 2.464 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s1/I1 |
| 2.566 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s1/O |
| 2.803 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s0/I0 |
| 2.906 | 0.103 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s0/O |
| 3.143 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/I1 |
| 3.698 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/F |
| 3.935 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s45/I0 |
| 4.452 | 0.517 | tINS | FF | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s45/F |
| 4.689 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s41/I0 |
| 5.207 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s41/F |
| 5.444 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s40/I0 |
| 5.961 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s40/F |
| 6.198 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1831 | clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.970, 55.670%; route: 2.133, 39.981%; tC2Q: 0.232, 4.349% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 4.630 |
| Data Arrival Time | 6.198 |
| Data Required Time | 10.828 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_20_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1831 | clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_20_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_20_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s9/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s9/F |
| 2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s4/I0 |
| 2.227 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s4/O |
| 2.464 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s1/I1 |
| 2.566 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s1/O |
| 2.803 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s0/I0 |
| 2.906 | 0.103 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n321_s0/O |
| 3.143 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s46/I1 |
| 3.698 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s46/F |
| 3.935 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s44/I0 |
| 4.452 | 0.517 | tINS | FF | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s44/F |
| 4.689 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s48/I0 |
| 5.207 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s48/F |
| 5.444 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s39/I0 |
| 5.961 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s39/F |
| 6.198 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1831 | clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.970, 55.670%; route: 2.133, 39.981%; tC2Q: 0.232, 4.349% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 4.694 |
| Data Arrival Time | 6.134 |
| Data Required Time | 10.828 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_23_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1831 | clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_23_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_23_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n324_s9/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n324_s9/F |
| 2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n324_s4/I0 |
| 2.227 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n324_s4/O |
| 2.464 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n324_s1/I1 |
| 2.566 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n324_s1/O |
| 2.803 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n324_s0/I0 |
| 2.906 | 0.103 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n324_s0/O |
| 3.143 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s53/I2 |
| 3.596 | 0.453 | tINS | FF | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s53/F |
| 3.833 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s48/I0 |
| 4.351 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s48/F |
| 4.588 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s41/I1 |
| 5.142 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s41/F |
| 5.379 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s40/I0 |
| 5.897 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s40/F |
| 6.134 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1831 | clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.906, 55.132%; route: 2.133, 40.467%; tC2Q: 0.232, 4.401% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |