Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\SERDES_IP\IPlib\SRIO\data\srio_top.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\SERDES_IP\IPlib\SRIO\data\srio_core_encryption.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Dec 30 15:42:32 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | SRIO_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 181.328MB Running netlist conversion: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.227s, Peak memory usage = 181.328MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 181.328MB Optimizing Phase 1: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.753s, Peak memory usage = 181.328MB Optimizing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 181.328MB Running inference: Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 181.328MB Inferring Phase 1: CPU time = 0h 0m 0.984s, Elapsed time = 0h 0m 0.984s, Peak memory usage = 181.328MB Inferring Phase 2: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.136s, Peak memory usage = 181.328MB Inferring Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 181.328MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 181.328MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.367s, Peak memory usage = 181.328MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.596s, Peak memory usage = 181.328MB Tech-Mapping Phase 3: CPU time = 0h 0m 21s, Elapsed time = 0h 0m 21s, Peak memory usage = 188.695MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.89s, Elapsed time = 0h 0m 0.958s, Peak memory usage = 188.695MB Generate output files: CPU time = 0h 0m 0.828s, Elapsed time = 0h 0m 0.83s, Peak memory usage = 226.801MB |
| Total Time and Memory Usage | CPU time = 0h 0m 31s, Elapsed time = 0h 0m 31s, Peak memory usage = 226.801MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 955 |
| I/O Buf | 853 |
| IBUF | 357 |
| OBUF | 496 |
| Register | 7453 |
| DFFSE | 359 |
| DFFRE | 7088 |
| DFFPE | 6 |
| LUT | 6622 |
| LUT2 | 1019 |
| LUT3 | 1784 |
| LUT4 | 3819 |
| ALU | 649 |
| ALU | 649 |
| INV | 114 |
| INV | 114 |
| BSRAM | 24 |
| SDPB | 16 |
| SDPX9B | 8 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 7385(6736 LUT, 649 ALU) / 138240 | 6% |
| Register | 7453 / 139140 | 6% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 7453 / 139140 | 6% |
| BSRAM | 24 / 340 | 8% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | srio_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | srio_clk_i_ibuf/I | ||
| 2 | user_pcs_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | user_pcs_clk_i_ibuf/I | ||
| 3 | cfg_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | cfg_clk_i_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | srio_clk_i | 100.000(MHz) | 102.080(MHz) | 11 | TOP |
| 2 | user_pcs_clk_i | 100.000(MHz) | 178.532(MHz) | 6 | TOP |
| 3 | cfg_clk_i | 100.000(MHz) | 159.141(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 0.204 |
| Data Arrival Time | 10.145 |
| Data Required Time | 10.349 |
| From | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1 |
| To | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1 |
| Launch Clk | srio_clk_i[R] |
| Latch Clk | srio_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | srio_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | srio_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 5056 | srio_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 5 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0 |
| 1.786 | 0.579 | tINS | RR | 27 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/I1 |
| 2.766 | 0.567 | tINS | RR | 5 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/F |
| 3.179 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I2 |
| 3.686 | 0.507 | tINS | RR | 2 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F |
| 4.099 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3 |
| 4.388 | 0.289 | tINS | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F |
| 4.800 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0 |
| 5.379 | 0.579 | tINS | RR | 10 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F |
| 5.791 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s9/I1 |
| 6.359 | 0.567 | tINS | RR | 2 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s9/F |
| 6.771 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s23/I3 |
| 7.060 | 0.289 | tINS | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s23/F |
| 7.473 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s21/I1 |
| 8.040 | 0.567 | tINS | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s21/F |
| 8.453 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s20/I0 |
| 9.031 | 0.579 | tINS | RR | 2 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s20/F |
| 9.444 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n728_s1/I3 |
| 9.733 | 0.289 | tINS | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n728_s1/F |
| 10.145 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | srio_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | srio_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 5056 | srio_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1/CLK |
| 10.349 | -0.064 | tSu | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.812, 49.448%; route: 4.537, 46.622%; tC2Q: 0.382, 3.930% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 0.657 |
| Data Arrival Time | 9.444 |
| Data Required Time | 10.101 |
| From | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1 |
| To | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0 |
| Launch Clk | srio_clk_i[R] |
| Latch Clk | srio_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | srio_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | srio_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 5056 | srio_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 5 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0 |
| 1.786 | 0.579 | tINS | RR | 27 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/I1 |
| 2.766 | 0.567 | tINS | RR | 5 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/F |
| 3.179 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I2 |
| 3.686 | 0.507 | tINS | RR | 2 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F |
| 4.099 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3 |
| 4.388 | 0.289 | tINS | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F |
| 4.800 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0 |
| 5.379 | 0.579 | tINS | RR | 10 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F |
| 5.791 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s9/I1 |
| 6.359 | 0.567 | tINS | RR | 2 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s9/F |
| 6.771 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s7/I3 |
| 7.060 | 0.289 | tINS | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s7/F |
| 7.473 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s6/I0 |
| 8.051 | 0.579 | tINS | RR | 2 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s6/F |
| 8.464 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s5/I1 |
| 9.031 | 0.567 | tINS | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s5/F |
| 9.444 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | srio_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | srio_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 5056 | srio_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/CLK |
| 10.101 | -0.311 | tSu | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.524, 50.090%; route: 4.125, 45.675%; tC2Q: 0.382, 4.235% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 0.905 |
| Data Arrival Time | 9.444 |
| Data Required Time | 10.349 |
| From | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1 |
| To | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0 |
| Launch Clk | srio_clk_i[R] |
| Latch Clk | srio_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | srio_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | srio_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 5056 | srio_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 5 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0 |
| 1.786 | 0.579 | tINS | RR | 27 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/I1 |
| 2.766 | 0.567 | tINS | RR | 5 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/F |
| 3.179 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I2 |
| 3.686 | 0.507 | tINS | RR | 2 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F |
| 4.099 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3 |
| 4.388 | 0.289 | tINS | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F |
| 4.800 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0 |
| 5.379 | 0.579 | tINS | RR | 10 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F |
| 5.791 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s9/I1 |
| 6.359 | 0.567 | tINS | RR | 2 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s9/F |
| 6.771 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s23/I3 |
| 7.060 | 0.289 | tINS | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s23/F |
| 7.473 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s21/I1 |
| 8.040 | 0.567 | tINS | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s21/F |
| 8.453 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s20/I0 |
| 9.031 | 0.579 | tINS | RR | 2 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s20/F |
| 9.444 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | srio_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | srio_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 5056 | srio_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.524, 50.090%; route: 4.125, 45.675%; tC2Q: 0.382, 4.235% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 1.365 |
| Data Arrival Time | 8.984 |
| Data Required Time | 10.349 |
| From | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_control_sym_gen/u_embed_queue/dout_int_reg_12_s0 |
| To | u_srio_core/u_srio_phy_top/u_link_init/status_timer_3_s0 |
| Launch Clk | srio_clk_i[R] |
| Latch Clk | srio_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | srio_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | srio_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 5056 | srio_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_control_sym_gen/u_embed_queue/dout_int_reg_12_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 3 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_control_sym_gen/u_embed_queue/dout_int_reg_12_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_tx_assemble/n417_s14/I0 |
| 1.786 | 0.579 | tINS | RR | 2 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_tx_assemble/n417_s14/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_tx_assemble/o_status_timer_clc_s2/I2 |
| 2.706 | 0.507 | tINS | RR | 1 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_tx_assemble/o_status_timer_clc_s2/F |
| 3.119 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_tx_assemble/o_status_timer_clc_s1/I0 |
| 3.698 | 0.579 | tINS | RR | 1 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_tx_assemble/o_status_timer_clc_s1/F |
| 4.110 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n123_s7/I0 |
| 4.689 | 0.579 | tINS | RR | 4 | u_srio_core/u_srio_phy_top/u_link_init/n123_s7/F |
| 5.101 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n169_s5/I1 |
| 5.669 | 0.567 | tINS | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n169_s5/F |
| 6.081 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n169_s3/I2 |
| 6.589 | 0.507 | tINS | RR | 2 | u_srio_core/u_srio_phy_top/u_link_init/n169_s3/F |
| 7.001 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n123_s5/I0 |
| 7.580 | 0.579 | tINS | RR | 5 | u_srio_core/u_srio_phy_top/u_link_init/n123_s5/F |
| 7.993 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n126_s4/I0 |
| 8.571 | 0.579 | tINS | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n126_s4/F |
| 8.984 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/status_timer_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | srio_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | srio_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 5056 | srio_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/status_timer_3_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | u_srio_core/u_srio_phy_top/u_link_init/status_timer_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.476, 52.224%; route: 3.712, 43.313%; tC2Q: 0.382, 4.463% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 1.365 |
| Data Arrival Time | 8.984 |
| Data Required Time | 10.349 |
| From | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_control_sym_gen/u_embed_queue/dout_int_reg_12_s0 |
| To | u_srio_core/u_srio_phy_top/u_link_init/status_timer_4_s0 |
| Launch Clk | srio_clk_i[R] |
| Latch Clk | srio_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | srio_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | srio_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 5056 | srio_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_control_sym_gen/u_embed_queue/dout_int_reg_12_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 3 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_control_sym_gen/u_embed_queue/dout_int_reg_12_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_tx_assemble/n417_s14/I0 |
| 1.786 | 0.579 | tINS | RR | 2 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_tx_assemble/n417_s14/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_tx_assemble/o_status_timer_clc_s2/I2 |
| 2.706 | 0.507 | tINS | RR | 1 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_tx_assemble/o_status_timer_clc_s2/F |
| 3.119 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_tx_assemble/o_status_timer_clc_s1/I0 |
| 3.698 | 0.579 | tINS | RR | 1 | u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_tx_assemble/o_status_timer_clc_s1/F |
| 4.110 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n123_s7/I0 |
| 4.689 | 0.579 | tINS | RR | 4 | u_srio_core/u_srio_phy_top/u_link_init/n123_s7/F |
| 5.101 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n169_s5/I1 |
| 5.669 | 0.567 | tINS | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n169_s5/F |
| 6.081 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n169_s3/I2 |
| 6.589 | 0.507 | tINS | RR | 2 | u_srio_core/u_srio_phy_top/u_link_init/n169_s3/F |
| 7.001 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n123_s5/I0 |
| 7.580 | 0.579 | tINS | RR | 5 | u_srio_core/u_srio_phy_top/u_link_init/n123_s5/F |
| 7.993 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n125_s4/I0 |
| 8.571 | 0.579 | tINS | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/n125_s4/F |
| 8.984 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/status_timer_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | srio_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | srio_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 5056 | srio_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_srio_core/u_srio_phy_top/u_link_init/status_timer_4_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | u_srio_core/u_srio_phy_top/u_link_init/status_timer_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.476, 52.224%; route: 3.712, 43.313%; tC2Q: 0.382, 4.463% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |