Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\gowin_prj\test_5at_srio_ed\gowin_srio\ref_design\Gowin_Serial_RapidIO_RefDesign\project\src\fifo_sc_top\temp\FIFO_SC\fifo_sc_define.v E:\gowin_prj\test_5at_srio_ed\gowin_srio\ref_design\Gowin_Serial_RapidIO_RefDesign\project\src\fifo_sc_top\temp\FIFO_SC\fifo_sc_parameter.v C:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO_SC\data\edc_sc.v C:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO_SC\data\fifo_sc.v C:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO_SC\data\fifo_sc_top.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-3 |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Mon Jul 24 09:52:36 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | fifo_sc_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.471s, Peak memory usage = 45.078MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 45.078MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 45.078MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 45.078MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 45.078MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 45.078MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 45.078MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 45.078MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 45.078MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 45.078MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 45.078MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 45.078MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.304s, Peak memory usage = 50.203MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 50.203MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 50.203MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.779s, Elapsed time = 0h 0m 0.831s, Peak memory usage = 50.203MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 200 |
| I/O Buf | 200 |
| IBUF | 100 |
| OBUF | 100 |
| Register | 24 |
| DFFPE | 2 |
| DFFCE | 22 |
| LUT | 50 |
| LUT2 | 10 |
| LUT3 | 12 |
| LUT4 | 28 |
| ALU | 19 |
| ALU | 19 |
| BSRAM | 3 |
| SDPB | 3 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 69(50 LUTs, 19 ALUs) / 138240 | <1% |
| Register | 24 / 139140 | <1% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 24 / 139140 | <1% |
| BSRAM | 3 / 340 | <1% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| Clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | Clk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | Clk | 100.0(MHz) | 159.8(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.744 |
| Data Arrival Time | 7.083 |
| Data Required Time | 10.828 |
| From | fifo_sc_inst/rbin_3_s0 |
| To | fifo_sc_inst/Almost_Empty_s0 |
| Launch Clk | Clk[R] |
| Latch Clk | Clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 30 | Clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | fifo_sc_inst/rbin_3_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 7 | fifo_sc_inst/rbin_3_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | fifo_sc_inst/rbin_next_7_s4/I1 |
| 1.887 | 0.555 | tINS | FF | 6 | fifo_sc_inst/rbin_next_7_s4/F |
| 2.124 | 0.237 | tNET | FF | 1 | fifo_sc_inst/rbin_next_6_s4/I1 |
| 2.679 | 0.555 | tINS | FF | 1 | fifo_sc_inst/rbin_next_6_s4/F |
| 2.916 | 0.237 | tNET | FF | 1 | fifo_sc_inst/n462_s6/I0 |
| 3.433 | 0.517 | tINS | FF | 3 | fifo_sc_inst/n462_s6/F |
| 3.670 | 0.237 | tNET | FF | 1 | fifo_sc_inst/n462_s5/I0 |
| 4.187 | 0.517 | tINS | FF | 1 | fifo_sc_inst/n462_s5/F |
| 4.424 | 0.237 | tNET | FF | 1 | fifo_sc_inst/wcnt_sub_9_s/I0 |
| 4.941 | 0.517 | tINS | FF | 1 | fifo_sc_inst/wcnt_sub_9_s/SUM |
| 5.178 | 0.237 | tNET | FF | 1 | fifo_sc_inst/awfull_val_s32/I3 |
| 5.549 | 0.371 | tINS | FF | 1 | fifo_sc_inst/awfull_val_s32/F |
| 5.786 | 0.237 | tNET | FF | 1 | fifo_sc_inst/awfull_val_s31/I3 |
| 6.156 | 0.371 | tINS | FF | 2 | fifo_sc_inst/awfull_val_s31/F |
| 6.393 | 0.237 | tNET | FF | 1 | fifo_sc_inst/arempty_val_s29/I2 |
| 6.846 | 0.453 | tINS | FF | 1 | fifo_sc_inst/arempty_val_s29/F |
| 7.083 | 0.237 | tNET | FF | 1 | fifo_sc_inst/Almost_Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | Clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 30 | Clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | fifo_sc_inst/Almost_Empty_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | fifo_sc_inst/Almost_Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.856, 61.984%; route: 2.133, 34.287%; tC2Q: 0.232, 3.729% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 3.826 |
| Data Arrival Time | 7.001 |
| Data Required Time | 10.828 |
| From | fifo_sc_inst/rbin_3_s0 |
| To | fifo_sc_inst/Almost_Full_s0 |
| Launch Clk | Clk[R] |
| Latch Clk | Clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 30 | Clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | fifo_sc_inst/rbin_3_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 7 | fifo_sc_inst/rbin_3_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | fifo_sc_inst/rbin_next_7_s4/I1 |
| 1.887 | 0.555 | tINS | FF | 6 | fifo_sc_inst/rbin_next_7_s4/F |
| 2.124 | 0.237 | tNET | FF | 1 | fifo_sc_inst/rbin_next_6_s4/I1 |
| 2.679 | 0.555 | tINS | FF | 1 | fifo_sc_inst/rbin_next_6_s4/F |
| 2.916 | 0.237 | tNET | FF | 1 | fifo_sc_inst/n462_s6/I0 |
| 3.433 | 0.517 | tINS | FF | 3 | fifo_sc_inst/n462_s6/F |
| 3.670 | 0.237 | tNET | FF | 1 | fifo_sc_inst/n462_s5/I0 |
| 4.187 | 0.517 | tINS | FF | 1 | fifo_sc_inst/n462_s5/F |
| 4.424 | 0.237 | tNET | FF | 1 | fifo_sc_inst/wcnt_sub_9_s/I0 |
| 4.941 | 0.517 | tINS | FF | 1 | fifo_sc_inst/wcnt_sub_9_s/SUM |
| 5.178 | 0.237 | tNET | FF | 1 | fifo_sc_inst/awfull_val_s32/I3 |
| 5.549 | 0.371 | tINS | FF | 1 | fifo_sc_inst/awfull_val_s32/F |
| 5.786 | 0.237 | tNET | FF | 1 | fifo_sc_inst/awfull_val_s31/I3 |
| 6.156 | 0.371 | tINS | FF | 2 | fifo_sc_inst/awfull_val_s31/F |
| 6.393 | 0.237 | tNET | FF | 1 | fifo_sc_inst/awfull_val_s30/I3 |
| 6.764 | 0.371 | tINS | FF | 1 | fifo_sc_inst/awfull_val_s30/F |
| 7.001 | 0.237 | tNET | FF | 1 | fifo_sc_inst/Almost_Full_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | Clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 30 | Clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | fifo_sc_inst/Almost_Full_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | fifo_sc_inst/Almost_Full_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.774, 61.476%; route: 2.133, 34.745%; tC2Q: 0.232, 3.779% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 6.345 |
| Data Arrival Time | 4.483 |
| Data Required Time | 10.828 |
| From | fifo_sc_inst/Empty_s0 |
| To | fifo_sc_inst/Empty_s0 |
| Launch Clk | Clk[R] |
| Latch Clk | Clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 30 | Clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | fifo_sc_inst/Empty_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | fifo_sc_inst/Empty_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | fifo_sc_inst/rbin_next_2_s4/I0 |
| 1.849 | 0.517 | tINS | FF | 10 | fifo_sc_inst/rbin_next_2_s4/F |
| 2.086 | 0.237 | tNET | FF | 1 | fifo_sc_inst/rbin_next_2_s3/I1 |
| 2.641 | 0.555 | tINS | FF | 3 | fifo_sc_inst/rbin_next_2_s3/F |
| 2.878 | 0.237 | tNET | FF | 1 | fifo_sc_inst/n485_s0/I0 |
| 3.427 | 0.549 | tINS | FR | 1 | fifo_sc_inst/n485_s0/COUT |
| 3.427 | 0.000 | tNET | RR | 1 | fifo_sc_inst/n486_s0/CIN |
| 3.462 | 0.035 | tINS | RF | 1 | fifo_sc_inst/n486_s0/COUT |
| 3.462 | 0.000 | tNET | FF | 1 | fifo_sc_inst/n487_s0/CIN |
| 3.497 | 0.035 | tINS | FF | 1 | fifo_sc_inst/n487_s0/COUT |
| 3.497 | 0.000 | tNET | FF | 1 | fifo_sc_inst/n488_s0/CIN |
| 3.532 | 0.035 | tINS | FF | 1 | fifo_sc_inst/n488_s0/COUT |
| 3.532 | 0.000 | tNET | FF | 1 | fifo_sc_inst/n489_s0/CIN |
| 3.567 | 0.035 | tINS | FF | 1 | fifo_sc_inst/n489_s0/COUT |
| 3.567 | 0.000 | tNET | FF | 1 | fifo_sc_inst/n490_s0/CIN |
| 3.603 | 0.035 | tINS | FF | 1 | fifo_sc_inst/n490_s0/COUT |
| 3.603 | 0.000 | tNET | FF | 1 | fifo_sc_inst/n491_s0/CIN |
| 3.638 | 0.035 | tINS | FF | 1 | fifo_sc_inst/n491_s0/COUT |
| 3.875 | 0.237 | tNET | FF | 1 | fifo_sc_inst/rempty_val_s2/I3 |
| 4.246 | 0.371 | tINS | FF | 1 | fifo_sc_inst/rempty_val_s2/F |
| 4.483 | 0.237 | tNET | FF | 1 | fifo_sc_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | Clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 30 | Clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | fifo_sc_inst/Empty_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | fifo_sc_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.203, 60.859%; route: 1.185, 32.733%; tC2Q: 0.232, 6.408% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 6.366 |
| Data Arrival Time | 4.462 |
| Data Required Time | 10.828 |
| From | fifo_sc_inst/wbin_3_s0 |
| To | fifo_sc_inst/Full_s0 |
| Launch Clk | Clk[R] |
| Latch Clk | Clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 30 | Clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | fifo_sc_inst/wbin_3_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | fifo_sc_inst/wbin_3_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | fifo_sc_inst/wbin_next_6_s4/I1 |
| 1.887 | 0.555 | tINS | FF | 5 | fifo_sc_inst/wbin_next_6_s4/F |
| 2.124 | 0.237 | tNET | FF | 1 | fifo_sc_inst/wbin_next_8_s3/I1 |
| 2.679 | 0.555 | tINS | FF | 3 | fifo_sc_inst/wbin_next_8_s3/F |
| 2.916 | 0.237 | tNET | FF | 1 | fifo_sc_inst/wfull_val_s1/I1 |
| 3.471 | 0.555 | tINS | FF | 1 | fifo_sc_inst/wfull_val_s1/F |
| 3.708 | 0.237 | tNET | FF | 1 | fifo_sc_inst/wfull_val_s0/I0 |
| 4.225 | 0.517 | tINS | FF | 1 | fifo_sc_inst/wfull_val_s0/F |
| 4.462 | 0.237 | tNET | FF | 1 | fifo_sc_inst/Full_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | Clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 30 | Clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | fifo_sc_inst/Full_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | fifo_sc_inst/Full_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 6.366 |
| Data Arrival Time | 4.462 |
| Data Required Time | 10.828 |
| From | fifo_sc_inst/rbin_3_s0 |
| To | fifo_sc_inst/rbin_9_s0 |
| Launch Clk | Clk[R] |
| Latch Clk | Clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 30 | Clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | fifo_sc_inst/rbin_3_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 7 | fifo_sc_inst/rbin_3_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | fifo_sc_inst/rbin_next_7_s4/I1 |
| 1.887 | 0.555 | tINS | FF | 6 | fifo_sc_inst/rbin_next_7_s4/F |
| 2.124 | 0.237 | tNET | FF | 1 | fifo_sc_inst/rbin_next_6_s4/I1 |
| 2.679 | 0.555 | tINS | FF | 1 | fifo_sc_inst/rbin_next_6_s4/F |
| 2.916 | 0.237 | tNET | FF | 1 | fifo_sc_inst/n462_s6/I0 |
| 3.433 | 0.517 | tINS | FF | 3 | fifo_sc_inst/n462_s6/F |
| 3.670 | 0.237 | tNET | FF | 1 | fifo_sc_inst/rbin_next_9_s2/I1 |
| 4.225 | 0.555 | tINS | FF | 1 | fifo_sc_inst/rbin_next_9_s2/F |
| 4.462 | 0.237 | tNET | FF | 1 | fifo_sc_inst/rbin_9_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | Clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 30 | Clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | fifo_sc_inst/rbin_9_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | fifo_sc_inst/rbin_9_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |