Timing Messages

Report Title	Timing Analysis Report
Design File	F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\impl\gwsynthesis\srio_ed_prj.vg
Physical Constraints File	F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\srio_ed_prj.cst
Timing Constraint File	F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\srio_ed_prj.sdc
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW5AST-LV138FPG676AES
Device	GW5AST-138
Device Version	B
Created Time	Tue Dec 30 15:44:06 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C ES
Hold Delay Model	Fast 0.945V 85C ES
Numbers of Paths Analyzed	22231
Numbers of Endpoints Analyzed	35513
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	srio_clk	Base	12.800	78.125	0.000	6.400			srio_clk
2	cfg_clk	Base	100.000	10.000	0.000	50.000			clk_10m
3	pll_ref_clk	Base	20.000	50.000	0.000	10.000			sys_clk_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	srio_clk	78.125(MHz)	80.657(MHz)	8	TOP
2	cfg_clk	10.000(MHz)	83.498(MHz)	8	TOP

No timing paths to get frequency of pll_ref_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
srio_clk	Setup	0.000	0
srio_clk	Hold	0.000	0
cfg_clk	Setup	0.000	0
cfg_clk	Hold	0.000	0
pll_ref_clk	Setup	0.000	0
pll_ref_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.402	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q	u0_srio_request_gen/tdata_out_27_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	12.358
2	0.659	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q	u0_srio_request_gen/tdata_out_35_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	12.107
3	0.681	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q	u0_srio_request_gen/tdata_out_3_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	12.079
4	0.681	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q	u0_srio_request_gen/tdata_out_11_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	12.079
5	0.683	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q	u0_srio_request_gen/tdata_out_19_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	12.077
6	1.259	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q	u0_srio_request_gen/tdata_out_43_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	11.501
7	1.354	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q	u0_srio_request_gen/tdata_out_51_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	11.406
8	1.823	u0_srio_response_gen/state_1_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.088	11.001
9	1.905	u0_srio_response_gen/state_1_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.081	10.912
10	2.301	u0_srio_response_gen/state_1_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/CE	srio_clk:[R]	srio_clk:[R]	12.800	-0.081	10.269
11	2.466	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q	u0_srio_request_gen/tdata_out_18_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	10.294
12	2.466	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q	u0_srio_request_gen/tdata_out_26_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	10.294
13	2.468	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q	u0_srio_request_gen/tdata_out_34_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	10.292
14	2.470	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q	u0_srio_request_gen/tdata_out_2_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.014	10.281
15	2.478	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/o_phy_tx_ready_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/rd_ptr_0_s3/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.036	10.295
16	2.529	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/o_phy_tx_ready_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/rd_ptr_0_s3/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.016	10.222
17	2.676	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q	u0_srio_request_gen/tdata_out_58_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.005	10.066
18	2.677	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/o_phy_tx_ready_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/rd_ptr_0_s3/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.027	10.086
19	2.690	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_0_s0/CE	srio_clk:[R]	srio_clk:[R]	12.800	-0.038	9.837
20	2.691	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_30_s0/CE	srio_clk:[R]	srio_clk:[R]	12.800	-0.041	9.839
21	2.691	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_31_s0/CE	srio_clk:[R]	srio_clk:[R]	12.800	-0.041	9.839
22	2.700	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_29_s0/CE	srio_clk:[R]	srio_clk:[R]	12.800	-0.048	9.837
23	2.711	u0_srio_response_gen/state_1_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_0_s1/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.074	10.099
24	2.712	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/rx_port_data_8_s0/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.041	10.065
25	2.734	u0_srio_response_gen/state_1_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_3_s1/D	srio_clk:[R]	srio_clk:[R]	12.800	-0.074	10.076

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.140	u0_srio_response_gen/rx_req_din_10_s0/Q	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_0_s/DI[10]	srio_clk:[R]	srio_clk:[R]	0.000	-0.018	0.195
2	0.143	u0_srio_response_gen/rx_req_din_70_s0/Q	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/DI[6]	srio_clk:[R]	srio_clk:[R]	0.000	0.005	0.175
3	0.143	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_5_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[5]	srio_clk:[R]	srio_clk:[R]	0.000	0.005	0.175
4	0.143	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_5_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s/DI[5]	srio_clk:[R]	srio_clk:[R]	0.000	0.005	0.175
5	0.144	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_4_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[4]	srio_clk:[R]	srio_clk:[R]	0.000	-0.014	0.195
6	0.157	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/wr_ptr_9_s1/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_1_s/ADA[13]	srio_clk:[R]	srio_clk:[R]	0.000	-0.010	0.204
7	0.166	u0_srio_response_gen/fifo_wdata_3_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/DI[3]	srio_clk:[R]	srio_clk:[R]	0.000	0.000	0.203
8	0.193	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_56_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[4]	srio_clk:[R]	srio_clk:[R]	0.000	-0.005	0.235
9	0.193	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_51_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[3]	srio_clk:[R]	srio_clk:[R]	0.000	-0.005	0.235
10	0.193	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_5_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[5]	srio_clk:[R]	srio_clk:[R]	0.000	-0.005	0.235
11	0.193	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_0_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[0]	srio_clk:[R]	srio_clk:[R]	0.000	-0.005	0.235
12	0.193	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_1_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s/DI[1]	srio_clk:[R]	srio_clk:[R]	0.000	-0.005	0.235
13	0.193	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_51_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[6]	srio_clk:[R]	srio_clk:[R]	0.000	-0.005	0.235
14	0.193	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_41_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s/DI[5]	srio_clk:[R]	srio_clk:[R]	0.000	-0.005	0.235
15	0.193	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_39_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s/DI[3]	srio_clk:[R]	srio_clk:[R]	0.000	-0.005	0.235
16	0.197	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_13_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[13]	srio_clk:[R]	srio_clk:[R]	0.000	-0.001	0.235
17	0.197	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_12_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[12]	srio_clk:[R]	srio_clk:[R]	0.000	-0.001	0.235
18	0.197	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_31_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/gowin_add_SDPB_mem_data_mem_data_0_0_s/DI[15]	srio_clk:[R]	srio_clk:[R]	0.000	-0.001	0.235
19	0.197	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_11_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[11]	srio_clk:[R]	srio_clk:[R]	0.000	-0.001	0.235
20	0.197	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_10_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[10]	srio_clk:[R]	srio_clk:[R]	0.000	-0.001	0.235
21	0.197	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_15_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s/DI[15]	srio_clk:[R]	srio_clk:[R]	0.000	-0.001	0.235
22	0.197	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_14_s0/Q	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s/DI[14]	srio_clk:[R]	srio_clk:[R]	0.000	-0.001	0.235
23	0.201	u0_srio_response_gen/rx_req_din_83_s0/Q	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/DI[11]	srio_clk:[R]	srio_clk:[R]	0.000	0.001	0.237
24	0.202	u0_srio_response_gen/rx_req_din_82_s0/Q	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/DI[10]	srio_clk:[R]	srio_clk:[R]	0.000	0.001	0.238
25	0.205	u0_srio_response_gen/rx_req_din_71_s0/Q	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/DI[7]	srio_clk:[R]	srio_clk:[R]	0.000	0.005	0.237

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	7.156	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.017	5.313
2	7.157	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.012	5.308
3	7.157	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.012	5.308
4	7.174	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.029	5.307
5	7.174	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.029	5.307
6	7.174	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_7_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.029	5.307
7	7.175	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.026	5.304
8	7.175	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.026	5.304
9	7.175	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.026	5.304
10	7.175	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.026	5.304
11	7.175	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	5.301
12	7.175	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	5.301
13	7.175	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_3_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	5.301
14	7.175	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	5.301
15	7.175	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	5.301
16	7.175	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_8_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.024	5.301
17	7.175	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.021	5.298
18	7.175	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.021	5.298
19	7.175	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.021	5.298
20	7.193	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Full_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.038	5.297
21	7.193	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.038	5.297
22	7.193	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Empty_s0/PRESET	srio_clk:[R]	srio_clk:[R]	12.800	-0.036	5.295
23	7.193	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.036	5.295
24	7.263	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.127	5.316
25	7.263	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_3_s0/CLEAR	srio_clk:[R]	srio_clk:[R]	12.800	-0.124	5.313

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.289	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0/Q	u_Serdes_Top/gtr12_quad_inst0/LANE0_PCS_RX_RST	srio_clk:[R]	srio_clk:[R]	0.000	-0.032	1.121
2	1.616	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0/Q	u_Serdes_Top/gtr12_quad_inst0/LANE0_PCS_TX_RST	srio_clk:[R]	srio_clk:[R]	0.000	-0.032	1.438
3	1.703	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0/Q	u_Serdes_Top/gtr12_quad_inst0/LANE1_PCS_RX_RST	srio_clk:[R]	srio_clk:[R]	0.000	-0.035	1.564
4	1.785	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0/Q	u_Serdes_Top/gtr12_quad_inst0/LANE1_PCS_TX_RST	srio_clk:[R]	srio_clk:[R]	0.000	-0.035	1.738
5	2.210	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_2_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.015	2.142
6	2.210	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_3_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.019	2.138
7	2.210	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_6_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.019	2.138
8	2.210	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_15_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.019	2.138
9	2.210	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.019	2.138
10	2.210	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.019	2.138
11	2.214	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_10_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.009	2.152
12	2.214	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_12_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.009	2.152
13	2.214	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.005	2.156
14	2.214	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_g2b_ptr_3_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.005	2.156
15	2.214	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd1_ptr_3_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.005	2.156
16	2.214	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_0_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.009	2.152
17	2.214	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_gray_ptr_2_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.009	2.152
18	2.214	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_gray_ptr1_2_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.009	2.152
19	2.214	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr_gray_ptr_0_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.005	2.156
20	2.214	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr_gray_ptr_2_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.005	2.156
21	2.214	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_gray_ptr_0_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.005	2.156
22	2.217	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_8_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	-0.005	2.169
23	2.217	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_rw_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	-0.001	2.165
24	2.217	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_1_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	-0.001	2.165
25	2.217	cfg_rst_srl_2_s0/Q	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_2_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	-0.001	2.165

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.373	4.373	1.000	High Pulse Width	srio_clk	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s
2	3.373	4.373	1.000	High Pulse Width	srio_clk	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_3_s
3	3.373	4.373	1.000	High Pulse Width	srio_clk	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/mem_data_mem_data_0_0_s
4	3.373	4.373	1.000	High Pulse Width	srio_clk	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/mem_data_mem_data_0_0_s
5	3.373	4.373	1.000	High Pulse Width	srio_clk	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s
6	3.373	4.373	1.000	High Pulse Width	srio_clk	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_3_s
7	3.373	4.373	1.000	High Pulse Width	srio_clk	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s
8	3.373	4.373	1.000	High Pulse Width	srio_clk	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/gowin_add_SDPB_mem_data_mem_data_0_2_s
9	3.373	4.373	1.000	High Pulse Width	srio_clk	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/gowin_add_SDPB_mem_data_mem_data_0_1_s
10	3.373	4.373	1.000	High Pulse Width	srio_clk	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/gowin_add_SDPB_mem_mem_0_0_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.402
Data Arrival Time	16.089
Data Required Time	16.491
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To	u0_srio_request_gen/tdata_out_27_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.731	3.731	tNET	RR	1	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
4.114	0.382	tC2Q	RR	5	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.829	0.715	tNET	RR	1	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
5.408	0.579	tINS	RR	27	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
6.008	0.600	tNET	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
6.296	0.289	tINS	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
6.299	0.003	tNET	RR	1	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.866	0.567	tINS	RR	9	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
7.706	0.840	tNET	RR	1	R4C70[3][B]	u0_srio_request_gen/n32793_s0/I3
8.280	0.574	tINS	RR	73	R4C70[3][B]	u0_srio_request_gen/n32793_s0/F
12.201	3.921	tNET	RR	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/I3
12.519	0.319	tINS	RF	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/F
12.676	0.156	tNET	FF	1	R4C43[3][A]	u0_srio_request_gen/n33674_s2/I1
13.223	0.548	tINS	FR	8	R4C43[3][A]	u0_srio_request_gen/n33674_s2/F
15.522	2.299	tNET	RR	1	R4C73[2][B]	u0_srio_request_gen/n33706_s0/I3
16.089	0.567	tINS	RR	1	R4C73[2][B]	u0_srio_request_gen/n33706_s0/F
16.089	0.000	tNET	RR	1	R4C73[2][B]	u0_srio_request_gen/tdata_out_27_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.555	3.755	tNET	RR	1	R4C73[2][B]	u0_srio_request_gen/tdata_out_27_s0/CLK
16.491	-0.064	tSu		1	R4C73[2][B]	u0_srio_request_gen/tdata_out_27_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%
Arrival Data Path Delay	cell: 3.443, 27.856%; route: 8.533, 69.049%; tC2Q: 0.382, 3.095%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.755, 100.000%

Path2

Path Summary:

Slack	0.659
Data Arrival Time	15.838
Data Required Time	16.497
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To	u0_srio_request_gen/tdata_out_35_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.731	3.731	tNET	RR	1	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
4.114	0.382	tC2Q	RR	5	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.829	0.715	tNET	RR	1	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
5.408	0.579	tINS	RR	27	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
6.008	0.600	tNET	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
6.296	0.289	tINS	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
6.299	0.003	tNET	RR	1	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.866	0.567	tINS	RR	9	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
7.706	0.840	tNET	RR	1	R4C70[3][B]	u0_srio_request_gen/n32793_s0/I3
8.280	0.574	tINS	RR	73	R4C70[3][B]	u0_srio_request_gen/n32793_s0/F
12.201	3.921	tNET	RR	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/I3
12.519	0.319	tINS	RF	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/F
12.676	0.156	tNET	FF	1	R4C43[3][A]	u0_srio_request_gen/n33674_s2/I1
13.223	0.548	tINS	FR	8	R4C43[3][A]	u0_srio_request_gen/n33674_s2/F
15.519	2.296	tNET	RR	1	R4C73[3][A]	u0_srio_request_gen/n33698_s0/I3
15.838	0.319	tINS	RF	1	R4C73[3][A]	u0_srio_request_gen/n33698_s0/F
15.838	0.000	tNET	FF	1	R4C73[3][A]	u0_srio_request_gen/tdata_out_35_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.555	3.755	tNET	RR	1	R4C73[3][A]	u0_srio_request_gen/tdata_out_35_s0/CLK
16.497	-0.058	tSu		1	R4C73[3][A]	u0_srio_request_gen/tdata_out_35_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%
Arrival Data Path Delay	cell: 3.194, 26.380%; route: 8.531, 70.461%; tC2Q: 0.382, 3.159%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.755, 100.000%

Path3

Path Summary:

Slack	0.681
Data Arrival Time	15.811
Data Required Time	16.491
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To	u0_srio_request_gen/tdata_out_3_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.731	3.731	tNET	RR	1	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
4.114	0.382	tC2Q	RR	5	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.829	0.715	tNET	RR	1	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
5.408	0.579	tINS	RR	27	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
6.008	0.600	tNET	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
6.296	0.289	tINS	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
6.299	0.003	tNET	RR	1	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.866	0.567	tINS	RR	9	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
7.706	0.840	tNET	RR	1	R4C70[3][B]	u0_srio_request_gen/n32793_s0/I3
8.280	0.574	tINS	RR	73	R4C70[3][B]	u0_srio_request_gen/n32793_s0/F
12.201	3.921	tNET	RR	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/I3
12.519	0.319	tINS	RF	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/F
12.676	0.156	tNET	FF	1	R4C43[3][A]	u0_srio_request_gen/n33674_s2/I1
13.223	0.548	tINS	FR	8	R4C43[3][A]	u0_srio_request_gen/n33674_s2/F
15.522	2.299	tNET	RR	1	R4C73[1][A]	u0_srio_request_gen/n33730_s0/I3
15.811	0.289	tINS	RR	1	R4C73[1][A]	u0_srio_request_gen/n33730_s0/F
15.811	0.000	tNET	RR	1	R4C73[1][A]	u0_srio_request_gen/tdata_out_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.555	3.755	tNET	RR	1	R4C73[1][A]	u0_srio_request_gen/tdata_out_3_s0/CLK
16.491	-0.064	tSu		1	R4C73[1][A]	u0_srio_request_gen/tdata_out_3_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%
Arrival Data Path Delay	cell: 3.164, 26.191%; route: 8.533, 70.642%; tC2Q: 0.382, 3.167%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.755, 100.000%

Path4

Path Summary:

Slack	0.681
Data Arrival Time	15.811
Data Required Time	16.491
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To	u0_srio_request_gen/tdata_out_11_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.731	3.731	tNET	RR	1	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
4.114	0.382	tC2Q	RR	5	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.829	0.715	tNET	RR	1	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
5.408	0.579	tINS	RR	27	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
6.008	0.600	tNET	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
6.296	0.289	tINS	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
6.299	0.003	tNET	RR	1	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.866	0.567	tINS	RR	9	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
7.706	0.840	tNET	RR	1	R4C70[3][B]	u0_srio_request_gen/n32793_s0/I3
8.280	0.574	tINS	RR	73	R4C70[3][B]	u0_srio_request_gen/n32793_s0/F
12.201	3.921	tNET	RR	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/I3
12.519	0.319	tINS	RF	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/F
12.676	0.156	tNET	FF	1	R4C43[3][A]	u0_srio_request_gen/n33674_s2/I1
13.223	0.548	tINS	FR	8	R4C43[3][A]	u0_srio_request_gen/n33674_s2/F
15.522	2.299	tNET	RR	1	R4C73[1][B]	u0_srio_request_gen/n33722_s0/I3
15.811	0.289	tINS	RR	1	R4C73[1][B]	u0_srio_request_gen/n33722_s0/F
15.811	0.000	tNET	RR	1	R4C73[1][B]	u0_srio_request_gen/tdata_out_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.555	3.755	tNET	RR	1	R4C73[1][B]	u0_srio_request_gen/tdata_out_11_s0/CLK
16.491	-0.064	tSu		1	R4C73[1][B]	u0_srio_request_gen/tdata_out_11_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%
Arrival Data Path Delay	cell: 3.164, 26.191%; route: 8.533, 70.642%; tC2Q: 0.382, 3.167%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.755, 100.000%

Path5

Path Summary:

Slack	0.683
Data Arrival Time	15.808
Data Required Time	16.491
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To	u0_srio_request_gen/tdata_out_19_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.731	3.731	tNET	RR	1	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
4.114	0.382	tC2Q	RR	5	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.829	0.715	tNET	RR	1	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
5.408	0.579	tINS	RR	27	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
6.008	0.600	tNET	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
6.296	0.289	tINS	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
6.299	0.003	tNET	RR	1	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.866	0.567	tINS	RR	9	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
7.706	0.840	tNET	RR	1	R4C70[3][B]	u0_srio_request_gen/n32793_s0/I3
8.280	0.574	tINS	RR	73	R4C70[3][B]	u0_srio_request_gen/n32793_s0/F
12.201	3.921	tNET	RR	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/I3
12.519	0.319	tINS	RF	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/F
12.676	0.156	tNET	FF	1	R4C43[3][A]	u0_srio_request_gen/n33674_s2/I1
13.223	0.548	tINS	FR	8	R4C43[3][A]	u0_srio_request_gen/n33674_s2/F
15.519	2.296	tNET	RR	1	R4C73[2][A]	u0_srio_request_gen/n33714_s0/I3
15.808	0.289	tINS	RR	1	R4C73[2][A]	u0_srio_request_gen/n33714_s0/F
15.808	0.000	tNET	RR	1	R4C73[2][A]	u0_srio_request_gen/tdata_out_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.555	3.755	tNET	RR	1	R4C73[2][A]	u0_srio_request_gen/tdata_out_19_s0/CLK
16.491	-0.064	tSu		1	R4C73[2][A]	u0_srio_request_gen/tdata_out_19_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%
Arrival Data Path Delay	cell: 3.164, 26.197%; route: 8.531, 70.636%; tC2Q: 0.382, 3.167%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.755, 100.000%

Path6

Path Summary:

Slack	1.259
Data Arrival Time	15.232
Data Required Time	16.491
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To	u0_srio_request_gen/tdata_out_43_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.731	3.731	tNET	RR	1	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
4.114	0.382	tC2Q	RR	5	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.829	0.715	tNET	RR	1	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
5.408	0.579	tINS	RR	27	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
6.008	0.600	tNET	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
6.296	0.289	tINS	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
6.299	0.003	tNET	RR	1	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.866	0.567	tINS	RR	9	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
7.706	0.840	tNET	RR	1	R4C70[3][B]	u0_srio_request_gen/n32793_s0/I3
8.280	0.574	tINS	RR	73	R4C70[3][B]	u0_srio_request_gen/n32793_s0/F
12.201	3.921	tNET	RR	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/I3
12.519	0.319	tINS	RF	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/F
12.676	0.156	tNET	FF	1	R4C43[3][A]	u0_srio_request_gen/n33674_s2/I1
13.223	0.548	tINS	FR	8	R4C43[3][A]	u0_srio_request_gen/n33674_s2/F
14.943	1.720	tNET	RR	1	R4C65[2][B]	u0_srio_request_gen/n33690_s0/I3
15.232	0.289	tINS	RR	1	R4C65[2][B]	u0_srio_request_gen/n33690_s0/F
15.232	0.000	tNET	RR	1	R4C65[2][B]	u0_srio_request_gen/tdata_out_43_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.555	3.755	tNET	RR	1	R4C65[2][B]	u0_srio_request_gen/tdata_out_43_s0/CLK
16.491	-0.064	tSu		1	R4C65[2][B]	u0_srio_request_gen/tdata_out_43_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%
Arrival Data Path Delay	cell: 3.164, 27.509%; route: 7.954, 69.165%; tC2Q: 0.382, 3.326%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.755, 100.000%

Path7

Path Summary:

Slack	1.354
Data Arrival Time	15.137
Data Required Time	16.491
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To	u0_srio_request_gen/tdata_out_51_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.731	3.731	tNET	RR	1	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
4.114	0.382	tC2Q	RR	5	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.829	0.715	tNET	RR	1	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
5.408	0.579	tINS	RR	27	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
6.008	0.600	tNET	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
6.296	0.289	tINS	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
6.299	0.003	tNET	RR	1	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.866	0.567	tINS	RR	9	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
7.706	0.840	tNET	RR	1	R4C70[3][B]	u0_srio_request_gen/n32793_s0/I3
8.280	0.574	tINS	RR	73	R4C70[3][B]	u0_srio_request_gen/n32793_s0/F
12.201	3.921	tNET	RR	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/I3
12.519	0.319	tINS	RF	1	R4C42[3][B]	u0_srio_request_gen/n33674_s3/F
12.676	0.156	tNET	FF	1	R4C43[3][A]	u0_srio_request_gen/n33674_s2/I1
13.223	0.548	tINS	FR	8	R4C43[3][A]	u0_srio_request_gen/n33674_s2/F
14.558	1.335	tNET	RR	1	R4C65[2][A]	u0_srio_request_gen/n33682_s0/I3
15.137	0.579	tINS	RR	1	R4C65[2][A]	u0_srio_request_gen/n33682_s0/F
15.137	0.000	tNET	RR	1	R4C65[2][A]	u0_srio_request_gen/tdata_out_51_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.555	3.755	tNET	RR	1	R4C65[2][A]	u0_srio_request_gen/tdata_out_51_s0/CLK
16.491	-0.064	tSu		1	R4C65[2][A]	u0_srio_request_gen/tdata_out_51_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%
Arrival Data Path Delay	cell: 3.454, 30.281%; route: 7.569, 66.365%; tC2Q: 0.382, 3.354%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.755, 100.000%

Path8

Path Summary:

Slack	1.823
Data Arrival Time	14.651
Data Required Time	16.474
From	u0_srio_response_gen/state_1_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.650	3.650	tNET	RR	1	R39C29[1][B]	u0_srio_response_gen/state_1_s0/CLK
4.032	0.382	tC2Q	RR	10	R39C29[1][B]	u0_srio_response_gen/state_1_s0/Q
4.210	0.178	tNET	RR	1	R38C29[1][B]	u0_srio_response_gen/tx_resp_trac_valid_s/I0
4.789	0.579	tINS	RR	10	R38C29[1][B]	u0_srio_response_gen/tx_resp_trac_valid_s/F
9.019	4.230	tNET	RR	1	R7C64[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/I0
9.526	0.507	tINS	RR	13	R7C64[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/F
10.198	0.671	tNET	RR	1	R8C67[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I3
10.516	0.319	tINS	RF	2	R8C67[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F
10.678	0.161	tNET	FF	1	R8C66[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3
10.966	0.289	tINS	FR	1	R8C66[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F
10.969	0.003	tNET	RR	1	R8C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0
11.536	0.567	tINS	RR	10	R8C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F
12.106	0.570	tNET	RR	1	R8C63[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s22/I3
12.685	0.579	tINS	RR	1	R8C63[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s22/F
13.300	0.615	tNET	RR	1	R7C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s21/I0
13.589	0.289	tINS	RR	1	R7C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s21/F
13.591	0.003	tNET	RR	1	R7C66[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s20/I0
14.099	0.507	tINS	RR	2	R7C66[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s20/F
14.104	0.005	tNET	RR	1	R7C66[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n728_s1/I3
14.651	0.548	tINS	RR	1	R7C66[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n728_s1/F
14.651	0.000	tNET	RR	1	R7C66[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.538	3.738	tNET	RR	1	R7C66[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1/CLK
16.474	-0.064	tSu		1	R7C66[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1

Path Statistics:

Clock Skew	0.088
Setup Relationship	12.800
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.650, 100.000%
Arrival Data Path Delay	cell: 4.184, 38.030%; route: 6.435, 58.493%; tC2Q: 0.382, 3.477%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.738, 100.000%

Path9

Path Summary:

Slack	1.905
Data Arrival Time	14.562
Data Required Time	16.467
From	u0_srio_response_gen/state_1_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.650	3.650	tNET	RR	1	R39C29[1][B]	u0_srio_response_gen/state_1_s0/CLK
4.032	0.382	tC2Q	RR	10	R39C29[1][B]	u0_srio_response_gen/state_1_s0/Q
4.210	0.178	tNET	RR	1	R38C29[1][B]	u0_srio_response_gen/tx_resp_trac_valid_s/I0
4.789	0.579	tINS	RR	10	R38C29[1][B]	u0_srio_response_gen/tx_resp_trac_valid_s/F
9.019	4.230	tNET	RR	1	R7C64[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/I0
9.526	0.507	tINS	RR	13	R7C64[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/F
10.198	0.671	tNET	RR	1	R8C67[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I3
10.516	0.319	tINS	RF	2	R8C67[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F
10.678	0.161	tNET	FF	1	R8C66[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3
10.966	0.289	tINS	FR	1	R8C66[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F
10.969	0.003	tNET	RR	1	R8C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0
11.536	0.567	tINS	RR	10	R8C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F
12.106	0.570	tNET	RR	1	R8C63[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s22/I3
12.685	0.579	tINS	RR	1	R8C63[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s22/F
13.300	0.615	tNET	RR	1	R7C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s21/I0
13.589	0.289	tINS	RR	1	R7C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s21/F
13.591	0.003	tNET	RR	1	R7C66[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s20/I0
14.099	0.507	tINS	RR	2	R7C66[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s20/F
14.562	0.464	tNET	RR	1	R8C66[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.531	3.731	tNET	RR	1	R8C66[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/CLK
16.467	-0.064	tSu		1	R8C66[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0

Path Statistics:

Clock Skew	0.081
Setup Relationship	12.800
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.650, 100.000%
Arrival Data Path Delay	cell: 3.636, 33.322%; route: 6.894, 63.173%; tC2Q: 0.382, 3.505%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%

Path10

Path Summary:

Slack	2.301
Data Arrival Time	13.919
Data Required Time	16.220
From	u0_srio_response_gen/state_1_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.650	3.650	tNET	RR	1	R39C29[1][B]	u0_srio_response_gen/state_1_s0/CLK
4.032	0.382	tC2Q	RR	10	R39C29[1][B]	u0_srio_response_gen/state_1_s0/Q
4.210	0.178	tNET	RR	1	R38C29[1][B]	u0_srio_response_gen/tx_resp_trac_valid_s/I0
4.789	0.579	tINS	RR	10	R38C29[1][B]	u0_srio_response_gen/tx_resp_trac_valid_s/F
9.019	4.230	tNET	RR	1	R7C64[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/I0
9.526	0.507	tINS	RR	13	R7C64[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/F
10.198	0.671	tNET	RR	1	R8C67[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I3
10.516	0.319	tINS	RF	2	R8C67[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F
10.678	0.161	tNET	FF	1	R8C66[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3
10.966	0.289	tINS	FR	1	R8C66[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F
10.969	0.003	tNET	RR	1	R8C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0
11.536	0.567	tINS	RR	10	R8C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F
11.546	0.010	tNET	RR	1	R8C66[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s9/I1
12.054	0.507	tINS	RR	2	R8C66[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s9/F
12.226	0.172	tNET	RR	1	R9C66[0][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s7/I3
12.515	0.289	tINS	RR	1	R9C66[0][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s7/F
12.517	0.003	tNET	RR	1	R9C66[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s6/I0
13.085	0.567	tINS	RR	2	R9C66[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s6/F
13.260	0.175	tNET	RR	1	R8C66[0][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s5/I1
13.767	0.507	tINS	RR	1	R8C66[0][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s5/F
13.919	0.151	tNET	RR	1	R8C66[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.531	3.731	tNET	RR	1	R8C66[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/CLK
16.220	-0.311	tSu		1	R8C66[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0

Path Statistics:

Clock Skew	0.081
Setup Relationship	12.800
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.650, 100.000%
Arrival Data Path Delay	cell: 4.133, 40.243%; route: 5.754, 56.032%; tC2Q: 0.382, 3.725%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%

Path11

Path Summary:

Slack	2.466
Data Arrival Time	14.026
Data Required Time	16.491
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To	u0_srio_request_gen/tdata_out_18_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.731	3.731	tNET	RR	1	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
4.114	0.382	tC2Q	RR	5	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.829	0.715	tNET	RR	1	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
5.408	0.579	tINS	RR	27	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
6.008	0.600	tNET	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
6.296	0.289	tINS	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
6.299	0.003	tNET	RR	1	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.866	0.567	tINS	RR	9	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
7.706	0.840	tNET	RR	1	R4C70[3][B]	u0_srio_request_gen/n32793_s0/I3
8.280	0.574	tINS	RR	73	R4C70[3][B]	u0_srio_request_gen/n32793_s0/F
11.711	3.431	tNET	RR	1	R4C55[2][B]	u0_srio_request_gen/n33675_s1/I2
12.289	0.579	tINS	RR	8	R4C55[2][B]	u0_srio_request_gen/n33675_s1/F
13.447	1.158	tNET	RR	1	R4C69[1][B]	u0_srio_request_gen/n33715_s1/I3
14.026	0.579	tINS	RR	1	R4C69[1][B]	u0_srio_request_gen/n33715_s1/F
14.026	0.000	tNET	RR	1	R4C69[1][B]	u0_srio_request_gen/tdata_out_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.555	3.755	tNET	RR	1	R4C69[1][B]	u0_srio_request_gen/tdata_out_18_s0/CLK
16.491	-0.064	tSu		1	R4C69[1][B]	u0_srio_request_gen/tdata_out_18_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%
Arrival Data Path Delay	cell: 3.166, 30.757%; route: 6.746, 65.527%; tC2Q: 0.382, 3.716%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.755, 100.000%

Path12

Path Summary:

Slack	2.466
Data Arrival Time	14.026
Data Required Time	16.491
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To	u0_srio_request_gen/tdata_out_26_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.731	3.731	tNET	RR	1	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
4.114	0.382	tC2Q	RR	5	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.829	0.715	tNET	RR	1	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
5.408	0.579	tINS	RR	27	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
6.008	0.600	tNET	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
6.296	0.289	tINS	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
6.299	0.003	tNET	RR	1	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.866	0.567	tINS	RR	9	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
7.706	0.840	tNET	RR	1	R4C70[3][B]	u0_srio_request_gen/n32793_s0/I3
8.280	0.574	tINS	RR	73	R4C70[3][B]	u0_srio_request_gen/n32793_s0/F
11.711	3.431	tNET	RR	1	R4C55[2][B]	u0_srio_request_gen/n33675_s1/I2
12.289	0.579	tINS	RR	8	R4C55[2][B]	u0_srio_request_gen/n33675_s1/F
13.447	1.158	tNET	RR	1	R4C69[1][A]	u0_srio_request_gen/n33707_s1/I3
14.026	0.579	tINS	RR	1	R4C69[1][A]	u0_srio_request_gen/n33707_s1/F
14.026	0.000	tNET	RR	1	R4C69[1][A]	u0_srio_request_gen/tdata_out_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.555	3.755	tNET	RR	1	R4C69[1][A]	u0_srio_request_gen/tdata_out_26_s0/CLK
16.491	-0.064	tSu		1	R4C69[1][A]	u0_srio_request_gen/tdata_out_26_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%
Arrival Data Path Delay	cell: 3.166, 30.757%; route: 6.746, 65.527%; tC2Q: 0.382, 3.716%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.755, 100.000%

Path13

Path Summary:

Slack	2.468
Data Arrival Time	14.023
Data Required Time	16.491
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To	u0_srio_request_gen/tdata_out_34_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.731	3.731	tNET	RR	1	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
4.114	0.382	tC2Q	RR	5	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.829	0.715	tNET	RR	1	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
5.408	0.579	tINS	RR	27	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
6.008	0.600	tNET	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
6.296	0.289	tINS	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
6.299	0.003	tNET	RR	1	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.866	0.567	tINS	RR	9	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
7.706	0.840	tNET	RR	1	R4C70[3][B]	u0_srio_request_gen/n32793_s0/I3
8.280	0.574	tINS	RR	73	R4C70[3][B]	u0_srio_request_gen/n32793_s0/F
11.711	3.431	tNET	RR	1	R4C55[2][B]	u0_srio_request_gen/n33675_s1/I2
12.289	0.579	tINS	RR	8	R4C55[2][B]	u0_srio_request_gen/n33675_s1/F
13.444	1.155	tNET	RR	1	R4C69[0][B]	u0_srio_request_gen/n33699_s1/I3
14.023	0.579	tINS	RR	1	R4C69[0][B]	u0_srio_request_gen/n33699_s1/F
14.023	0.000	tNET	RR	1	R4C69[0][B]	u0_srio_request_gen/tdata_out_34_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.555	3.755	tNET	RR	1	R4C69[0][B]	u0_srio_request_gen/tdata_out_34_s0/CLK
16.491	-0.064	tSu		1	R4C69[0][B]	u0_srio_request_gen/tdata_out_34_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%
Arrival Data Path Delay	cell: 3.166, 30.765%; route: 6.743, 65.519%; tC2Q: 0.382, 3.717%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.755, 100.000%

Path14

Path Summary:

Slack	2.470
Data Arrival Time	14.012
Data Required Time	16.482
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To	u0_srio_request_gen/tdata_out_2_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.731	3.731	tNET	RR	1	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
4.114	0.382	tC2Q	RR	5	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.829	0.715	tNET	RR	1	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
5.408	0.579	tINS	RR	27	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
6.008	0.600	tNET	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
6.296	0.289	tINS	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
6.299	0.003	tNET	RR	1	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.866	0.567	tINS	RR	9	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
7.706	0.840	tNET	RR	1	R4C70[3][B]	u0_srio_request_gen/n32793_s0/I3
8.280	0.574	tINS	RR	73	R4C70[3][B]	u0_srio_request_gen/n32793_s0/F
11.711	3.431	tNET	RR	1	R4C55[2][B]	u0_srio_request_gen/n33675_s1/I2
12.289	0.579	tINS	RR	8	R4C55[2][B]	u0_srio_request_gen/n33675_s1/F
13.444	1.155	tNET	RR	1	R4C68[0][A]	u0_srio_request_gen/n33731_s1/I3
14.012	0.567	tINS	RR	1	R4C68[0][A]	u0_srio_request_gen/n33731_s1/F
14.012	0.000	tNET	RR	1	R4C68[0][A]	u0_srio_request_gen/tdata_out_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.546	3.746	tNET	RR	1	R4C68[0][A]	u0_srio_request_gen/tdata_out_2_s0/CLK
16.482	-0.064	tSu		1	R4C68[0][A]	u0_srio_request_gen/tdata_out_2_s0

Path Statistics:

Clock Skew	0.014
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%
Arrival Data Path Delay	cell: 3.155, 30.689%; route: 6.743, 65.591%; tC2Q: 0.382, 3.721%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.746, 100.000%

Path15

Path Summary:

Slack	2.478
Data Arrival Time	13.984
Data Required Time	16.462
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/o_phy_tx_ready_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/rd_ptr_0_s3
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.689	3.689	tNET	RR	1	R13C55[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/o_phy_tx_ready_s0/CLK
4.072	0.382	tC2Q	RR	11	R13C55[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/o_phy_tx_ready_s0/Q
7.777	3.705	tNET	RR	1	R36C70[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/n2057_s0/I3
8.233	0.456	tINS	RR	29	R36C70[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/n2057_s0/F
9.942	1.709	tNET	RR	1	R42C63[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/ram_rd_en_i_s3/I2
10.509	0.567	tINS	RR	5	R42C63[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/ram_rd_en_i_s3/F
10.959	0.450	tNET	RR	1	R41C65[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/ram_rd_en_i_s2/I0
11.527	0.567	tINS	RR	5	R41C65[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/ram_rd_en_i_s2/F
11.911	0.384	tNET	RR	1	R38C65[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/rd_ptr_3_s4/I1
12.484	0.574	tINS	RR	8	R38C65[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/rd_ptr_3_s4/F
13.417	0.933	tNET	RR	1	R36C69[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/n44_s4/I3
13.984	0.567	tINS	RR	1	R36C69[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/n44_s4/F
13.984	0.000	tNET	RR	1	R36C69[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/rd_ptr_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.526	3.726	tNET	RR	1	R36C69[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/rd_ptr_0_s3/CLK
16.462	-0.064	tSu		1	R36C69[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/rd_ptr_0_s3

Path Statistics:

Clock Skew	0.036
Setup Relationship	12.800
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.689, 100.000%
Arrival Data Path Delay	cell: 2.733, 26.542%; route: 7.180, 69.743%; tC2Q: 0.382, 3.715%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.726, 100.000%

Path16

Path Summary:

Slack	2.529
Data Arrival Time	13.912
Data Required Time	16.441
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/o_phy_tx_ready_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/rd_ptr_0_s3
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.689	3.689	tNET	RR	1	R13C55[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/o_phy_tx_ready_s0/CLK
4.072	0.382	tC2Q	RR	11	R13C55[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/o_phy_tx_ready_s0/Q
7.777	3.705	tNET	RR	1	R36C70[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/n2057_s0/I3
8.233	0.456	tINS	RR	29	R36C70[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/n2057_s0/F
9.942	1.709	tNET	RR	1	R42C63[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/ram_rd_en_i_s3/I2
10.516	0.574	tINS	RR	5	R42C63[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/ram_rd_en_i_s3/F
11.374	0.859	tNET	RR	1	R41C66[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/ram_rd_en_i_s2/I0
11.922	0.548	tINS	RR	5	R41C66[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/ram_rd_en_i_s2/F
12.143	0.221	tNET	RR	1	R39C66[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/rd_ptr_3_s4/I1
12.717	0.574	tINS	RR	8	R39C66[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/rd_ptr_3_s4/F
13.333	0.616	tNET	RR	1	R35C67[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/n44_s4/I3
13.912	0.579	tINS	RR	1	R35C67[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/n44_s4/F
13.912	0.000	tNET	RR	1	R35C67[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/rd_ptr_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.505	3.705	tNET	RR	1	R35C67[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/rd_ptr_0_s3/CLK
16.441	-0.064	tSu		1	R35C67[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/rd_ptr_0_s3

Path Statistics:

Clock Skew	0.016
Setup Relationship	12.800
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.689, 100.000%
Arrival Data Path Delay	cell: 2.730, 26.706%; route: 7.110, 69.552%; tC2Q: 0.382, 3.742%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.705, 100.000%

Path17

Path Summary:

Slack	2.676
Data Arrival Time	13.797
Data Required Time	16.473
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To	u0_srio_request_gen/tdata_out_58_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.731	3.731	tNET	RR	1	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
4.114	0.382	tC2Q	RR	5	R6C71[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.829	0.715	tNET	RR	1	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
5.408	0.579	tINS	RR	27	R6C65[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
6.008	0.600	tNET	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
6.296	0.289	tINS	RR	1	R8C67[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
6.299	0.003	tNET	RR	1	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.866	0.567	tINS	RR	9	R8C67[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
7.706	0.840	tNET	RR	1	R4C70[3][B]	u0_srio_request_gen/n32793_s0/I3
8.280	0.574	tINS	RR	73	R4C70[3][B]	u0_srio_request_gen/n32793_s0/F
11.711	3.431	tNET	RR	1	R4C55[2][B]	u0_srio_request_gen/n33675_s1/I2
12.289	0.579	tINS	RR	8	R4C55[2][B]	u0_srio_request_gen/n33675_s1/F
13.223	0.934	tNET	RR	1	R4C67[3][A]	u0_srio_request_gen/n33675_s2/I3
13.797	0.574	tINS	RR	1	R4C67[3][A]	u0_srio_request_gen/n33675_s2/F
13.797	0.000	tNET	RR	1	R4C67[3][A]	u0_srio_request_gen/tdata_out_58_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.536	3.736	tNET	RR	1	R4C67[3][A]	u0_srio_request_gen/tdata_out_58_s0/CLK
16.473	-0.064	tSu		1	R4C67[3][A]	u0_srio_request_gen/tdata_out_58_s0

Path Statistics:

Clock Skew	0.005
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.731, 100.000%
Arrival Data Path Delay	cell: 3.161, 31.406%; route: 6.522, 64.794%; tC2Q: 0.382, 3.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.736, 100.000%

Path18

Path Summary:

Slack	2.677
Data Arrival Time	13.776
Data Required Time	16.453
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/o_phy_tx_ready_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/rd_ptr_0_s3
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.689	3.689	tNET	RR	1	R13C55[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/o_phy_tx_ready_s0/CLK
4.072	0.382	tC2Q	RR	11	R13C55[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/o_phy_tx_ready_s0/Q
7.777	3.705	tNET	RR	1	R36C70[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/n2057_s0/I3
8.233	0.456	tINS	RR	29	R36C70[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/n2057_s0/F
9.942	1.709	tNET	RR	1	R42C63[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/ram_rd_en_i_s3/I2
10.516	0.574	tINS	RR	5	R42C63[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/ram_rd_en_i_s3/F
10.902	0.386	tNET	RR	1	R41C62[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/ram_rd_en_i_s2/I0
11.221	0.319	tINS	RF	5	R41C62[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/ram_rd_en_i_s2/F
11.934	0.714	tNET	FF	1	R39C67[0][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/rd_ptr_3_s4/I1
12.502	0.567	tINS	FR	8	R39C67[0][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/rd_ptr_3_s4/F
13.319	0.817	tNET	RR	1	R36C68[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/n44_s4/I3
13.776	0.456	tINS	RR	1	R36C68[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/n44_s4/F
13.776	0.000	tNET	RR	1	R36C68[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/rd_ptr_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.516	3.716	tNET	RR	1	R36C68[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/rd_ptr_0_s3/CLK
16.453	-0.064	tSu		1	R36C68[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/rd_ptr_0_s3

Path Statistics:

Clock Skew	0.027
Setup Relationship	12.800
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.689, 100.000%
Arrival Data Path Delay	cell: 2.372, 23.522%; route: 7.331, 72.686%; tC2Q: 0.382, 3.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.716, 100.000%

Path19

Path Summary:

Slack	2.690
Data Arrival Time	13.539
Data Required Time	16.229
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_0_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.702	3.702	tNET	RR	1	R48C69[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/CLK
4.085	0.382	tC2Q	RR	4	R48C69[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/Q
6.322	2.238	tNET	RR	1	R60C42[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s7/I1
6.901	0.579	tINS	RR	1	R60C42[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s7/F
6.903	0.003	tNET	RR	1	R60C42[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s2/I3
7.482	0.579	tINS	RR	12	R60C42[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s2/F
8.423	0.941	tNET	RR	1	R61C35[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s3/I3
8.931	0.507	tINS	RR	5	R61C35[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s3/F
9.356	0.425	tNET	RR	1	R59C34[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s1/I2
9.863	0.507	tINS	RR	66	R59C34[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s1/F
13.539	3.676	tNET	RR	1	R60C56[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.541	3.741	tNET	RR	1	R60C56[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_0_s0/CLK
16.229	-0.311	tSu		1	R60C56[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_0_s0

Path Statistics:

Clock Skew	0.038
Setup Relationship	12.800
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.702, 100.000%
Arrival Data Path Delay	cell: 2.172, 22.085%; route: 7.282, 74.026%; tC2Q: 0.382, 3.888%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.741, 100.000%

Path20

Path Summary:

Slack	2.691
Data Arrival Time	13.541
Data Required Time	16.232
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_30_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.702	3.702	tNET	RR	1	R48C69[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/CLK
4.085	0.382	tC2Q	RR	4	R48C69[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/Q
6.322	2.238	tNET	RR	1	R60C42[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s7/I1
6.901	0.579	tINS	RR	1	R60C42[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s7/F
6.903	0.003	tNET	RR	1	R60C42[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s2/I3
7.482	0.579	tINS	RR	12	R60C42[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s2/F
8.423	0.941	tNET	RR	1	R61C35[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s3/I3
8.931	0.507	tINS	RR	5	R61C35[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s3/F
9.356	0.425	tNET	RR	1	R59C34[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s1/I2
9.863	0.507	tINS	RR	66	R59C34[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s1/F
13.541	3.678	tNET	RR	1	R59C58[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_30_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.543	3.743	tNET	RR	1	R59C58[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_30_s0/CLK
16.232	-0.311	tSu		1	R59C58[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_30_s0

Path Statistics:

Clock Skew	0.041
Setup Relationship	12.800
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.702, 100.000%
Arrival Data Path Delay	cell: 2.172, 22.081%; route: 7.284, 74.031%; tC2Q: 0.382, 3.888%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.743, 100.000%

Path21

Path Summary:

Slack	2.691
Data Arrival Time	13.541
Data Required Time	16.232
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_31_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.702	3.702	tNET	RR	1	R48C69[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/CLK
4.085	0.382	tC2Q	RR	4	R48C69[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/Q
6.322	2.238	tNET	RR	1	R60C42[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s7/I1
6.901	0.579	tINS	RR	1	R60C42[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s7/F
6.903	0.003	tNET	RR	1	R60C42[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s2/I3
7.482	0.579	tINS	RR	12	R60C42[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s2/F
8.423	0.941	tNET	RR	1	R61C35[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s3/I3
8.931	0.507	tINS	RR	5	R61C35[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s3/F
9.356	0.425	tNET	RR	1	R59C34[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s1/I2
9.863	0.507	tINS	RR	66	R59C34[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s1/F
13.541	3.678	tNET	RR	1	R59C58[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_31_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.543	3.743	tNET	RR	1	R59C58[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_31_s0/CLK
16.232	-0.311	tSu		1	R59C58[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_31_s0

Path Statistics:

Clock Skew	0.041
Setup Relationship	12.800
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.702, 100.000%
Arrival Data Path Delay	cell: 2.172, 22.081%; route: 7.284, 74.031%; tC2Q: 0.382, 3.888%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.743, 100.000%

Path22

Path Summary:

Slack	2.700
Data Arrival Time	13.539
Data Required Time	16.239
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_29_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.702	3.702	tNET	RR	1	R48C69[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/CLK
4.085	0.382	tC2Q	RR	4	R48C69[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/Q
6.322	2.238	tNET	RR	1	R60C42[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s7/I1
6.901	0.579	tINS	RR	1	R60C42[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s7/F
6.903	0.003	tNET	RR	1	R60C42[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s2/I3
7.482	0.579	tINS	RR	12	R60C42[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s2/F
8.423	0.941	tNET	RR	1	R61C35[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s3/I3
8.931	0.507	tINS	RR	5	R61C35[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s3/F
9.356	0.425	tNET	RR	1	R59C34[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s1/I2
9.863	0.507	tINS	RR	66	R59C34[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_en_s1/F
13.539	3.676	tNET	RR	1	R60C57[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_29_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.550	3.750	tNET	RR	1	R60C57[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_29_s0/CLK
16.239	-0.311	tSu		1	R60C57[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/stack_reg_29_s0

Path Statistics:

Clock Skew	0.048
Setup Relationship	12.800
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.702, 100.000%
Arrival Data Path Delay	cell: 2.172, 22.085%; route: 7.282, 74.026%; tC2Q: 0.382, 3.888%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.750, 100.000%

Path23

Path Summary:

Slack	2.711
Data Arrival Time	13.749
Data Required Time	16.460
From	u0_srio_response_gen/state_1_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_0_s1
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.650	3.650	tNET	RR	1	R39C29[1][B]	u0_srio_response_gen/state_1_s0/CLK
4.032	0.382	tC2Q	RR	10	R39C29[1][B]	u0_srio_response_gen/state_1_s0/Q
4.210	0.178	tNET	RR	1	R38C29[1][B]	u0_srio_response_gen/tx_resp_trac_valid_s/I0
4.789	0.579	tINS	RR	10	R38C29[1][B]	u0_srio_response_gen/tx_resp_trac_valid_s/F
9.019	4.230	tNET	RR	1	R7C64[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/I0
9.526	0.507	tINS	RR	13	R7C64[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/F
10.198	0.671	tNET	RR	1	R8C67[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I3
10.516	0.319	tINS	RF	2	R8C67[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F
10.678	0.161	tNET	FF	1	R8C66[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3
10.966	0.289	tINS	FR	1	R8C66[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F
10.969	0.003	tNET	RR	1	R8C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0
11.536	0.567	tINS	RR	10	R8C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F
12.378	0.841	tNET	RR	1	R9C62[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n494_s0/I3
12.666	0.289	tINS	RR	2	R9C62[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n494_s0/F
12.671	0.005	tNET	RR	1	R9C62[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n627_s1/I1
13.179	0.507	tINS	RR	1	R9C62[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n627_s1/F
13.181	0.003	tNET	RR	1	R9C62[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n627_s0/I2
13.749	0.567	tINS	RR	1	R9C62[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n627_s0/F
13.749	0.000	tNET	RR	1	R9C62[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.524	3.724	tNET	RR	1	R9C62[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_0_s1/CLK
16.460	-0.064	tSu		1	R9C62[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_0_s1

Path Statistics:

Clock Skew	0.074
Setup Relationship	12.800
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.650, 100.000%
Arrival Data Path Delay	cell: 3.625, 35.896%; route: 6.091, 60.317%; tC2Q: 0.382, 3.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.724, 100.000%

Path24

Path Summary:

Slack	2.712
Data Arrival Time	13.767
Data Required Time	16.479
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/rx_port_data_8_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.702	3.702	tNET	RR	1	R48C69[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/CLK
4.085	0.382	tC2Q	RR	4	R48C69[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/o_rx_maint_req_trac_ready_s0/Q
6.322	2.238	tNET	RR	1	R60C42[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s7/I1
6.901	0.579	tINS	RR	1	R60C42[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s7/F
6.903	0.003	tNET	RR	1	R60C42[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s2/I3
7.482	0.579	tINS	RR	12	R60C42[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n934_s2/F
8.423	0.941	tNET	RR	1	R61C35[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/next_rx_data_7_s2/I0
8.880	0.456	tINS	RR	8	R61C35[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/next_rx_data_7_s2/F
10.180	1.300	tNET	RR	1	R60C51[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/next_rx_data_5_s0/I2
10.636	0.456	tINS	RR	2	R60C51[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/next_rx_data_5_s0/F
11.493	0.858	tNET	RR	1	R60C43[0][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n2132_s9/I2
12.061	0.567	tINS	RR	1	R60C43[0][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n2132_s9/F
12.442	0.381	tNET	RR	1	R60C40[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n2132_s3/I3
13.016	0.574	tINS	RR	1	R60C40[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n2132_s3/F
13.188	0.172	tNET	RR	1	R59C40[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n2132_s0/I3
13.767	0.579	tINS	RR	1	R59C40[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n2132_s0/F
13.767	0.000	tNET	RR	1	R59C40[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/rx_port_data_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.543	3.743	tNET	RR	1	R59C40[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/rx_port_data_8_s0/CLK
16.479	-0.064	tSu		1	R59C40[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/rx_port_data_8_s0

Path Statistics:

Clock Skew	0.041
Setup Relationship	12.800
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.702, 100.000%
Arrival Data Path Delay	cell: 3.790, 37.655%; route: 5.893, 58.544%; tC2Q: 0.382, 3.800%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.743, 100.000%

Path25

Path Summary:

Slack	2.734
Data Arrival Time	13.726
Data Required Time	16.460
From	u0_srio_response_gen/state_1_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_3_s1
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.650	3.650	tNET	RR	1	R39C29[1][B]	u0_srio_response_gen/state_1_s0/CLK
4.032	0.382	tC2Q	RR	10	R39C29[1][B]	u0_srio_response_gen/state_1_s0/Q
4.210	0.178	tNET	RR	1	R38C29[1][B]	u0_srio_response_gen/tx_resp_trac_valid_s/I0
4.789	0.579	tINS	RR	10	R38C29[1][B]	u0_srio_response_gen/tx_resp_trac_valid_s/F
9.019	4.230	tNET	RR	1	R7C64[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/I0
9.526	0.507	tINS	RR	13	R7C64[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/F
10.198	0.671	tNET	RR	1	R8C67[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I3
10.516	0.319	tINS	RF	2	R8C67[3][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F
10.678	0.161	tNET	FF	1	R8C66[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3
10.966	0.289	tINS	FR	1	R8C66[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F
10.969	0.003	tNET	RR	1	R8C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0
11.536	0.567	tINS	RR	10	R8C66[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F
12.378	0.841	tNET	RR	1	R9C62[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n649_s2/I0
12.666	0.289	tINS	RR	1	R9C62[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n649_s2/F
12.669	0.003	tNET	RR	1	R9C62[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n649_s1/I2
13.216	0.548	tINS	RR	1	R9C62[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n649_s1/F
13.219	0.003	tNET	RR	1	R9C62[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n649_s0/I2
13.726	0.507	tINS	RR	1	R9C62[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n649_s0/F
13.726	0.000	tNET	RR	1	R9C62[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.524	3.724	tNET	RR	1	R9C62[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_3_s1/CLK
16.460	-0.064	tSu		1	R9C62[1][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_3_s1

Path Statistics:

Clock Skew	0.074
Setup Relationship	12.800
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.650, 100.000%
Arrival Data Path Delay	cell: 3.605, 35.777%; route: 6.089, 60.427%; tC2Q: 0.382, 3.796%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.724, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.140
Data Arrival Time	1.587
Data Required Time	1.447
From	u0_srio_response_gen/rx_req_din_10_s0
To	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.392	1.392	tNET	RR	1	R30C18[0][A]	u0_srio_response_gen/rx_req_din_10_s0/CLK
1.533	0.141	tC2Q	RF	1	R30C18[0][A]	u0_srio_response_gen/rx_req_din_10_s0/Q
1.587	0.054	tNET	FF	1	BSRAM_R28[2][B]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_0_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.410	1.410	tNET	RR	1	BSRAM_R28[2][B]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_0_s/CLKA
1.447	0.037	tHld		1	BSRAM_R28[2][B]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.018
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.392, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.410, 100.000%

Path2

Path Summary:

Slack	0.143
Data Arrival Time	1.590
Data Required Time	1.447
From	u0_srio_response_gen/rx_req_din_70_s0
To	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.415	1.415	tNET	RR	1	R45C29[3][A]	u0_srio_response_gen/rx_req_din_70_s0/CLK
1.556	0.141	tC2Q	RF	1	R45C29[3][A]	u0_srio_response_gen/rx_req_din_70_s0/Q
1.590	0.034	tNET	FF	1	BSRAM_R46[5]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.410	1.410	tNET	RR	1	BSRAM_R46[5]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/CLKA
1.447	0.037	tHld		1	BSRAM_R46[5]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.415, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.034, 19.429%; tC2Q: 0.141, 80.571%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.410, 100.000%

Path3

Path Summary:

Slack	0.143
Data Arrival Time	1.600
Data Required Time	1.457
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_5_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.425	1.425	tNET	RR	1	R45C56[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_5_s0/CLK
1.566	0.141	tC2Q	RF	1	R45C56[3][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_5_s0/Q
1.600	0.034	tNET	FF	1	BSRAM_R46[11]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.420	1.420	tNET	RR	1	BSRAM_R46[11]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.457	0.037	tHld		1	BSRAM_R46[11]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.425, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.034, 19.429%; tC2Q: 0.141, 80.571%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.420, 100.000%

Path4

Path Summary:

Slack	0.143
Data Arrival Time	1.600
Data Required Time	1.457
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_5_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.425	1.425	tNET	RR	1	R45C44[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_5_s0/CLK
1.566	0.141	tC2Q	RF	1	R45C44[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_5_s0/Q
1.600	0.034	tNET	FF	1	BSRAM_R46[8][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.420	1.420	tNET	RR	1	BSRAM_R46[8][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s/CLKA
1.457	0.037	tHld		1	BSRAM_R46[8][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.425, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.034, 19.429%; tC2Q: 0.141, 80.571%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.420, 100.000%

Path5

Path Summary:

Slack	0.144
Data Arrival Time	1.597
Data Required Time	1.453
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_4_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.402	1.402	tNET	RR	1	R30C47[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_4_s0/CLK
1.543	0.141	tC2Q	RF	1	R30C47[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_4_s0/Q
1.597	0.054	tNET	FF	1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.416	1.416	tNET	RR	1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.453	0.037	tHld		1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.402, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path6

Path Summary:

Slack	0.157
Data Arrival Time	1.610
Data Required Time	1.453
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/wr_ptr_9_s1
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_1_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.406	1.406	tNET	RR	1	R48C48[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/wr_ptr_9_s1/CLK
1.547	0.141	tC2Q	RF	7	R48C48[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/wr_ptr_9_s1/Q
1.610	0.063	tNET	FF	1	BSRAM_R46[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_1_s/ADA[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.416	1.416	tNET	RR	1	BSRAM_R46[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_1_s/CLKA
1.453	0.037	tHld		1	BSRAM_R46[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.063, 30.882%; tC2Q: 0.141, 69.118%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path7

Path Summary:

Slack	0.166
Data Arrival Time	1.606
Data Required Time	1.439
From	u0_srio_response_gen/fifo_wdata_3_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.403	1.403	tNET	RR	1	R35C23[1][B]	u0_srio_response_gen/fifo_wdata_3_s0/CLK
1.544	0.141	tC2Q	RF	1	R35C23[1][B]	u0_srio_response_gen/fifo_wdata_3_s0/Q
1.606	0.062	tNET	FF	1	BSRAM_R28[4][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.402	1.402	tNET	RR	1	BSRAM_R28[4][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/CLKA
1.439	0.037	tHld		1	BSRAM_R28[4][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.403, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.062, 30.542%; tC2Q: 0.141, 69.458%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.402, 100.000%

Path8

Path Summary:

Slack	0.193
Data Arrival Time	1.646
Data Required Time	1.453
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_56_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.411	1.411	tNET	RR	1	R29C71[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_56_s0/CLK
1.552	0.141	tC2Q	RF	1	R29C71[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_56_s0/Q
1.646	0.094	tNET	FF	1	BSRAM_R28[14][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.416	1.416	tNET	RR	1	BSRAM_R28[14][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.453	0.037	tHld		1	BSRAM_R28[14][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.411, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path9

Path Summary:

Slack	0.193
Data Arrival Time	1.646
Data Required Time	1.453
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_51_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.411	1.411	tNET	RR	1	R29C71[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_51_s0/CLK
1.552	0.141	tC2Q	RF	1	R29C71[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_51_s0/Q
1.646	0.094	tNET	FF	1	BSRAM_R28[14][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.416	1.416	tNET	RR	1	BSRAM_R28[14][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.453	0.037	tHld		1	BSRAM_R28[14][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.411, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path10

Path Summary:

Slack	0.193
Data Arrival Time	1.646
Data Required Time	1.453
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_5_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.411	1.411	tNET	RR	1	R29C47[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_5_s0/CLK
1.552	0.141	tC2Q	RF	1	R29C47[1][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_5_s0/Q
1.646	0.094	tNET	FF	1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.416	1.416	tNET	RR	1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.453	0.037	tHld		1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.411, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path11

Path Summary:

Slack	0.193
Data Arrival Time	1.646
Data Required Time	1.453
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_0_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.411	1.411	tNET	RR	1	R29C47[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_0_s0/CLK
1.552	0.141	tC2Q	RF	1	R29C47[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_0_s0/Q
1.646	0.094	tNET	FF	1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.416	1.416	tNET	RR	1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.453	0.037	tHld		1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.411, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path12

Path Summary:

Slack	0.193
Data Arrival Time	1.646
Data Required Time	1.453
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_1_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.411	1.411	tNET	RR	1	R29C59[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_1_s0/CLK
1.552	0.141	tC2Q	RF	1	R29C59[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_1_s0/Q
1.646	0.094	tNET	FF	1	BSRAM_R28[12][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.416	1.416	tNET	RR	1	BSRAM_R28[12][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s/CLKA
1.453	0.037	tHld		1	BSRAM_R28[12][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.411, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path13

Path Summary:

Slack	0.193
Data Arrival Time	1.654
Data Required Time	1.461
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_51_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.419	1.419	tNET	RR	1	R11C77[0][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_51_s0/CLK
1.560	0.141	tC2Q	RF	1	R11C77[0][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_51_s0/Q
1.654	0.094	tNET	FF	1	BSRAM_R10[17][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.424	1.424	tNET	RR	1	BSRAM_R10[17][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.461	0.037	tHld		1	BSRAM_R10[17][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.419, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.424, 100.000%

Path14

Path Summary:

Slack	0.193
Data Arrival Time	1.654
Data Required Time	1.461
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_41_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.419	1.419	tNET	RR	1	R29C65[0][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_41_s0/CLK
1.560	0.141	tC2Q	RF	1	R29C65[0][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_41_s0/Q
1.654	0.094	tNET	FF	1	BSRAM_R28[13]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.424	1.424	tNET	RR	1	BSRAM_R28[13]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s/CLKA
1.461	0.037	tHld		1	BSRAM_R28[13]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.419, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.424, 100.000%

Path15

Path Summary:

Slack	0.193
Data Arrival Time	1.654
Data Required Time	1.461
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_39_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.419	1.419	tNET	RR	1	R29C65[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_39_s0/CLK
1.560	0.141	tC2Q	RF	1	R29C65[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_39_s0/Q
1.654	0.094	tNET	FF	1	BSRAM_R28[13]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.424	1.424	tNET	RR	1	BSRAM_R28[13]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s/CLKA
1.461	0.037	tHld		1	BSRAM_R28[13]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.419, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.424, 100.000%

Path16

Path Summary:

Slack	0.197
Data Arrival Time	1.654
Data Required Time	1.457
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_13_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.419	1.419	tNET	RR	1	R47C57[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_13_s0/CLK
1.560	0.141	tC2Q	RF	1	R47C57[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_13_s0/Q
1.654	0.094	tNET	FF	1	BSRAM_R46[11]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.420	1.420	tNET	RR	1	BSRAM_R46[11]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.457	0.037	tHld		1	BSRAM_R46[11]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.419, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.420, 100.000%

Path17

Path Summary:

Slack	0.197
Data Arrival Time	1.654
Data Required Time	1.457
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_12_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.419	1.419	tNET	RR	1	R47C57[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_12_s0/CLK
1.560	0.141	tC2Q	RF	1	R47C57[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_12_s0/Q
1.654	0.094	tNET	FF	1	BSRAM_R46[11]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.420	1.420	tNET	RR	1	BSRAM_R46[11]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.457	0.037	tHld		1	BSRAM_R46[11]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.419, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.420, 100.000%

Path18

Path Summary:

Slack	0.197
Data Arrival Time	1.654
Data Required Time	1.457
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_31_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/gowin_add_SDPB_mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.419	1.419	tNET	RR	1	R29C45[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_31_s0/CLK
1.560	0.141	tC2Q	RF	1	R29C45[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_31_s0/Q
1.654	0.094	tNET	FF	1	BSRAM_R28[8][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/gowin_add_SDPB_mem_data_mem_data_0_0_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.420	1.420	tNET	RR	1	BSRAM_R28[8][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/gowin_add_SDPB_mem_data_mem_data_0_0_s/CLKA
1.457	0.037	tHld		1	BSRAM_R28[8][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/gowin_add_SDPB_mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.419, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.420, 100.000%

Path19

Path Summary:

Slack	0.197
Data Arrival Time	1.650
Data Required Time	1.453
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_11_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.415	1.415	tNET	RR	1	R29C48[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_11_s0/CLK
1.556	0.141	tC2Q	RF	1	R29C48[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_11_s0/Q
1.650	0.094	tNET	FF	1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.416	1.416	tNET	RR	1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.453	0.037	tHld		1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.415, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path20

Path Summary:

Slack	0.197
Data Arrival Time	1.650
Data Required Time	1.453
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_10_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.415	1.415	tNET	RR	1	R29C48[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_10_s0/CLK
1.556	0.141	tC2Q	RF	1	R29C48[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_10_s0/Q
1.650	0.094	tNET	FF	1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.416	1.416	tNET	RR	1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.453	0.037	tHld		1	BSRAM_R28[9]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.415, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path21

Path Summary:

Slack	0.197
Data Arrival Time	1.650
Data Required Time	1.453
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_15_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.415	1.415	tNET	RR	1	R29C60[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_15_s0/CLK
1.556	0.141	tC2Q	RF	1	R29C60[2][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_15_s0/Q
1.650	0.094	tNET	FF	1	BSRAM_R28[12][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.416	1.416	tNET	RR	1	BSRAM_R28[12][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s/CLKA
1.453	0.037	tHld		1	BSRAM_R28[12][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.415, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path22

Path Summary:

Slack	0.197
Data Arrival Time	1.650
Data Required Time	1.453
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_14_s0
To	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.415	1.415	tNET	RR	1	R29C60[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_14_s0/CLK
1.556	0.141	tC2Q	RF	1	R29C60[2][B]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/ram_wr_data_14_s0/Q
1.650	0.094	tNET	FF	1	BSRAM_R28[12][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.416	1.416	tNET	RR	1	BSRAM_R28[12][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s/CLKA
1.453	0.037	tHld		1	BSRAM_R28[12][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.415, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path23

Path Summary:

Slack	0.201
Data Arrival Time	1.648
Data Required Time	1.447
From	u0_srio_response_gen/rx_req_din_83_s0
To	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.411	1.411	tNET	RR	1	R45C30[2][B]	u0_srio_response_gen/rx_req_din_83_s0/CLK
1.555	0.144	tC2Q	RR	1	R45C30[2][B]	u0_srio_response_gen/rx_req_din_83_s0/Q
1.648	0.093	tNET	RR	1	BSRAM_R46[5]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.410	1.410	tNET	RR	1	BSRAM_R46[5]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/CLKA
1.447	0.037	tHld		1	BSRAM_R46[5]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.411, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.410, 100.000%

Path24

Path Summary:

Slack	0.202
Data Arrival Time	1.649
Data Required Time	1.447
From	u0_srio_response_gen/rx_req_din_82_s0
To	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.411	1.411	tNET	RR	1	R45C30[3][A]	u0_srio_response_gen/rx_req_din_82_s0/CLK
1.552	0.141	tC2Q	RF	1	R45C30[3][A]	u0_srio_response_gen/rx_req_din_82_s0/Q
1.649	0.097	tNET	FF	1	BSRAM_R46[5]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.410	1.410	tNET	RR	1	BSRAM_R46[5]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/CLKA
1.447	0.037	tHld		1	BSRAM_R46[5]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.411, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.097, 40.756%; tC2Q: 0.141, 59.244%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.410, 100.000%

Path25

Path Summary:

Slack	0.205
Data Arrival Time	1.652
Data Required Time	1.447
From	u0_srio_response_gen/rx_req_din_71_s0
To	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.415	1.415	tNET	RR	1	R45C29[2][B]	u0_srio_response_gen/rx_req_din_71_s0/CLK
1.559	0.144	tC2Q	RR	1	R45C29[2][B]	u0_srio_response_gen/rx_req_din_71_s0/Q
1.652	0.093	tNET	RR	1	BSRAM_R46[5]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.410	1.410	tNET	RR	1	BSRAM_R46[5]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/CLKA
1.447	0.037	tHld		1	BSRAM_R46[5]	u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.415, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.410, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	7.156
Data Arrival Time	8.928
Data Required Time	16.084
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.928	4.946	tNET	FF	1	R39C31[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.431	3.631	tNET	RR	1	R39C31[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0/CLK
16.084	-0.347	tSu		1	R39C31[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0

Path Statistics:

Clock Skew	0.017
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.946, 93.084%; tC2Q: 0.368, 6.916%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.631, 100.000%

Path2

Path Summary:

Slack	7.157
Data Arrival Time	8.922
Data Required Time	16.079
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.922	4.940	tNET	FF	1	R41C27[1][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.426	3.626	tNET	RR	1	R41C27[1][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0/CLK
16.079	-0.347	tSu		1	R41C27[1][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0

Path Statistics:

Clock Skew	0.012
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.940, 93.076%; tC2Q: 0.368, 6.924%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.626, 100.000%

Path3

Path Summary:

Slack	7.157
Data Arrival Time	8.922
Data Required Time	16.079
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.922	4.940	tNET	FF	1	R41C27[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.426	3.626	tNET	RR	1	R41C27[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0/CLK
16.079	-0.347	tSu		1	R41C27[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0

Path Statistics:

Clock Skew	0.012
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.940, 93.076%; tC2Q: 0.368, 6.924%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.626, 100.000%

Path4

Path Summary:

Slack	7.174
Data Arrival Time	8.921
Data Required Time	16.096
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.921	4.939	tNET	FF	1	R38C26[1][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.443	3.643	tNET	RR	1	R38C26[1][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0/CLK
16.096	-0.347	tSu		1	R38C26[1][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0

Path Statistics:

Clock Skew	0.029
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.939, 93.075%; tC2Q: 0.368, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.643, 100.000%

Path5

Path Summary:

Slack	7.174
Data Arrival Time	8.921
Data Required Time	16.096
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.921	4.939	tNET	FF	1	R38C26[2][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.443	3.643	tNET	RR	1	R38C26[2][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0/CLK
16.096	-0.347	tSu		1	R38C26[2][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0

Path Statistics:

Clock Skew	0.029
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.939, 93.075%; tC2Q: 0.368, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.643, 100.000%

Path6

Path Summary:

Slack	7.174
Data Arrival Time	8.921
Data Required Time	16.096
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_7_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.921	4.939	tNET	FF	1	R38C30[3][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.443	3.643	tNET	RR	1	R38C30[3][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_7_s0/CLK
16.096	-0.347	tSu		1	R38C30[3][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_7_s0

Path Statistics:

Clock Skew	0.029
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.939, 93.075%; tC2Q: 0.368, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.643, 100.000%

Path7

Path Summary:

Slack	7.175
Data Arrival Time	8.918
Data Required Time	16.093
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.918	4.937	tNET	FF	1	R39C28[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.441	3.641	tNET	RR	1	R39C28[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0/CLK
16.093	-0.347	tSu		1	R39C28[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0

Path Statistics:

Clock Skew	0.026
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.937, 93.071%; tC2Q: 0.368, 6.929%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.641, 100.000%

Path8

Path Summary:

Slack	7.175
Data Arrival Time	8.918
Data Required Time	16.093
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.918	4.937	tNET	FF	1	R39C28[0][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.441	3.641	tNET	RR	1	R39C28[0][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0/CLK
16.093	-0.347	tSu		1	R39C28[0][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0

Path Statistics:

Clock Skew	0.026
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.937, 93.071%; tC2Q: 0.368, 6.929%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.641, 100.000%

Path9

Path Summary:

Slack	7.175
Data Arrival Time	8.918
Data Required Time	16.093
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.918	4.937	tNET	FF	1	R39C28[1][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.441	3.641	tNET	RR	1	R39C28[1][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0/CLK
16.093	-0.347	tSu		1	R39C28[1][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0

Path Statistics:

Clock Skew	0.026
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.937, 93.071%; tC2Q: 0.368, 6.929%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.641, 100.000%

Path10

Path Summary:

Slack	7.175
Data Arrival Time	8.918
Data Required Time	16.093
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.918	4.937	tNET	FF	1	R39C28[0][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.441	3.641	tNET	RR	1	R39C28[0][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0/CLK
16.093	-0.347	tSu		1	R39C28[0][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0

Path Statistics:

Clock Skew	0.026
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.937, 93.071%; tC2Q: 0.368, 6.929%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.641, 100.000%

Path11

Path Summary:

Slack	7.175
Data Arrival Time	8.916
Data Required Time	16.091
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.916	4.934	tNET	FF	1	R40C26[3][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.438	3.638	tNET	RR	1	R40C26[3][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0/CLK
16.091	-0.347	tSu		1	R40C26[3][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.934, 93.068%; tC2Q: 0.368, 6.932%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.638, 100.000%

Path12

Path Summary:

Slack	7.175
Data Arrival Time	8.916
Data Required Time	16.091
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.916	4.934	tNET	FF	1	R40C28[3][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.438	3.638	tNET	RR	1	R40C28[3][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0/CLK
16.091	-0.347	tSu		1	R40C28[3][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.934, 93.068%; tC2Q: 0.368, 6.932%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.638, 100.000%

Path13

Path Summary:

Slack	7.175
Data Arrival Time	8.916
Data Required Time	16.091
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_3_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.916	4.934	tNET	FF	1	R40C30[1][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.438	3.638	tNET	RR	1	R40C30[1][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_3_s0/CLK
16.091	-0.347	tSu		1	R40C30[1][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_3_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.934, 93.068%; tC2Q: 0.368, 6.932%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.638, 100.000%

Path14

Path Summary:

Slack	7.175
Data Arrival Time	8.916
Data Required Time	16.091
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.916	4.934	tNET	FF	1	R40C30[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.438	3.638	tNET	RR	1	R40C30[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0/CLK
16.091	-0.347	tSu		1	R40C30[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.934, 93.068%; tC2Q: 0.368, 6.932%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.638, 100.000%

Path15

Path Summary:

Slack	7.175
Data Arrival Time	8.916
Data Required Time	16.091
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.916	4.934	tNET	FF	1	R40C30[2][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.438	3.638	tNET	RR	1	R40C30[2][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0/CLK
16.091	-0.347	tSu		1	R40C30[2][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.934, 93.068%; tC2Q: 0.368, 6.932%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.638, 100.000%

Path16

Path Summary:

Slack	7.175
Data Arrival Time	8.916
Data Required Time	16.091
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_8_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.916	4.934	tNET	FF	1	R40C30[3][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.438	3.638	tNET	RR	1	R40C30[3][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_8_s0/CLK
16.091	-0.347	tSu		1	R40C30[3][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_8_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.934, 93.068%; tC2Q: 0.368, 6.932%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.638, 100.000%

Path17

Path Summary:

Slack	7.175
Data Arrival Time	8.913
Data Required Time	16.088
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.913	4.931	tNET	FF	1	R41C30[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.436	3.636	tNET	RR	1	R41C30[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0/CLK
16.088	-0.347	tSu		1	R41C30[1][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0

Path Statistics:

Clock Skew	0.021
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.931, 93.064%; tC2Q: 0.368, 6.936%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.636, 100.000%

Path18

Path Summary:

Slack	7.175
Data Arrival Time	8.913
Data Required Time	16.088
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.913	4.931	tNET	FF	1	R41C30[0][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.436	3.636	tNET	RR	1	R41C30[0][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0/CLK
16.088	-0.347	tSu		1	R41C30[0][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0

Path Statistics:

Clock Skew	0.021
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.931, 93.064%; tC2Q: 0.368, 6.936%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.636, 100.000%

Path19

Path Summary:

Slack	7.175
Data Arrival Time	8.913
Data Required Time	16.088
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.913	4.931	tNET	FF	1	R41C30[0][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.436	3.636	tNET	RR	1	R41C30[0][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0/CLK
16.088	-0.347	tSu		1	R41C30[0][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0

Path Statistics:

Clock Skew	0.021
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.931, 93.064%; tC2Q: 0.368, 6.936%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.636, 100.000%

Path20

Path Summary:

Slack	7.193
Data Arrival Time	8.912
Data Required Time	16.105
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Full_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.912	4.930	tNET	FF	1	R38C29[0][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Full_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.452	3.652	tNET	RR	1	R38C29[0][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Full_s0/CLK
16.105	-0.347	tSu		1	R38C29[0][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Full_s0

Path Statistics:

Clock Skew	0.038
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.930, 93.063%; tC2Q: 0.368, 6.937%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.652, 100.000%

Path21

Path Summary:

Slack	7.193
Data Arrival Time	8.912
Data Required Time	16.105
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.912	4.930	tNET	FF	1	R38C29[0][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.452	3.652	tNET	RR	1	R38C29[0][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0/CLK
16.105	-0.347	tSu		1	R38C29[0][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0

Path Statistics:

Clock Skew	0.038
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.930, 93.063%; tC2Q: 0.368, 6.937%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.652, 100.000%

Path22

Path Summary:

Slack	7.193
Data Arrival Time	8.909
Data Required Time	16.103
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Empty_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.909	4.927	tNET	FF	1	R39C29[0][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Empty_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.450	3.650	tNET	RR	1	R39C29[0][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Empty_s0/CLK
16.103	-0.347	tSu		1	R39C29[0][A]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Empty_s0

Path Statistics:

Clock Skew	0.036
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.927, 93.059%; tC2Q: 0.368, 6.941%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.650, 100.000%

Path23

Path Summary:

Slack	7.193
Data Arrival Time	8.909
Data Required Time	16.103
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.909	4.927	tNET	FF	1	R39C29[0][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.450	3.650	tNET	RR	1	R39C29[0][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0/CLK
16.103	-0.347	tSu		1	R39C29[0][B]	u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0

Path Statistics:

Clock Skew	0.036
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.927, 93.059%; tC2Q: 0.368, 6.941%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.650, 100.000%

Path24

Path Summary:

Slack	7.263
Data Arrival Time	8.931
Data Required Time	16.194
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.931	4.949	tNET	FF	1	R2C47[3][A]	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.541	3.741	tNET	RR	1	R2C47[3][A]	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0/CLK
16.194	-0.347	tSu		1	R2C47[3][A]	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0

Path Statistics:

Clock Skew	0.127
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.949, 93.087%; tC2Q: 0.368, 6.913%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.741, 100.000%

Path25

Path Summary:

Slack	7.263
Data Arrival Time	8.928
Data Required Time	16.191
From	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_3_s0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.614	3.614	tNET	RR	1	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.982	0.368	tC2Q	RF	767	R34C33[3][B]	u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
8.928	4.946	tNET	FF	1	R3C51[1][A]	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					srio_clk
12.800	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.539	3.739	tNET	RR	1	R3C51[1][A]	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_3_s0/CLK
16.191	-0.347	tSu		1	R3C51[1][A]	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_3_s0

Path Statistics:

Clock Skew	0.124
Setup Relationship	12.800
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.614, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.946, 93.084%; tC2Q: 0.368, 6.916%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.739, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.289
Data Arrival Time	2.539
Data Required Time	1.250
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0
To	u_Serdes_Top/gtr12_quad_inst0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.418	1.418	tNET	RR	1	R51C40[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0/CLK
1.562	0.144	tC2Q	RR	3	R51C40[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0/Q
1.964	0.402	tNET	RR	1	R7C40[2][B]	u_Serdes_Top/SRIO_Top_inst/serdes_pcs_rx_rst_o_d_1_s/I1
2.218	0.254	tINS	RR	2	R7C40[2][B]	u_Serdes_Top/SRIO_Top_inst/serdes_pcs_rx_rst_o_d_1_s/F
2.539	0.321	tNET	RR	1	R0C38	u_Serdes_Top/gtr12_quad_inst0/LANE0_PCS_RX_RST

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.450	1.450	tNET	RR	1	R0C38	u_Serdes_Top/gtr12_quad_inst0/LANE0_FABRIC_RX_CLK
1.250	-0.199	tHld		1	R0C38	u_Serdes_Top/gtr12_quad_inst0

Path Statistics:

Clock Skew	0.032
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.418, 100.000%
Arrival Data Path Delay	cell: 0.254, 22.658%; route: 0.723, 64.496%; tC2Q: 0.144, 12.846%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%

Path2

Path Summary:

Slack	1.616
Data Arrival Time	2.856
Data Required Time	1.240
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0
To	u_Serdes_Top/gtr12_quad_inst0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.418	1.418	tNET	RR	1	R51C40[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0/CLK
1.562	0.144	tC2Q	RR	3	R51C40[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0/Q
2.254	0.692	tNET	RR	1	R7C38[0][B]	u_Serdes_Top/SRIO_Top_inst/serdes_pcs_tx_rst_o_d_1_s/I1
2.514	0.260	tINS	RR	2	R7C38[0][B]	u_Serdes_Top/SRIO_Top_inst/serdes_pcs_tx_rst_o_d_1_s/F
2.856	0.342	tNET	RR	1	R0C38	u_Serdes_Top/gtr12_quad_inst0/LANE0_PCS_TX_RST

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.450	1.450	tNET	RR	1	R0C38	u_Serdes_Top/gtr12_quad_inst0/LANE0_FABRIC_TX_CLK
1.240	-0.210	tHld		1	R0C38	u_Serdes_Top/gtr12_quad_inst0

Path Statistics:

Clock Skew	0.032
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.418, 100.000%
Arrival Data Path Delay	cell: 0.260, 18.081%; route: 1.034, 71.905%; tC2Q: 0.144, 10.014%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%

Path3

Path Summary:

Slack	1.703
Data Arrival Time	2.982
Data Required Time	1.279
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0
To	u_Serdes_Top/gtr12_quad_inst0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.418	1.418	tNET	RR	1	R51C40[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0/CLK
1.562	0.144	tC2Q	RR	3	R51C40[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0/Q
1.964	0.402	tNET	RR	1	R7C40[2][B]	u_Serdes_Top/SRIO_Top_inst/serdes_pcs_rx_rst_o_d_1_s/I1
2.218	0.254	tINS	RR	2	R7C40[2][B]	u_Serdes_Top/SRIO_Top_inst/serdes_pcs_rx_rst_o_d_1_s/F
2.982	0.764	tNET	RR	1	R0C38	u_Serdes_Top/gtr12_quad_inst0/LANE1_PCS_RX_RST

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.453	1.453	tNET	RR	1	R0C38	u_Serdes_Top/gtr12_quad_inst0/LANE1_FABRIC_RX_CLK
1.279	-0.174	tHld		1	R0C38	u_Serdes_Top/gtr12_quad_inst0

Path Statistics:

Clock Skew	0.035
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.418, 100.000%
Arrival Data Path Delay	cell: 0.254, 16.240%; route: 1.166, 74.552%; tC2Q: 0.144, 9.207%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.453, 100.000%

Path4

Path Summary:

Slack	1.785
Data Arrival Time	3.156
Data Required Time	1.371
From	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0
To	u_Serdes_Top/gtr12_quad_inst0
Launch Clk	srio_clk:[R]
Latch Clk	srio_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.418	1.418	tNET	RR	1	R51C40[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0/CLK
1.562	0.144	tC2Q	RR	3	R51C40[0][A]	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/gtr12_rstn_s0/Q
2.254	0.692	tNET	RR	1	R7C38[0][B]	u_Serdes_Top/SRIO_Top_inst/serdes_pcs_tx_rst_o_d_1_s/I1
2.514	0.260	tINS	RR	2	R7C38[0][B]	u_Serdes_Top/SRIO_Top_inst/serdes_pcs_tx_rst_o_d_1_s/F
3.156	0.642	tNET	RR	1	R0C38	u_Serdes_Top/gtr12_quad_inst0/LANE1_PCS_TX_RST

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					srio_clk
0.000	0.000	tCL	RR	7272	PLL_L[0]	u_gowin_serdes_pll/PLL_inst/CLKOUT1
1.453	1.453	tNET	RR	1	R0C38	u_Serdes_Top/gtr12_quad_inst0/LANE1_FABRIC_TX_CLK
1.371	-0.082	tHld		1	R0C38	u_Serdes_Top/gtr12_quad_inst0

Path Statistics:

Clock Skew	0.035
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.418, 100.000%
Arrival Data Path Delay	cell: 0.260, 14.960%; route: 1.334, 76.755%; tC2Q: 0.144, 8.285%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.453, 100.000%

Path5

Path Summary:

Slack	2.210
Data Arrival Time	3.555
Data Required Time	1.345
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_2_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.555	1.998	tNET	RR	1	R11C26[2][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.398	1.398	tNET	RR	1	R11C26[2][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_2_s0/CLK
1.345	-0.053	tHld		1	R11C26[2][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_2_s0

Path Statistics:

Clock Skew	-0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.998, 93.277%; tC2Q: 0.144, 6.723%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.398, 100.000%

Path6

Path Summary:

Slack	2.210
Data Arrival Time	3.551
Data Required Time	1.341
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_3_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.551	1.994	tNET	RR	1	R11C31[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.394	1.394	tNET	RR	1	R11C31[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_3_s0/CLK
1.341	-0.053	tHld		1	R11C31[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_3_s0

Path Statistics:

Clock Skew	-0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.994, 93.265%; tC2Q: 0.144, 6.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.394, 100.000%

Path7

Path Summary:

Slack	2.210
Data Arrival Time	3.551
Data Required Time	1.341
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_6_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.551	1.994	tNET	RR	1	R11C31[1][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.394	1.394	tNET	RR	1	R11C31[1][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_6_s0/CLK
1.341	-0.053	tHld		1	R11C31[1][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_6_s0

Path Statistics:

Clock Skew	-0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.994, 93.265%; tC2Q: 0.144, 6.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.394, 100.000%

Path8

Path Summary:

Slack	2.210
Data Arrival Time	3.551
Data Required Time	1.341
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_15_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.551	1.994	tNET	RR	1	R11C31[1][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.394	1.394	tNET	RR	1	R11C31[1][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_15_s0/CLK
1.341	-0.053	tHld		1	R11C31[1][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_15_s0

Path Statistics:

Clock Skew	-0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.994, 93.265%; tC2Q: 0.144, 6.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.394, 100.000%

Path9

Path Summary:

Slack	2.210
Data Arrival Time	3.551
Data Required Time	1.341
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.551	1.994	tNET	RR	1	R11C31[3][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.394	1.394	tNET	RR	1	R11C31[3][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s0/CLK
1.341	-0.053	tHld		1	R11C31[3][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s0

Path Statistics:

Clock Skew	-0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.994, 93.265%; tC2Q: 0.144, 6.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.394, 100.000%

Path10

Path Summary:

Slack	2.210
Data Arrival Time	3.551
Data Required Time	1.341
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.551	1.994	tNET	RR	1	R11C31[2][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.394	1.394	tNET	RR	1	R11C31[2][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0/CLK
1.341	-0.053	tHld		1	R11C31[2][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0

Path Statistics:

Clock Skew	-0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.994, 93.265%; tC2Q: 0.144, 6.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.394, 100.000%

Path11

Path Summary:

Slack	2.214
Data Arrival Time	3.565
Data Required Time	1.351
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_10_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.565	2.008	tNET	RR	1	R9C31[1][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_10_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.404	1.404	tNET	RR	1	R9C31[1][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_10_s0/CLK
1.351	-0.053	tHld		1	R9C31[1][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_10_s0

Path Statistics:

Clock Skew	-0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.008, 93.309%; tC2Q: 0.144, 6.691%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.404, 100.000%

Path12

Path Summary:

Slack	2.214
Data Arrival Time	3.565
Data Required Time	1.351
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_12_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.565	2.008	tNET	RR	1	R9C31[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_12_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.404	1.404	tNET	RR	1	R9C31[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_12_s0/CLK
1.351	-0.053	tHld		1	R9C31[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_12_s0

Path Statistics:

Clock Skew	-0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.008, 93.309%; tC2Q: 0.144, 6.691%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.404, 100.000%

Path13

Path Summary:

Slack	2.214
Data Arrival Time	3.569
Data Required Time	1.355
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.569	2.012	tNET	RR	1	R9C26[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.408	1.408	tNET	RR	1	R9C26[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0/CLK
1.355	-0.053	tHld		1	R9C26[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.012, 93.321%; tC2Q: 0.144, 6.679%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.408, 100.000%

Path14

Path Summary:

Slack	2.214
Data Arrival Time	3.569
Data Required Time	1.355
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_g2b_ptr_3_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.569	2.012	tNET	RR	1	R27C30[3][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_g2b_ptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.408	1.408	tNET	RR	1	R27C30[3][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_g2b_ptr_3_s0/CLK
1.355	-0.053	tHld		1	R27C30[3][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_g2b_ptr_3_s0

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.012, 93.321%; tC2Q: 0.144, 6.679%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.408, 100.000%

Path15

Path Summary:

Slack	2.214
Data Arrival Time	3.569
Data Required Time	1.355
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd1_ptr_3_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.569	2.012	tNET	RR	1	R27C30[1][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd1_ptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.408	1.408	tNET	RR	1	R27C30[1][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd1_ptr_3_s0/CLK
1.355	-0.053	tHld		1	R27C30[1][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd1_ptr_3_s0

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.012, 93.321%; tC2Q: 0.144, 6.679%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.408, 100.000%

Path16

Path Summary:

Slack	2.214
Data Arrival Time	3.565
Data Required Time	1.351
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_0_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.565	2.008	tNET	RR	1	R27C27[1][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.404	1.404	tNET	RR	1	R27C27[1][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_0_s0/CLK
1.351	-0.053	tHld		1	R27C27[1][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_0_s0

Path Statistics:

Clock Skew	-0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.008, 93.309%; tC2Q: 0.144, 6.691%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.404, 100.000%

Path17

Path Summary:

Slack	2.214
Data Arrival Time	3.565
Data Required Time	1.351
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_gray_ptr_2_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.565	2.008	tNET	RR	1	R27C27[0][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_gray_ptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.404	1.404	tNET	RR	1	R27C27[0][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_gray_ptr_2_s0/CLK
1.351	-0.053	tHld		1	R27C27[0][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_gray_ptr_2_s0

Path Statistics:

Clock Skew	-0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.008, 93.309%; tC2Q: 0.144, 6.691%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.404, 100.000%

Path18

Path Summary:

Slack	2.214
Data Arrival Time	3.565
Data Required Time	1.351
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_gray_ptr1_2_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.565	2.008	tNET	RR	1	R27C27[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_gray_ptr1_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.404	1.404	tNET	RR	1	R27C27[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_gray_ptr1_2_s0/CLK
1.351	-0.053	tHld		1	R27C27[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rp_wr_gray_ptr1_2_s0

Path Statistics:

Clock Skew	-0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.008, 93.309%; tC2Q: 0.144, 6.691%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.404, 100.000%

Path19

Path Summary:

Slack	2.214
Data Arrival Time	3.569
Data Required Time	1.355
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr_gray_ptr_0_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.569	2.012	tNET	RR	1	R27C30[0][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr_gray_ptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.408	1.408	tNET	RR	1	R27C30[0][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr_gray_ptr_0_s0/CLK
1.355	-0.053	tHld		1	R27C30[0][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr_gray_ptr_0_s0

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.012, 93.321%; tC2Q: 0.144, 6.679%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.408, 100.000%

Path20

Path Summary:

Slack	2.214
Data Arrival Time	3.569
Data Required Time	1.355
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr_gray_ptr_2_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.569	2.012	tNET	RR	1	R27C30[2][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr_gray_ptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.408	1.408	tNET	RR	1	R27C30[2][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr_gray_ptr_2_s0/CLK
1.355	-0.053	tHld		1	R27C30[2][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr_gray_ptr_2_s0

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.012, 93.321%; tC2Q: 0.144, 6.679%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.408, 100.000%

Path21

Path Summary:

Slack	2.214
Data Arrival Time	3.569
Data Required Time	1.355
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_gray_ptr_0_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.569	2.012	tNET	RR	1	R27C30[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_gray_ptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.408	1.408	tNET	RR	1	R27C30[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_gray_ptr_0_s0/CLK
1.355	-0.053	tHld		1	R27C30[0][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_gray_ptr_0_s0

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.012, 93.321%; tC2Q: 0.144, 6.679%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.408, 100.000%

Path22

Path Summary:

Slack	2.217
Data Arrival Time	3.582
Data Required Time	1.365
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_8_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.582	2.025	tNET	RR	1	R25C30[2][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.418	1.418	tNET	RR	1	R25C30[2][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_8_s0/CLK
1.365	-0.053	tHld		1	R25C30[2][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_8_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.025, 93.361%; tC2Q: 0.144, 6.639%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.418, 100.000%

Path23

Path Summary:

Slack	2.217
Data Arrival Time	3.578
Data Required Time	1.361
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_rw_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.578	2.021	tNET	RR	1	R25C23[2][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_rw_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.414	1.414	tNET	RR	1	R25C23[2][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_rw_s0/CLK
1.361	-0.053	tHld		1	R25C23[2][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_rw_s0

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.021, 93.349%; tC2Q: 0.144, 6.651%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.414, 100.000%

Path24

Path Summary:

Slack	2.217
Data Arrival Time	3.578
Data Required Time	1.361
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_1_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.578	2.021	tNET	RR	1	R25C23[3][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.414	1.414	tNET	RR	1	R25C23[3][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_1_s0/CLK
1.361	-0.053	tHld		1	R25C23[3][A]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_1_s0

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.021, 93.349%; tC2Q: 0.144, 6.651%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.414, 100.000%

Path25

Path Summary:

Slack	2.217
Data Arrival Time	3.578
Data Required Time	1.361
From	cfg_rst_srl_2_s0
To	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_2_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.413	1.413	tNET	RR	1	R26C34[2][B]	cfg_rst_srl_2_s0/CLK
1.557	0.144	tC2Q	RR	1056	R26C34[2][B]	cfg_rst_srl_2_s0/Q
3.578	2.021	tNET	RR	1	R25C23[2][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	3721	PLL_R[3]	u_gowin_pll/PLL_inst/CLKOUT0
1.414	1.414	tNET	RR	1	R25C23[2][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_2_s0/CLK
1.361	-0.053	tHld		1	R25C23[2][B]	u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_2_s0

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.413, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.021, 93.349%; tC2Q: 0.144, 6.651%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.414, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.373
Actual Width:	4.373
Required Width:	1.000
Type:	High Pulse Width
Clock:	srio_clk
Objects:	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			srio_clk
0.000	0.000	tCL	RR	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.726	3.726	tNET	RR	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			srio_clk
6.400	0.000	tCL	FF	u_gowin_serdes_pll/PLL_inst/CLKOUT1
8.099	1.699	tNET	FF	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_2_s/CLKA

MPW2

MPW Summary:

Slack:	3.373
Actual Width:	4.373
Required Width:	1.000
Type:	High Pulse Width
Clock:	srio_clk
Objects:	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			srio_clk
0.000	0.000	tCL	RR	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.726	3.726	tNET	RR	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_3_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			srio_clk
6.400	0.000	tCL	FF	u_gowin_serdes_pll/PLL_inst/CLKOUT1
8.099	1.699	tNET	FF	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_3_s/CLKB

MPW3

MPW Summary:

Slack:	3.373
Actual Width:	4.373
Required Width:	1.000
Type:	High Pulse Width
Clock:	srio_clk
Objects:	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/mem_data_mem_data_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			srio_clk
0.000	0.000	tCL	RR	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.726	3.726	tNET	RR	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/mem_data_mem_data_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			srio_clk
6.400	0.000	tCL	FF	u_gowin_serdes_pll/PLL_inst/CLKOUT1
8.099	1.699	tNET	FF	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/mem_data_mem_data_0_0_s/CLKA

MPW4

MPW Summary:

Slack:	3.373
Actual Width:	4.373
Required Width:	1.000
Type:	High Pulse Width
Clock:	srio_clk
Objects:	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/mem_data_mem_data_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			srio_clk
0.000	0.000	tCL	RR	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.726	3.726	tNET	RR	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/mem_data_mem_data_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			srio_clk
6.400	0.000	tCL	FF	u_gowin_serdes_pll/PLL_inst/CLKOUT1
8.099	1.699	tNET	FF	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/mem_data_mem_data_0_0_s/CLKB

MPW5

MPW Summary:

Slack:	3.373
Actual Width:	4.373
Required Width:	1.000
Type:	High Pulse Width
Clock:	srio_clk
Objects:	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			srio_clk
0.000	0.000	tCL	RR	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.726	3.726	tNET	RR	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			srio_clk
6.400	0.000	tCL	FF	u_gowin_serdes_pll/PLL_inst/CLKOUT1
8.099	1.699	tNET	FF	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s/CLKB

MPW6

MPW Summary:

Slack:	3.373
Actual Width:	4.373
Required Width:	1.000
Type:	High Pulse Width
Clock:	srio_clk
Objects:	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			srio_clk
0.000	0.000	tCL	RR	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.726	3.726	tNET	RR	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_3_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			srio_clk
6.400	0.000	tCL	FF	u_gowin_serdes_pll/PLL_inst/CLKOUT1
8.099	1.699	tNET	FF	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_3_s/CLKA

MPW7

MPW Summary:

Slack:	3.373
Actual Width:	4.373
Required Width:	1.000
Type:	High Pulse Width
Clock:	srio_clk
Objects:	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			srio_clk
0.000	0.000	tCL	RR	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.726	3.726	tNET	RR	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			srio_clk
6.400	0.000	tCL	FF	u_gowin_serdes_pll/PLL_inst/CLKOUT1
8.099	1.699	tNET	FF	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/CLKB

MPW8

MPW Summary:

Slack:	3.373
Actual Width:	4.373
Required Width:	1.000
Type:	High Pulse Width
Clock:	srio_clk
Objects:	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/gowin_add_SDPB_mem_data_mem_data_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			srio_clk
0.000	0.000	tCL	RR	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.726	3.726	tNET	RR	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/gowin_add_SDPB_mem_data_mem_data_0_2_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			srio_clk
6.400	0.000	tCL	FF	u_gowin_serdes_pll/PLL_inst/CLKOUT1
8.099	1.699	tNET	FF	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/gowin_add_SDPB_mem_data_mem_data_0_2_s/CLKB

MPW9

MPW Summary:

Slack:	3.373
Actual Width:	4.373
Required Width:	1.000
Type:	High Pulse Width
Clock:	srio_clk
Objects:	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/gowin_add_SDPB_mem_data_mem_data_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			srio_clk
0.000	0.000	tCL	RR	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.726	3.726	tNET	RR	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/gowin_add_SDPB_mem_data_mem_data_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			srio_clk
6.400	0.000	tCL	FF	u_gowin_serdes_pll/PLL_inst/CLKOUT1
8.099	1.699	tNET	FF	u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/gowin_add_SDPB_mem_data_mem_data_0_1_s/CLKA

MPW10

MPW Summary:

Slack:	3.373
Actual Width:	4.373
Required Width:	1.000
Type:	High Pulse Width
Clock:	srio_clk
Objects:	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/gowin_add_SDPB_mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			srio_clk
0.000	0.000	tCL	RR	u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.726	3.726	tNET	RR	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/gowin_add_SDPB_mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			srio_clk
6.400	0.000	tCL	FF	u_gowin_serdes_pll/PLL_inst/CLKOUT1
8.099	1.699	tNET	FF	u0_srio_request_gen/u_fifo_top/fifo_sc_inst/gowin_add_SDPB_mem_mem_0_0_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
7272	srio_clk	0.402	3.772
3721	clk_10m	88.024	3.746
1191	u_gowin_srio_maints/maint_address[3]	91.022	5.841
1190	u_gowin_srio_maints/maint_address[2]	91.321	6.069
1188	u_gowin_srio_maints/maint_address[0]	90.940	6.691
1186	u_gowin_srio_maints/maint_address[1]	90.291	6.840
1056	cfg_rst_srl[2]	91.720	5.353
767	srio_ui_rst	4.399	5.476
595	u_gowin_srio_maints/maint_address[4]	93.658	4.338
299	u_gowin_srio_maints/maint_address[5]	91.990	5.328

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C32	100.00%
R2C51	100.00%
R2C57	100.00%
R2C61	100.00%
R2C62	100.00%
R2C63	100.00%
R3C11	100.00%
R4C87	100.00%
R7C59	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name srio_clk -period 12.8 -waveform {0 6.4} [get_nets {srio_clk}]
TC_CLOCK	Actived	create_clock -name cfg_clk -period 100 -waveform {0 50} [get_nets {clk_10m}]
TC_CLOCK	Actived	create_clock -name pll_ref_clk -period 20 -waveform {0 10} [get_ports {sys_clk_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {srio_clk}] -to [get_clocks {cfg_clk}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {cfg_clk}] -to [get_clocks {srio_clk}]