Power Messages

Report Title	Power Analysis Report
Design File	F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\impl\gwsynthesis\srio_ed_prj.vg
Physical Constraints File	F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\srio_ed_prj.cst
Timing Constraints File	F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\srio_ed_prj.sdc
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW5AST-LV138FPG676AES
Device	GW5AST-138
Device Version	B
Created Time	Tue Dec 30 15:44:06 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade	Commercial
Process	Typical
Ambient Temperature	25.000
Use Custom Theta JA	false
Heat Sink	None
Air Flow	LFM_0
Use Custom Theta SA	false
Board Thermal Model	None
Use Custom Theta JB	false
Related Vcd File
Related Saif File
Filter Glitches	false
Default IO Toggle Rate	0.125
Default Remain Toggle Rate	0.125

Power Summary

Power Information:

Total Power (mW)	272.011
Quiescent Power (mW)	100.762
Dynamic Power (mW)	171.249

Thermal Information:

Junction Temperature	28.325
Theta JA	12.222
Max Allowed Ambient Temperature	81.675

Supply Information:

Voltage Source	Voltage	Dynamic Current(mA)	Quiescent Current(mA)	Power(mW)
VCC	0.900	189.668	80.013	242.713
VCCX	1.800	0.106	7.200	13.151
VCCIO33	3.300	0.108	3.039	10.387
VCCLDO	1.200	0.000	4.800	5.760

Power Details

Power By Block Type:

Block Type	Total Power(mW)	Static Power(mW)	Average Toggle Rate(millions of transitions/sec)
Logic	4.200	NA	6.817
IO	11.987	11.344	5.463
BSRAM	156.752	NA	NA
PLL	9.648	NA	NA

Power By Hierarchy:

Hierarchy Entity	Total Power(mW)	Block Dynamic Power(mW)
srio_board	170.601	170.601(170.521)
srio_board/u0_srio_request_gen/	9.482	9.482(8.452)
srio_board/u0_srio_request_gen/u_fifo_top/	8.452	8.452(8.452)
srio_board/u0_srio_request_gen/u_fifo_top/fifo_sc_inst/	8.452	8.452(0.000)
srio_board/u0_srio_response_gen/	42.194	42.194(42.067)
srio_board/u0_srio_response_gen/u0_sdpram_dat/	25.211	25.211(0.000)
srio_board/u0_srio_response_gen/u_fifo_top/	16.856	16.856(16.856)
srio_board/u0_srio_response_gen/u_fifo_top/fifo_sc_inst/	16.856	16.856(0.000)
srio_board/u_Serdes_Top/	109.039	109.039(109.039)
srio_board/u_Serdes_Top/SRIO_Top_inst/	109.039	109.039(109.037)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/	109.037	109.037(109.034)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/	54.584	54.584(54.584)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/	17.350	17.350(17.229)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/	17.229	17.229(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/	37.234	37.234(36.979)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/	3.896	3.896(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[1].u_pri_fifo/	3.895	3.895(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[2].u_pri_fifo/	3.895	3.895(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[3].u_pri_fifo/	3.895	3.895(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_ram_delay/	0.085	0.085(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_ackid/	4.202	4.202(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/	17.111	17.111(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_cfg/	0.145	0.145(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/	0.765	0.765(0.765)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/	0.273	0.273(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/	0.492	0.492(0.492)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/	0.212	0.212(0.003)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/	0.003	0.003(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/	0.280	0.280(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/	47.557	47.557(47.552)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_cfg_bridge/	0.004	0.004(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/	19.014	19.014(18.996)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/	9.498	9.498(9.479)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/	9.479	9.479(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/	9.498	9.498(9.479)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/	9.479	9.479(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_resp_maints/	0.007	0.007(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/	28.508	28.508(28.481)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u0_gen_async_fifo/	14.241	14.241(14.219)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u0_gen_async_fifo/u_async_data_buffer/	14.219	14.219(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/	14.241	14.241(14.219)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/	14.219	14.219(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_req_maints/	0.020	0.020(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/	5.983	5.983(5.983)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_link_init/	0.015	0.015(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_oplm_top/	0.387	0.387(0.358)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_oplm_top/[0].u_lane_sync/	0.057	0.057(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_oplm_top/[1].u_lane_sync/	0.057	0.057(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_oplm_top/port_init_nx/	0.038	0.038(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_oplm_top/u_lane_align/	0.018	0.018(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_oplm_top/u_oplm_rx/	0.093	0.093(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_oplm_top/u_oplm_tx/	0.095	0.095(0.095)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_oplm_top/u_oplm_tx/u_idle_seq_gen/	0.016	0.016(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_oplm_top/u_oplm_tx/u_oplm_tx_adapt/	0.033	0.033(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_oplm_top/u_oplm_tx/u_oplm_tx_assemble/	0.046	0.046(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_rx/	0.964	0.964(0.964)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_rx/u_rx_cs_deal/	0.070	0.070(0.058)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_rx/u_rx_cs_deal/u_rx_cs_stack/	0.058	0.058(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_rx/u_rx_cs_decode/	0.136	0.136(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_rx/u_rx_data_deal/	0.280	0.280(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_rx/u_rx_err_mgn/	0.028	0.028(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_rx/u_srio_rx_crc16_v1/	0.450	0.450(0.104)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_rx/u_srio_rx_crc16_v1/u_srio_crc16_16w/	0.013	0.013(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_rx/u_srio_rx_crc16_v1/u_srio_crc16_32w/	0.025	0.025(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_rx/u_srio_rx_crc16_v1/u_srio_crc16_48w/	0.028	0.028(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_rx/u_srio_rx_crc16_v1/u_srio_crc16_64w/	0.037	0.037(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/	4.617	4.617(4.598)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_control_sym_gen/	4.262	4.262(4.253)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_control_sym_gen/u_embed_queue/	4.253	4.253(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_srio_tx_crc16_v1/	0.254	0.254(0.138)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_srio_tx_crc16_v1/u_srio_crc16_16w/	0.013	0.013(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_srio_tx_crc16_v1/u_srio_crc16_32w/	0.019	0.019(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_srio_tx_crc16_v1/u_srio_crc16_48w/	0.028	0.028(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_srio_tx_crc16_v1/u_srio_crc16_64w/	0.041	0.041(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_srio_tx_crc16_v1/u_srio_crc16_mid/	0.037	0.037(0.000)
srio_board/u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_phy_top/u_phy_ollm_tx/u_tx_assemble/	0.082	0.082(0.000)
srio_board/u_cfg_2to1/	0.004	0.004(0.000)
srio_board/u_gowin_pll/	9.648	9.648(0.000)
srio_board/u_gowin_srio_maints/	0.059	0.059(0.000)
srio_board/u_testreg/	0.011	0.011(0.000)
srio_board/u_uart_to_bus_top/	0.083	0.083(0.083)
srio_board/u_uart_to_bus_top/uart_bus_core/	0.083	0.083(0.078)
srio_board/u_uart_to_bus_top/uart_bus_core/u_uart_md/	0.078	0.078(0.078)
srio_board/u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/	0.003	0.003(0.000)
srio_board/u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/	0.037	0.037(0.037)
srio_board/u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/	0.035	0.035(0.027)
srio_board/u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/	0.027	0.027(0.000)
srio_board/u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/	0.002	0.002(0.000)
srio_board/u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/	0.038	0.038(0.038)
srio_board/u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/	0.034	0.034(0.028)
srio_board/u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/	0.028	0.028(0.000)
srio_board/u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/	0.003	0.003(0.000)

Power By Clock Domain:

Clock Domain	Clock Frequency(Mhz)	Total Dynamic Power(mW)
cfg_clk	10.000	5.618
srio_clk	78.125	155.339
NO CLOCK DOMAIN	0.000	0.000
pll_ref_clk	50.000	9.648