Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\debug\cfg_2to1.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\debug\testreg.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\fifo_sc_top\fifo_sc_top.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\gowin_pll\gowin_pll.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\gowin_pll\gowin_serdes_pll_1p25g.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\gowin_pll\gowin_serdes_pll_2p5g.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\gowin_pll\gowin_serdes_pll_3p125g.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\gowin_pll\gowin_serdes_pll_5g.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\serdes\serdes.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\serdes\srio\srio.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\srio_board.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\test\gowin_sdpram.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\test\gowin_srio_maints.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\test\gowin_srio_request_gen.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\test\gowin_srio_response_gen.v F:\138k_serdes\20251230\Gowin_Serial_RapidIO_RefDesign\project\src\uart_to_bus\uart_to_bus.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Dec 30 15:43:16 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | srio_board |
| Synthesis Process | Running parser: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 569.699MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.906s, Elapsed time = 0h 0m 0.912s, Peak memory usage = 569.699MB Optimizing Phase 1: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.563s, Peak memory usage = 569.699MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 569.699MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.665s, Peak memory usage = 569.699MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 569.699MB Inferring Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.108s, Peak memory usage = 569.699MB Inferring Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 569.699MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 569.699MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.216s, Peak memory usage = 569.699MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.089s, Peak memory usage = 569.699MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 569.699MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.659s, Peak memory usage = 569.699MB Generate output files: CPU time = 0h 0m 0.828s, Elapsed time = 0h 0m 0.868s, Peak memory usage = 569.699MB |
| Total Time and Memory Usage | CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 569.699MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 13 |
| I/O Buf | 13 |
| IBUF | 4 |
| OBUF | 9 |
| Register | 10895 |
| DFFSE | 383 |
| DFFRE | 8611 |
| DFFPE | 20 |
| DFFCE | 1881 |
| LUT | 9831 |
| LUT2 | 1335 |
| LUT3 | 2782 |
| LUT4 | 5714 |
| ALU | 852 |
| ALU | 852 |
| INV | 139 |
| INV | 139 |
| BSRAM | 32 |
| SDPB | 22 |
| SDPX9B | 8 |
| pROM | 2 |
| CLOCK | 2 |
| PLL | 2 |
| GTR12_QUAD | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 10822(9970 LUT, 852 ALU) / 138240 | 8% |
| Register | 10895 / 139140 | 8% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 10895 / 139140 | 8% |
| BSRAM | 32 / 340 | 10% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | sys_clk_i | Base | 20.000 | 50.000 | 0.000 | 10.000 | sys_clk_i_ibuf/I | ||
| 2 | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk | Generated | 100.000 | 10.000 | 0.000 | 50.000 | sys_clk_i_ibuf/I | sys_clk_i | u_gowin_pll/PLL_inst/CLKOUT0 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk | 10.000(MHz) | 114.074(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 91.234 |
| Data Arrival Time | 9.415 |
| Data Required Time | 100.649 |
| From | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
| To | u_testreg/cfg_prdata_o_12_s0 |
| Launch Clk | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.300 | 0.300 | tCL | RR | 3711 | u_gowin_pll/PLL_inst/CLKOUT0 |
| 0.713 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
| 1.095 | 0.382 | tC2Q | RR | 4 | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
| 1.508 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s3/I0 |
| 2.087 | 0.579 | tINS | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s3/F |
| 2.499 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s1/I0 |
| 3.078 | 0.579 | tINS | RR | 3 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s1/F |
| 3.490 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s/I1 |
| 4.058 | 0.567 | tINS | RR | 80 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s/F |
| 4.470 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_addr_o_d_2_s/I1 |
| 5.038 | 0.567 | tINS | RR | 36 | u_uart_to_bus_top/uart_bus_core/apb0_addr_o_d_2_s/F |
| 5.450 | 0.413 | tNET | RR | 1 | u_testreg/n1066_s2/I0 |
| 6.029 | 0.579 | tINS | RR | 2 | u_testreg/n1066_s2/F |
| 6.442 | 0.413 | tNET | RR | 1 | u_testreg/n1066_s3/I0 |
| 7.020 | 0.579 | tINS | RR | 31 | u_testreg/n1066_s3/F |
| 7.433 | 0.413 | tNET | RR | 1 | u_testreg/n367_s19/I0 |
| 8.012 | 0.579 | tINS | RR | 1 | u_testreg/n367_s19/F |
| 8.424 | 0.413 | tNET | RR | 1 | u_testreg/n367_s18/I0 |
| 9.003 | 0.579 | tINS | RR | 1 | u_testreg/n367_s18/F |
| 9.415 | 0.413 | tNET | RR | 1 | u_testreg/cfg_prdata_o_12_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 100.000 | 0.000 | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 100.300 | 0.300 | tCL | RR | 3711 | u_gowin_pll/PLL_inst/CLKOUT0 |
| 100.713 | 0.413 | tNET | RR | 1 | u_testreg/cfg_prdata_o_12_s0/CLK |
| 100.649 | -0.064 | tSu | 1 | u_testreg/cfg_prdata_o_12_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 100.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.608, 52.945%; route: 3.712, 42.660%; tC2Q: 0.382, 4.395% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 91.234 |
| Data Arrival Time | 9.415 |
| Data Required Time | 100.649 |
| From | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
| To | u_testreg/cfg_prdata_o_16_s0 |
| Launch Clk | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.300 | 0.300 | tCL | RR | 3711 | u_gowin_pll/PLL_inst/CLKOUT0 |
| 0.713 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
| 1.095 | 0.382 | tC2Q | RR | 4 | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
| 1.508 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s3/I0 |
| 2.087 | 0.579 | tINS | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s3/F |
| 2.499 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s1/I0 |
| 3.078 | 0.579 | tINS | RR | 3 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s1/F |
| 3.490 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s/I1 |
| 4.058 | 0.567 | tINS | RR | 80 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s/F |
| 4.470 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_addr_o_d_2_s/I1 |
| 5.038 | 0.567 | tINS | RR | 36 | u_uart_to_bus_top/uart_bus_core/apb0_addr_o_d_2_s/F |
| 5.450 | 0.413 | tNET | RR | 1 | u_testreg/n1066_s2/I0 |
| 6.029 | 0.579 | tINS | RR | 2 | u_testreg/n1066_s2/F |
| 6.442 | 0.413 | tNET | RR | 1 | u_testreg/n1066_s3/I0 |
| 7.020 | 0.579 | tINS | RR | 31 | u_testreg/n1066_s3/F |
| 7.433 | 0.413 | tNET | RR | 1 | u_testreg/n355_s16/I0 |
| 8.012 | 0.579 | tINS | RR | 1 | u_testreg/n355_s16/F |
| 8.424 | 0.413 | tNET | RR | 1 | u_testreg/n355_s15/I0 |
| 9.003 | 0.579 | tINS | RR | 1 | u_testreg/n355_s15/F |
| 9.415 | 0.413 | tNET | RR | 1 | u_testreg/cfg_prdata_o_16_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 100.000 | 0.000 | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 100.300 | 0.300 | tCL | RR | 3711 | u_gowin_pll/PLL_inst/CLKOUT0 |
| 100.713 | 0.413 | tNET | RR | 1 | u_testreg/cfg_prdata_o_16_s0/CLK |
| 100.649 | -0.064 | tSu | 1 | u_testreg/cfg_prdata_o_16_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 100.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.608, 52.945%; route: 3.712, 42.660%; tC2Q: 0.382, 4.395% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 91.234 |
| Data Arrival Time | 9.415 |
| Data Required Time | 100.649 |
| From | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
| To | u_testreg/cfg_prdata_o_17_s0 |
| Launch Clk | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.300 | 0.300 | tCL | RR | 3711 | u_gowin_pll/PLL_inst/CLKOUT0 |
| 0.713 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
| 1.095 | 0.382 | tC2Q | RR | 4 | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
| 1.508 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s3/I0 |
| 2.087 | 0.579 | tINS | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s3/F |
| 2.499 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s1/I0 |
| 3.078 | 0.579 | tINS | RR | 3 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s1/F |
| 3.490 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s/I1 |
| 4.058 | 0.567 | tINS | RR | 80 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s/F |
| 4.470 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_addr_o_d_2_s/I1 |
| 5.038 | 0.567 | tINS | RR | 36 | u_uart_to_bus_top/uart_bus_core/apb0_addr_o_d_2_s/F |
| 5.450 | 0.413 | tNET | RR | 1 | u_testreg/n1066_s2/I0 |
| 6.029 | 0.579 | tINS | RR | 2 | u_testreg/n1066_s2/F |
| 6.442 | 0.413 | tNET | RR | 1 | u_testreg/n1066_s3/I0 |
| 7.020 | 0.579 | tINS | RR | 31 | u_testreg/n1066_s3/F |
| 7.433 | 0.413 | tNET | RR | 1 | u_testreg/n352_s16/I0 |
| 8.012 | 0.579 | tINS | RR | 1 | u_testreg/n352_s16/F |
| 8.424 | 0.413 | tNET | RR | 1 | u_testreg/n352_s15/I0 |
| 9.003 | 0.579 | tINS | RR | 1 | u_testreg/n352_s15/F |
| 9.415 | 0.413 | tNET | RR | 1 | u_testreg/cfg_prdata_o_17_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 100.000 | 0.000 | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 100.300 | 0.300 | tCL | RR | 3711 | u_gowin_pll/PLL_inst/CLKOUT0 |
| 100.713 | 0.413 | tNET | RR | 1 | u_testreg/cfg_prdata_o_17_s0/CLK |
| 100.649 | -0.064 | tSu | 1 | u_testreg/cfg_prdata_o_17_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 100.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.608, 52.945%; route: 3.712, 42.660%; tC2Q: 0.382, 4.395% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 91.245 |
| Data Arrival Time | 9.404 |
| Data Required Time | 100.649 |
| From | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
| To | u_testreg/cfg_prdata_o_4_s0 |
| Launch Clk | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.300 | 0.300 | tCL | RR | 3711 | u_gowin_pll/PLL_inst/CLKOUT0 |
| 0.713 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
| 1.095 | 0.382 | tC2Q | RR | 4 | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
| 1.508 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s3/I0 |
| 2.087 | 0.579 | tINS | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s3/F |
| 2.499 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s1/I0 |
| 3.078 | 0.579 | tINS | RR | 3 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s1/F |
| 3.490 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s/I1 |
| 4.058 | 0.567 | tINS | RR | 80 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s/F |
| 4.470 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_addr_o_d_2_s/I1 |
| 5.038 | 0.567 | tINS | RR | 36 | u_uart_to_bus_top/uart_bus_core/apb0_addr_o_d_2_s/F |
| 5.450 | 0.413 | tNET | RR | 1 | u_testreg/n1066_s2/I0 |
| 6.029 | 0.579 | tINS | RR | 2 | u_testreg/n1066_s2/F |
| 6.442 | 0.413 | tNET | RR | 1 | u_testreg/n1066_s3/I0 |
| 7.020 | 0.579 | tINS | RR | 31 | u_testreg/n1066_s3/F |
| 7.433 | 0.413 | tNET | RR | 1 | u_testreg/n391_s21/I0 |
| 8.012 | 0.579 | tINS | RR | 1 | u_testreg/n391_s21/F |
| 8.424 | 0.413 | tNET | RR | 1 | u_testreg/n391_s19/I1 |
| 8.992 | 0.567 | tINS | RR | 1 | u_testreg/n391_s19/F |
| 9.404 | 0.413 | tNET | RR | 1 | u_testreg/cfg_prdata_o_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 100.000 | 0.000 | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 100.300 | 0.300 | tCL | RR | 3711 | u_gowin_pll/PLL_inst/CLKOUT0 |
| 100.713 | 0.413 | tNET | RR | 1 | u_testreg/cfg_prdata_o_4_s0/CLK |
| 100.649 | -0.064 | tSu | 1 | u_testreg/cfg_prdata_o_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 100.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.596, 52.884%; route: 3.712, 42.715%; tC2Q: 0.382, 4.401% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 91.245 |
| Data Arrival Time | 9.404 |
| Data Required Time | 100.649 |
| From | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
| To | u_testreg/cfg_prdata_o_8_s0 |
| Launch Clk | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.300 | 0.300 | tCL | RR | 3711 | u_gowin_pll/PLL_inst/CLKOUT0 |
| 0.713 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
| 1.095 | 0.382 | tC2Q | RR | 4 | u_uart_to_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
| 1.508 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s3/I0 |
| 2.087 | 0.579 | tINS | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s3/F |
| 2.499 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s1/I0 |
| 3.078 | 0.579 | tINS | RR | 3 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s1/F |
| 3.490 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s/I1 |
| 4.058 | 0.567 | tINS | RR | 80 | u_uart_to_bus_top/uart_bus_core/apb0_sel_o_d_s/F |
| 4.470 | 0.413 | tNET | RR | 1 | u_uart_to_bus_top/uart_bus_core/apb0_addr_o_d_2_s/I1 |
| 5.038 | 0.567 | tINS | RR | 36 | u_uart_to_bus_top/uart_bus_core/apb0_addr_o_d_2_s/F |
| 5.450 | 0.413 | tNET | RR | 1 | u_testreg/n1066_s2/I0 |
| 6.029 | 0.579 | tINS | RR | 2 | u_testreg/n1066_s2/F |
| 6.442 | 0.413 | tNET | RR | 1 | u_testreg/n1066_s3/I0 |
| 7.020 | 0.579 | tINS | RR | 31 | u_testreg/n1066_s3/F |
| 7.433 | 0.413 | tNET | RR | 1 | u_testreg/n379_s21/I1 |
| 8.000 | 0.567 | tINS | RR | 1 | u_testreg/n379_s21/F |
| 8.413 | 0.413 | tNET | RR | 1 | u_testreg/n379_s20/I0 |
| 8.991 | 0.579 | tINS | RR | 1 | u_testreg/n379_s20/F |
| 9.404 | 0.413 | tNET | RR | 1 | u_testreg/cfg_prdata_o_8_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 100.000 | 0.000 | u_gowin_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 100.300 | 0.300 | tCL | RR | 3711 | u_gowin_pll/PLL_inst/CLKOUT0 |
| 100.713 | 0.413 | tNET | RR | 1 | u_testreg/cfg_prdata_o_8_s0/CLK |
| 100.649 | -0.064 | tSu | 1 | u_testreg/cfg_prdata_o_8_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 100.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.596, 52.884%; route: 3.712, 42.715%; tC2Q: 0.382, 4.401% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |