Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\SERDES_IP\IPlib\1GSERETH\data\ge_pcs.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\SERDES_IP\IPlib\1GSERETH\data\ge_pcs_wrap.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Dec 30 10:23:23 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Giga_Serial_Ethernet_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 1s, Peak memory usage = 87.211MB Running netlist conversion: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 87.211MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.253s, Peak memory usage = 87.211MB Optimizing Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.152s, Peak memory usage = 87.211MB Optimizing Phase 2: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.32s, Peak memory usage = 87.211MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.125s, Peak memory usage = 87.211MB Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 87.211MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 87.211MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 87.211MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.27s, Peak memory usage = 87.211MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.084s, Peak memory usage = 87.211MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 87.211MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 4s, Peak memory usage = 112.031MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.28s, Peak memory usage = 112.031MB Generate output files: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.952s, Peak memory usage = 112.031MB |
| Total Time and Memory Usage | CPU time = 0h 0m 5s, Elapsed time = 0h 0m 7s, Peak memory usage = 112.031MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 419 |
| I/O Buf | 417 |
| IBUF | 175 |
| OBUF | 242 |
| Register | 1516 |
| DFFRE | 42 |
| DFFPE | 81 |
| DFFCE | 1393 |
| LUT | 1650 |
| LUT2 | 228 |
| LUT3 | 333 |
| LUT4 | 1089 |
| ALU | 44 |
| ALU | 44 |
| INV | 15 |
| INV | 15 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1709(1665 LUT, 44 ALU) / 138240 | 2% |
| Register | 1516 / 139140 | 2% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 1516 / 139140 | 2% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | serdes_pcs_rx_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | serdes_pcs_rx_clk_i_ibuf/I | ||
| 2 | serdes_pcs_tx_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | serdes_pcs_tx_clk_i_ibuf/I | ||
| 3 | clk_in_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_in_i_ibuf/I | ||
| 4 | miim_hs_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | miim_hs_clk_i_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | serdes_pcs_rx_clk_i | 100.000(MHz) | 147.465(MHz) | 8 | TOP |
| 2 | serdes_pcs_tx_clk_i | 100.000(MHz) | 167.539(MHz) | 6 | TOP |
| 3 | clk_in_i | 100.000(MHz) | 856.531(MHz) | 1 | TOP |
| 4 | miim_hs_clk_i | 100.000(MHz) | 179.897(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.219 |
| Data Arrival Time | 7.130 |
| Data Required Time | 10.349 |
| From | u_ge_pcs/u_ge_rx/rx_config_5_s1 |
| To | u_ge_pcs/u_ge_an/c_state_0_s0 |
| Launch Clk | serdes_pcs_rx_clk_i[R] |
| Latch Clk | serdes_pcs_rx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 790 | serdes_pcs_rx_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 6 | u_ge_pcs/u_ge_rx/rx_config_5_s1/Q |
| 1.207 | 0.413 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n572_s0/I1 |
| 1.807 | 0.600 | tINS | RF | 1 | u_ge_pcs/u_ge_rx/n572_s0/COUT |
| 1.807 | 0.000 | tNET | FF | 2 | u_ge_pcs/u_ge_rx/n573_s0/CIN |
| 1.857 | 0.050 | tINS | FR | 1 | u_ge_pcs/u_ge_rx/n573_s0/COUT |
| 1.857 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n574_s0/CIN |
| 1.907 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n574_s0/COUT |
| 1.907 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n575_s0/CIN |
| 1.957 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n575_s0/COUT |
| 1.957 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n576_s0/CIN |
| 2.007 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 2.007 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 2.057 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 2.470 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 2.977 | 0.507 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 3.390 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 3.957 | 0.567 | tINS | RR | 2 | u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 4.370 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n_state_2_s3/I2 |
| 4.878 | 0.507 | tINS | RR | 2 | u_ge_pcs/u_ge_an/n_state_2_s3/F |
| 5.290 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n_state_0_s4/I2 |
| 5.798 | 0.507 | tINS | RR | 1 | u_ge_pcs/u_ge_an/n_state_0_s4/F |
| 6.210 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n_state_0_s2/I2 |
| 6.718 | 0.507 | tINS | RR | 1 | u_ge_pcs/u_ge_an/n_state_0_s2/F |
| 7.130 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/c_state_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 790 | serdes_pcs_rx_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/c_state_0_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | u_ge_pcs/u_ge_an/c_state_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.447, 51.321%; route: 2.887, 42.985%; tC2Q: 0.382, 5.694% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 3.338 |
| Data Arrival Time | 6.764 |
| Data Required Time | 10.101 |
| From | u_ge_pcs/u_ge_rx/rx_config_5_s1 |
| To | u_ge_pcs/u_ge_an/link_timer_cnt_0_s1 |
| Launch Clk | serdes_pcs_rx_clk_i[R] |
| Latch Clk | serdes_pcs_rx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 790 | serdes_pcs_rx_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 6 | u_ge_pcs/u_ge_rx/rx_config_5_s1/Q |
| 1.207 | 0.413 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n572_s0/I1 |
| 1.807 | 0.600 | tINS | RF | 1 | u_ge_pcs/u_ge_rx/n572_s0/COUT |
| 1.807 | 0.000 | tNET | FF | 2 | u_ge_pcs/u_ge_rx/n573_s0/CIN |
| 1.857 | 0.050 | tINS | FR | 1 | u_ge_pcs/u_ge_rx/n573_s0/COUT |
| 1.857 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n574_s0/CIN |
| 1.907 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n574_s0/COUT |
| 1.907 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n575_s0/CIN |
| 1.957 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n575_s0/COUT |
| 1.957 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n576_s0/CIN |
| 2.007 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 2.007 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 2.057 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 2.470 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 2.977 | 0.507 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 3.390 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 3.957 | 0.567 | tINS | RR | 2 | u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 4.370 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n276_s3/I3 |
| 4.659 | 0.289 | tINS | RR | 5 | u_ge_pcs/u_ge_an/n276_s3/F |
| 5.071 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n276_s2/I0 |
| 5.650 | 0.579 | tINS | RR | 19 | u_ge_pcs/u_ge_an/n276_s2/F |
| 6.062 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 6.351 | 0.289 | tINS | RR | 21 | u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 6.764 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_0_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 790 | serdes_pcs_rx_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_0_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.081, 48.515%; route: 2.887, 45.463%; tC2Q: 0.382, 6.022% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 3.338 |
| Data Arrival Time | 6.764 |
| Data Required Time | 10.101 |
| From | u_ge_pcs/u_ge_rx/rx_config_5_s1 |
| To | u_ge_pcs/u_ge_an/link_timer_cnt_1_s1 |
| Launch Clk | serdes_pcs_rx_clk_i[R] |
| Latch Clk | serdes_pcs_rx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 790 | serdes_pcs_rx_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 6 | u_ge_pcs/u_ge_rx/rx_config_5_s1/Q |
| 1.207 | 0.413 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n572_s0/I1 |
| 1.807 | 0.600 | tINS | RF | 1 | u_ge_pcs/u_ge_rx/n572_s0/COUT |
| 1.807 | 0.000 | tNET | FF | 2 | u_ge_pcs/u_ge_rx/n573_s0/CIN |
| 1.857 | 0.050 | tINS | FR | 1 | u_ge_pcs/u_ge_rx/n573_s0/COUT |
| 1.857 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n574_s0/CIN |
| 1.907 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n574_s0/COUT |
| 1.907 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n575_s0/CIN |
| 1.957 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n575_s0/COUT |
| 1.957 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n576_s0/CIN |
| 2.007 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 2.007 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 2.057 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 2.470 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 2.977 | 0.507 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 3.390 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 3.957 | 0.567 | tINS | RR | 2 | u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 4.370 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n276_s3/I3 |
| 4.659 | 0.289 | tINS | RR | 5 | u_ge_pcs/u_ge_an/n276_s3/F |
| 5.071 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n276_s2/I0 |
| 5.650 | 0.579 | tINS | RR | 19 | u_ge_pcs/u_ge_an/n276_s2/F |
| 6.062 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 6.351 | 0.289 | tINS | RR | 21 | u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 6.764 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_1_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 790 | serdes_pcs_rx_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_1_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.081, 48.515%; route: 2.887, 45.463%; tC2Q: 0.382, 6.022% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 3.338 |
| Data Arrival Time | 6.764 |
| Data Required Time | 10.101 |
| From | u_ge_pcs/u_ge_rx/rx_config_5_s1 |
| To | u_ge_pcs/u_ge_an/link_timer_cnt_2_s1 |
| Launch Clk | serdes_pcs_rx_clk_i[R] |
| Latch Clk | serdes_pcs_rx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 790 | serdes_pcs_rx_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 6 | u_ge_pcs/u_ge_rx/rx_config_5_s1/Q |
| 1.207 | 0.413 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n572_s0/I1 |
| 1.807 | 0.600 | tINS | RF | 1 | u_ge_pcs/u_ge_rx/n572_s0/COUT |
| 1.807 | 0.000 | tNET | FF | 2 | u_ge_pcs/u_ge_rx/n573_s0/CIN |
| 1.857 | 0.050 | tINS | FR | 1 | u_ge_pcs/u_ge_rx/n573_s0/COUT |
| 1.857 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n574_s0/CIN |
| 1.907 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n574_s0/COUT |
| 1.907 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n575_s0/CIN |
| 1.957 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n575_s0/COUT |
| 1.957 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n576_s0/CIN |
| 2.007 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 2.007 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 2.057 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 2.470 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 2.977 | 0.507 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 3.390 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 3.957 | 0.567 | tINS | RR | 2 | u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 4.370 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n276_s3/I3 |
| 4.659 | 0.289 | tINS | RR | 5 | u_ge_pcs/u_ge_an/n276_s3/F |
| 5.071 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n276_s2/I0 |
| 5.650 | 0.579 | tINS | RR | 19 | u_ge_pcs/u_ge_an/n276_s2/F |
| 6.062 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 6.351 | 0.289 | tINS | RR | 21 | u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 6.764 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_2_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 790 | serdes_pcs_rx_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_2_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.081, 48.515%; route: 2.887, 45.463%; tC2Q: 0.382, 6.022% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 3.338 |
| Data Arrival Time | 6.764 |
| Data Required Time | 10.101 |
| From | u_ge_pcs/u_ge_rx/rx_config_5_s1 |
| To | u_ge_pcs/u_ge_an/link_timer_cnt_3_s1 |
| Launch Clk | serdes_pcs_rx_clk_i[R] |
| Latch Clk | serdes_pcs_rx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 790 | serdes_pcs_rx_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 6 | u_ge_pcs/u_ge_rx/rx_config_5_s1/Q |
| 1.207 | 0.413 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n572_s0/I1 |
| 1.807 | 0.600 | tINS | RF | 1 | u_ge_pcs/u_ge_rx/n572_s0/COUT |
| 1.807 | 0.000 | tNET | FF | 2 | u_ge_pcs/u_ge_rx/n573_s0/CIN |
| 1.857 | 0.050 | tINS | FR | 1 | u_ge_pcs/u_ge_rx/n573_s0/COUT |
| 1.857 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n574_s0/CIN |
| 1.907 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n574_s0/COUT |
| 1.907 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n575_s0/CIN |
| 1.957 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n575_s0/COUT |
| 1.957 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n576_s0/CIN |
| 2.007 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 2.007 | 0.000 | tNET | RR | 2 | u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 2.057 | 0.050 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 2.470 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 2.977 | 0.507 | tINS | RR | 1 | u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 3.390 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 3.957 | 0.567 | tINS | RR | 2 | u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 4.370 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n276_s3/I3 |
| 4.659 | 0.289 | tINS | RR | 5 | u_ge_pcs/u_ge_an/n276_s3/F |
| 5.071 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/n276_s2/I0 |
| 5.650 | 0.579 | tINS | RR | 19 | u_ge_pcs/u_ge_an/n276_s2/F |
| 6.062 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 6.351 | 0.289 | tINS | RR | 21 | u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 6.764 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_3_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_rx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_rx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 790 | serdes_pcs_rx_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_3_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_ge_pcs/u_ge_an/link_timer_cnt_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.081, 48.515%; route: 2.887, 45.463%; tC2Q: 0.382, 6.022% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |