Timing Messages
| Report Title | Timing Analysis Report |
| Design File | E:\IP_Release\1G_Serial_Ethernet_Over_Serdes\191201\Gowin_1G_Serial_Ethernet_RefDesign\project\impl\gwsynthesis\fpga_project.vg |
| Physical Constraints File | E:\IP_Release\1G_Serial_Ethernet_Over_Serdes\191201\Gowin_1G_Serial_Ethernet_RefDesign\project\src\fpga_project.cst |
| Timing Constraint File | E:\IP_Release\1G_Serial_Ethernet_Over_Serdes\191201\Gowin_1G_Serial_Ethernet_RefDesign\project\src\fpga_project.sdc |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Dec 30 10:25:04 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 0.855V 0C ES |
| Hold Delay Model | Fast 0.945V 85C ES |
| Numbers of Paths Analyzed | 4561 |
| Numbers of Endpoints Analyzed | 6404 |
| Numbers of Falling Endpoints | 3 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|---|
| 1 | rx_mac_clk | Base | 8.000 | 125.000 | 0.000 | 4.000 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK | ||
| 2 | clk_in | Base | 19.048 | 52.499 | 0.000 | 9.524 | u_osc/OSCOUT | ||
| 3 | tck | Base | 50.000 | 20.000 | 0.000 | 25.000 | gw_gao_inst_0/tck_ibuf/I | ||
| 4 | tx_mac_clk | Base | 8.000 | 125.000 | 0.000 | 4.000 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | rx_mac_clk | 125.000(MHz) | 136.437(MHz) | 8 | TOP |
| 2 | clk_in | 52.499(MHz) | 777.077(MHz) | 1 | TOP |
| 3 | tck | 20.000(MHz) | 150.093(MHz) | 6 | TOP |
| 4 | tx_mac_clk | 125.000(MHz) | 173.780(MHz) | 6 | TOP |
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| rx_mac_clk | Setup | 0.000 | 0 |
| rx_mac_clk | Hold | 0.000 | 0 |
| clk_in | Setup | 0.000 | 0 |
| clk_in | Hold | 0.000 | 0 |
| tck | Setup | 0.000 | 0 |
| tck | Hold | 0.000 | 0 |
| tx_mac_clk | Setup | 0.000 | 0 |
| tx_mac_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.671 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_4_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.009 | 7.256 |
| 2 | 0.764 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.002 | 7.170 |
| 3 | 0.790 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.012 | 7.135 |
| 4 | 0.794 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_0_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.019 | 6.876 |
| 5 | 0.794 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_1_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.019 | 6.876 |
| 6 | 0.794 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_2_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.019 | 6.876 |
| 7 | 0.794 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_3_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.019 | 6.876 |
| 8 | 0.794 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_19_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.019 | 6.876 |
| 9 | 0.801 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.012 | 6.876 |
| 10 | 0.801 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.012 | 6.876 |
| 11 | 0.803 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_4_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.009 | 6.876 |
| 12 | 0.803 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_5_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.009 | 6.876 |
| 13 | 0.803 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_6_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.009 | 6.876 |
| 14 | 0.803 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_7_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.009 | 6.876 |
| 15 | 0.810 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.002 | 6.876 |
| 16 | 0.810 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.002 | 6.876 |
| 17 | 0.810 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_10_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.002 | 6.876 |
| 18 | 0.810 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.002 | 6.876 |
| 19 | 0.810 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_12_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.002 | 6.876 |
| 20 | 0.835 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.002 | 7.099 |
| 21 | 0.835 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.002 | 7.099 |
| 22 | 0.835 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.002 | 7.099 |
| 23 | 0.839 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_13_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.002 | 6.848 |
| 24 | 0.839 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_14_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.002 | 6.848 |
| 25 | 0.839 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_15_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.002 | 6.848 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.227 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[13] | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.013 | 0.251 |
| 2 | 0.248 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[9] | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | -0.001 | 0.286 |
| 3 | 0.248 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3] | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | -0.001 | 0.286 |
| 4 | 0.249 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[4] | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.002 | 0.284 |
| 5 | 0.271 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[12] | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.015 | 0.293 |
| 6 | 0.275 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg1_13_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_13_s0/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.222 |
| 7 | 0.275 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg2_2_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg3_2_s0/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.222 |
| 8 | 0.275 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg1_2_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg2_2_s0/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.222 |
| 9 | 0.275 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg1_0_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_0_s0/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.222 |
| 10 | 0.275 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg1_1_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_1_s0/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.222 |
| 11 | 0.275 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg1_40_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg2_40_s0/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.222 |
| 12 | 0.275 | u_mac_rx_model/rx_data_cnt_0_s3/Q | u_mac_rx_model/rx_data_cnt_0_s3/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 13 | 0.275 | u_mac_rx_model/rx_data_cnt_pause_1_s1/Q | u_mac_rx_model/rx_data_cnt_pause_1_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 14 | 0.275 | u_mac_rx_model/rx_data_cnt_pause_3_s1/Q | u_mac_rx_model/rx_data_cnt_pause_3_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 15 | 0.275 | u_mac_rx_model/rx_data_cnt_pause_9_s1/Q | u_mac_rx_model/rx_data_cnt_pause_9_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 16 | 0.275 | u_mac_rx_model/rx_data_cnt_pause_12_s1/Q | u_mac_rx_model/rx_data_cnt_pause_12_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 17 | 0.275 | u_mac_rx_model/rx_data_cnt_pause_13_s1/Q | u_mac_rx_model/rx_data_cnt_pause_13_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 18 | 0.275 | u_mac_rx_model/rx_data_cnt_2_s1/Q | u_mac_rx_model/rx_data_cnt_2_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 19 | 0.275 | u_mac_rx_model/rx_data_cnt_3_s1/Q | u_mac_rx_model/rx_data_cnt_3_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 20 | 0.275 | u_mac_rx_model/rx_data_cnt_15_s1/Q | u_mac_rx_model/rx_data_cnt_15_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 21 | 0.275 | u_mac_tx_model/tx_data_cnt_11_s3/Q | u_mac_tx_model/tx_data_cnt_11_s3/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 22 | 0.275 | u_mac_tx_model/tx_data_cnt_14_s3/Q | u_mac_tx_model/tx_data_cnt_14_s3/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 23 | 0.275 | u_mac_tx_model/tx_data_cnt_15_s1/Q | u_mac_tx_model/tx_data_cnt_15_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 24 | 0.275 | u_mac_tx_model/data_increase_7_s1/Q | u_mac_tx_model/data_increase_7_s1/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
| 25 | 0.275 | u_mac_tx_model/wait_cnt_1_s0/Q | u_mac_tx_model/wait_cnt_1_s0/D | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.300 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 1.261 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.412 | 2.804 |
| 2 | 1.261 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.412 | 2.804 |
| 3 | 1.453 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.403 | 2.602 |
| 4 | 1.453 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.403 | 2.602 |
| 5 | 1.453 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.403 | 2.602 |
| 6 | 1.606 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.408 | 2.454 |
| 7 | 1.606 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.408 | 2.454 |
| 8 | 1.606 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.408 | 2.454 |
| 9 | 1.606 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.408 | 2.454 |
| 10 | 1.661 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.401 | 2.392 |
| 11 | 1.661 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.401 | 2.392 |
| 12 | 1.663 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.403 | 2.392 |
| 13 | 3.443 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_3_s0/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.113 | 4.096 |
| 14 | 3.541 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_2_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.068 | 4.044 |
| 15 | 3.541 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_9_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.068 | 4.044 |
| 16 | 3.541 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_10_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.068 | 4.044 |
| 17 | 3.541 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_16_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.068 | 4.044 |
| 18 | 3.541 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_17_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.068 | 4.044 |
| 19 | 3.541 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_18_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.068 | 4.044 |
| 20 | 1.823 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.405 | 2.235 |
| 21 | 1.823 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.405 | 2.235 |
| 22 | 1.823 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR | rx_mac_clk:[F] | rx_mac_clk:[R] | 4.000 | -0.405 | 2.235 |
| 23 | 3.652 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_8_s0/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.106 | 3.895 |
| 24 | 3.652 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_er_err_o_s0/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.106 | 3.895 |
| 25 | 3.661 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_tmp_6_s0/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.096 | 3.895 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.392 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | -0.006 | 0.345 |
| 2 | 0.394 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_int_tmp_3_s0/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.002 | 0.339 |
| 3 | 0.401 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/sync_status_d2_s0/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.001 | 0.347 |
| 4 | 0.407 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_13_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.005 | 0.349 |
| 5 | 0.407 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_14_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.005 | 0.349 |
| 6 | 0.407 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_15_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.005 | 0.349 |
| 7 | 0.407 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.005 | 0.349 |
| 8 | 0.410 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_0_s3/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.006 | 0.351 |
| 9 | 0.410 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_1_s3/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.006 | 0.351 |
| 10 | 0.410 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_4_s3/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.006 | 0.351 |
| 11 | 0.411 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.005 | 0.353 |
| 12 | 0.411 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.005 | 0.353 |
| 13 | 0.411 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_10_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.005 | 0.353 |
| 14 | 0.411 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.005 | 0.353 |
| 15 | 0.411 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_12_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.005 | 0.353 |
| 16 | 0.412 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_17_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.010 | 0.349 |
| 17 | 0.414 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_9_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.361 |
| 18 | 0.414 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_10_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.361 |
| 19 | 0.414 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_12_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.000 | 0.361 |
| 20 | 0.415 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.009 | 0.353 |
| 21 | 0.415 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.009 | 0.353 |
| 22 | 0.417 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_latch_0_s3/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.002 | 0.363 |
| 23 | 0.417 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/clk_ena_s0/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.002 | 0.363 |
| 24 | 0.417 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_0_s0/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.002 | 0.363 |
| 25 | 0.417 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg2_6_s0/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.002 | 0.363 |
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 1.075 | 2.075 | 1.000 | High Pulse Width | rx_mac_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| 2 | 1.080 | 2.080 | 1.000 | High Pulse Width | rx_mac_clk | gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s |
| 3 | 1.160 | 2.160 | 1.000 | Low Pulse Width | rx_mac_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| 4 | 1.165 | 2.165 | 1.000 | Low Pulse Width | rx_mac_clk | gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s |
| 5 | 1.548 | 1.798 | 0.250 | High Pulse Width | tx_mac_clk | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_fabric_tx_vld_s0 |
| 6 | 1.591 | 1.841 | 0.250 | High Pulse Width | tx_mac_clk | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg2_4_s0 |
| 7 | 1.591 | 1.841 | 0.250 | High Pulse Width | tx_mac_clk | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_latch_12_s3 |
| 8 | 1.591 | 1.841 | 0.250 | High Pulse Width | tx_mac_clk | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/u_crc_gen/crc_reg_27_s1 |
| 9 | 1.591 | 1.841 | 0.250 | High Pulse Width | tx_mac_clk | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_19_s3 |
| 10 | 1.591 | 1.841 | 0.250 | High Pulse Width | tx_mac_clk | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_17_s3 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.671 |
| Data Arrival Time | 10.927 |
| Data Required Time | 11.597 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_4_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 10.471 | 0.630 | tNET | RR | 1 | R9C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n315_s2/I2 |
| 10.927 | 0.456 | tINS | RR | 1 | R9C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n315_s2/F |
| 10.927 | 0.000 | tNET | RR | 1 | R9C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_4_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.661 | 3.661 | tNET | RR | 1 | R9C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_4_s1/CLK |
| 11.597 | -0.064 | tSu | 1 | R9C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_4_s1 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.932, 40.413%; route: 3.941, 54.315%; tC2Q: 0.382, 5.271% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.661, 100.000% |
Path2
Path Summary:
| Slack | 0.764 |
| Data Arrival Time | 10.841 |
| Data Required Time | 11.605 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 10.262 | 0.421 | tNET | RR | 1 | R8C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n303_s2/I3 |
| 10.841 | 0.579 | tINS | RR | 1 | R8C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n303_s2/F |
| 10.841 | 0.000 | tNET | RR | 1 | R8C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.668 | 3.668 | tNET | RR | 1 | R8C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1/CLK |
| 11.605 | -0.064 | tSu | 1 | R8C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 3.055, 42.608%; route: 3.733, 52.057%; tC2Q: 0.382, 5.335% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.668, 100.000% |
Path3
Path Summary:
| Slack | 0.790 |
| Data Arrival Time | 10.806 |
| Data Required Time | 11.595 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 10.238 | 0.398 | tNET | RR | 1 | R8C143[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n301_s2/I3 |
| 10.806 | 0.567 | tINS | RR | 1 | R8C143[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n301_s2/F |
| 10.806 | 0.000 | tNET | RR | 1 | R8C143[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.659 | 3.659 | tNET | RR | 1 | R8C143[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1/CLK |
| 11.595 | -0.064 | tSu | 1 | R8C143[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1 |
Path Statistics:
| Clock Skew | -0.012 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 3.044, 42.659%; route: 3.709, 51.980%; tC2Q: 0.382, 5.361% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.659, 100.000% |
Path4
Path Summary:
| Slack | 0.794 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.341 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_0_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R9C143[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_0_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.652 | 3.652 | tNET | RR | 1 | R9C143[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_0_s1/CLK |
| 11.341 | -0.311 | tSu | 1 | R9C143[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_0_s1 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.652, 100.000% |
Path5
Path Summary:
| Slack | 0.794 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.341 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_1_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R9C143[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_1_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.652 | 3.652 | tNET | RR | 1 | R9C143[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_1_s1/CLK |
| 11.341 | -0.311 | tSu | 1 | R9C143[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_1_s1 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.652, 100.000% |
Path6
Path Summary:
| Slack | 0.794 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.341 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_2_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R9C143[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_2_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.652 | 3.652 | tNET | RR | 1 | R9C143[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_2_s1/CLK |
| 11.341 | -0.311 | tSu | 1 | R9C143[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_2_s1 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.652, 100.000% |
Path7
Path Summary:
| Slack | 0.794 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.341 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_3_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R9C143[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_3_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.652 | 3.652 | tNET | RR | 1 | R9C143[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_3_s1/CLK |
| 11.341 | -0.311 | tSu | 1 | R9C143[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_3_s1 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.652, 100.000% |
Path8
Path Summary:
| Slack | 0.794 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.341 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_19_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R9C143[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_19_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.652 | 3.652 | tNET | RR | 1 | R9C143[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_19_s1/CLK |
| 11.341 | -0.311 | tSu | 1 | R9C143[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_19_s1 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.652, 100.000% |
Path9
Path Summary:
| Slack | 0.801 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.348 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R8C143[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.659 | 3.659 | tNET | RR | 1 | R8C143[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1/CLK |
| 11.348 | -0.311 | tSu | 1 | R8C143[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1 |
Path Statistics:
| Clock Skew | -0.012 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.659, 100.000% |
Path10
Path Summary:
| Slack | 0.801 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.348 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R8C143[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.659 | 3.659 | tNET | RR | 1 | R8C143[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s1/CLK |
| 11.348 | -0.311 | tSu | 1 | R8C143[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s1 |
Path Statistics:
| Clock Skew | -0.012 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.659, 100.000% |
Path11
Path Summary:
| Slack | 0.803 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.350 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_4_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R9C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_4_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.661 | 3.661 | tNET | RR | 1 | R9C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_4_s1/CLK |
| 11.350 | -0.311 | tSu | 1 | R9C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_4_s1 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.661, 100.000% |
Path12
Path Summary:
| Slack | 0.803 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.350 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_5_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R9C144[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_5_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.661 | 3.661 | tNET | RR | 1 | R9C144[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_5_s1/CLK |
| 11.350 | -0.311 | tSu | 1 | R9C144[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_5_s1 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.661, 100.000% |
Path13
Path Summary:
| Slack | 0.803 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.350 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_6_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R9C144[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_6_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.661 | 3.661 | tNET | RR | 1 | R9C144[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_6_s1/CLK |
| 11.350 | -0.311 | tSu | 1 | R9C144[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_6_s1 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.661, 100.000% |
Path14
Path Summary:
| Slack | 0.803 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.350 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_7_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R9C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_7_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.661 | 3.661 | tNET | RR | 1 | R9C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_7_s1/CLK |
| 11.350 | -0.311 | tSu | 1 | R9C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_7_s1 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.661, 100.000% |
Path15
Path Summary:
| Slack | 0.810 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.357 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R8C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.668 | 3.668 | tNET | RR | 1 | R8C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1/CLK |
| 11.357 | -0.311 | tSu | 1 | R8C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.668, 100.000% |
Path16
Path Summary:
| Slack | 0.810 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.357 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R8C144[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.668 | 3.668 | tNET | RR | 1 | R8C144[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1/CLK |
| 11.357 | -0.311 | tSu | 1 | R8C144[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.668, 100.000% |
Path17
Path Summary:
| Slack | 0.810 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.357 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_10_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R8C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_10_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.668 | 3.668 | tNET | RR | 1 | R8C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_10_s1/CLK |
| 11.357 | -0.311 | tSu | 1 | R8C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_10_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.668, 100.000% |
Path18
Path Summary:
| Slack | 0.810 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.357 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R8C144[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.668 | 3.668 | tNET | RR | 1 | R8C144[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1/CLK |
| 11.357 | -0.311 | tSu | 1 | R8C144[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.668, 100.000% |
Path19
Path Summary:
| Slack | 0.810 |
| Data Arrival Time | 10.547 |
| Data Required Time | 11.357 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_12_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.547 | 0.399 | tNET | RR | 1 | R8C144[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_12_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.668 | 3.668 | tNET | RR | 1 | R8C144[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_12_s1/CLK |
| 11.357 | -0.311 | tSu | 1 | R8C144[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_12_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.211%; route: 3.729, 54.227%; tC2Q: 0.382, 5.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.668, 100.000% |
Path20
Path Summary:
| Slack | 0.835 |
| Data Arrival Time | 10.769 |
| Data Required Time | 11.605 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 10.262 | 0.421 | tNET | RR | 1 | R8C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n311_s5/I3 |
| 10.769 | 0.507 | tINS | RR | 1 | R8C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n311_s5/F |
| 10.769 | 0.000 | tNET | RR | 1 | R8C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.668 | 3.668 | tNET | RR | 1 | R8C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1/CLK |
| 11.605 | -0.064 | tSu | 1 | R8C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.984, 42.032%; route: 3.733, 52.580%; tC2Q: 0.382, 5.388% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.668, 100.000% |
Path21
Path Summary:
| Slack | 0.835 |
| Data Arrival Time | 10.769 |
| Data Required Time | 11.605 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 10.262 | 0.421 | tNET | RR | 1 | R8C144[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n310_s2/I3 |
| 10.769 | 0.507 | tINS | RR | 1 | R8C144[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n310_s2/F |
| 10.769 | 0.000 | tNET | RR | 1 | R8C144[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.668 | 3.668 | tNET | RR | 1 | R8C144[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1/CLK |
| 11.605 | -0.064 | tSu | 1 | R8C144[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.984, 42.032%; route: 3.733, 52.580%; tC2Q: 0.382, 5.388% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.668, 100.000% |
Path22
Path Summary:
| Slack | 0.835 |
| Data Arrival Time | 10.769 |
| Data Required Time | 11.605 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 10.262 | 0.421 | tNET | RR | 1 | R8C144[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n308_s2/I3 |
| 10.769 | 0.507 | tINS | RR | 1 | R8C144[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n308_s2/F |
| 10.769 | 0.000 | tNET | RR | 1 | R8C144[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.668 | 3.668 | tNET | RR | 1 | R8C144[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1/CLK |
| 11.605 | -0.064 | tSu | 1 | R8C144[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.984, 42.032%; route: 3.733, 52.580%; tC2Q: 0.382, 5.388% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.668, 100.000% |
Path23
Path Summary:
| Slack | 0.839 |
| Data Arrival Time | 10.518 |
| Data Required Time | 11.357 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_13_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.518 | 0.370 | tNET | RR | 1 | R8C142[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_13_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.668 | 3.668 | tNET | RR | 1 | R8C142[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_13_s1/CLK |
| 11.357 | -0.311 | tSu | 1 | R8C142[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_13_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.380%; route: 3.700, 54.034%; tC2Q: 0.382, 5.586% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.668, 100.000% |
Path24
Path Summary:
| Slack | 0.839 |
| Data Arrival Time | 10.518 |
| Data Required Time | 11.357 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_14_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.518 | 0.370 | tNET | RR | 1 | R8C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_14_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.668 | 3.668 | tNET | RR | 1 | R8C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_14_s1/CLK |
| 11.357 | -0.311 | tSu | 1 | R8C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_14_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.380%; route: 3.700, 54.034%; tC2Q: 0.382, 5.586% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.668, 100.000% |
Path25
Path Summary:
| Slack | 0.839 |
| Data Arrival Time | 10.518 |
| Data Required Time | 11.357 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_15_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.671 | 3.671 | tNET | RR | 1 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/CLK |
| 4.053 | 0.382 | tC2Q | RR | 6 | R9C133[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_12_s1/Q |
| 5.231 | 1.178 | tNET | RR | 2 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/I1 |
| 5.831 | 0.600 | tINS | RF | 1 | R9C131[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n576_s0/COUT |
| 5.831 | 0.000 | tNET | FF | 2 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/CIN |
| 5.881 | 0.050 | tINS | FR | 1 | R9C131[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n577_s0/COUT |
| 6.689 | 0.809 | tNET | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2 |
| 7.197 | 0.507 | tINS | RR | 1 | R11C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F |
| 7.812 | 0.615 | tNET | RR | 1 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/I1 |
| 8.268 | 0.456 | tINS | RR | 2 | R11C140[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n_state_2_s5/F |
| 8.443 | 0.175 | tNET | RR | 1 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/I3 |
| 9.017 | 0.574 | tINS | RR | 5 | R11C141[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s3/F |
| 9.552 | 0.535 | tNET | RR | 1 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/I0 |
| 9.841 | 0.289 | tINS | RR | 19 | R9C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/n276_s2/F |
| 9.859 | 0.019 | tNET | RR | 1 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/I3 |
| 10.148 | 0.289 | tINS | RR | 21 | R9C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s5/F |
| 10.518 | 0.370 | tNET | RR | 1 | R8C142[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_15_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.668 | 3.668 | tNET | RR | 1 | R8C142[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_15_s1/CLK |
| 11.357 | -0.311 | tSu | 1 | R8C142[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_15_s1 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 8.000 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.671, 100.000% |
| Arrival Data Path Delay | cell: 2.765, 40.380%; route: 3.700, 54.034%; tC2Q: 0.382, 5.586% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.668, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.227 |
| Data Arrival Time | 1.670 |
| Data Required Time | 1.443 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.419 | 1.419 | tNET | RR | 1 | R24C152[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
| 1.563 | 0.144 | tC2Q | RR | 3 | R24C152[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q |
| 1.670 | 0.107 | tNET | RR | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[13] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.406 | 1.406 | tNET | RR | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
| 1.443 | 0.037 | tHld | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
| Clock Skew | -0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.419, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.107, 42.629%; tC2Q: 0.144, 57.371% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.406, 100.000% |
Path2
Path Summary:
| Slack | 0.248 |
| Data Arrival Time | 1.691 |
| Data Required Time | 1.443 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.405 | 1.405 | tNET | RR | 1 | R16C149[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/CLK |
| 1.549 | 0.144 | tC2Q | RR | 1 | R16C149[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q |
| 1.691 | 0.142 | tNET | RR | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[9] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.406 | 1.406 | tNET | RR | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
| 1.443 | 0.037 | tHld | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
| Clock Skew | 0.001 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.405, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.142, 49.650%; tC2Q: 0.144, 50.350% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.406, 100.000% |
Path3
Path Summary:
| Slack | 0.248 |
| Data Arrival Time | 1.691 |
| Data Required Time | 1.443 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.405 | 1.405 | tNET | RR | 1 | R16C149[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/CLK |
| 1.549 | 0.144 | tC2Q | RR | 1 | R16C149[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q |
| 1.691 | 0.142 | tNET | RR | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.406 | 1.406 | tNET | RR | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
| 1.443 | 0.037 | tHld | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
| Clock Skew | 0.001 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.405, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.142, 49.650%; tC2Q: 0.144, 50.350% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.406, 100.000% |
Path4
Path Summary:
| Slack | 0.249 |
| Data Arrival Time | 1.692 |
| Data Required Time | 1.443 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.408 | 1.408 | tNET | RR | 1 | R18C149[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/CLK |
| 1.552 | 0.144 | tC2Q | RR | 1 | R18C149[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q |
| 1.692 | 0.140 | tNET | RR | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.406 | 1.406 | tNET | RR | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
| 1.443 | 0.037 | tHld | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
| Clock Skew | -0.002 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.408, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.140, 49.296%; tC2Q: 0.144, 50.704% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.406, 100.000% |
Path5
Path Summary:
| Slack | 0.271 |
| Data Arrival Time | 1.714 |
| Data Required Time | 1.443 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.421 | 1.421 | tNET | RR | 1 | R23C152[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
| 1.565 | 0.144 | tC2Q | RR | 4 | R23C152[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q |
| 1.714 | 0.149 | tNET | RR | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[12] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.406 | 1.406 | tNET | RR | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
| 1.443 | 0.037 | tHld | 1 | BSRAM_R28[29][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
| Clock Skew | -0.015 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.421, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.149, 50.853%; tC2Q: 0.144, 49.147% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.406, 100.000% |
Path6
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.671 |
| Data Required Time | 1.396 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg1_13_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_13_s0 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.449 | 1.449 | tNET | RR | 1 | R17C134[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg1_13_s0/CLK |
| 1.592 | 0.144 | tC2Q | RR | 1 | R17C134[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg1_13_s0/Q |
| 1.670 | 0.078 | tNET | RR | 1 | R17C134[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_13_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.449 | 1.449 | tNET | RR | 1 | R17C134[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_13_s0/CLK |
| 1.396 | -0.053 | tHld | 1 | R17C134[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.449, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.449, 100.000% |
Path7
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.672 |
| Data Required Time | 1.397 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg2_2_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg3_2_s0 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.450 | 1.450 | tNET | RR | 1 | R18C134[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg2_2_s0/CLK |
| 1.594 | 0.144 | tC2Q | RR | 1 | R18C134[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg2_2_s0/Q |
| 1.672 | 0.078 | tNET | RR | 1 | R18C134[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg3_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.450 | 1.450 | tNET | RR | 1 | R18C134[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg3_2_s0/CLK |
| 1.397 | -0.053 | tHld | 1 | R18C134[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg3_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.450, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.450, 100.000% |
Path8
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.672 |
| Data Required Time | 1.397 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg1_2_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg2_2_s0 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.450 | 1.450 | tNET | RR | 1 | R18C134[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg1_2_s0/CLK |
| 1.594 | 0.144 | tC2Q | RR | 1 | R18C134[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg1_2_s0/Q |
| 1.672 | 0.078 | tNET | RR | 1 | R18C134[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg2_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.450 | 1.450 | tNET | RR | 1 | R18C134[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg2_2_s0/CLK |
| 1.397 | -0.053 | tHld | 1 | R18C134[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg2_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.450, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.450, 100.000% |
Path9
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.663 |
| Data Required Time | 1.388 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg1_0_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_0_s0 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.441 | 1.441 | tNET | RR | 1 | R17C136[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg1_0_s0/CLK |
| 1.585 | 0.144 | tC2Q | RR | 1 | R17C136[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg1_0_s0/Q |
| 1.663 | 0.078 | tNET | RR | 1 | R17C136[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.441 | 1.441 | tNET | RR | 1 | R17C136[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_0_s0/CLK |
| 1.388 | -0.053 | tHld | 1 | R17C136[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.441, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.441, 100.000% |
Path10
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.665 |
| Data Required Time | 1.390 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg1_1_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_1_s0 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.443 | 1.443 | tNET | RR | 1 | R16C139[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg1_1_s0/CLK |
| 1.587 | 0.144 | tC2Q | RR | 1 | R16C139[3][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg1_1_s0/Q |
| 1.665 | 0.078 | tNET | RR | 1 | R16C139[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.443 | 1.443 | tNET | RR | 1 | R16C139[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_1_s0/CLK |
| 1.390 | -0.053 | tHld | 1 | R16C139[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.443, 100.000% |
Path11
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.688 |
| Data Required Time | 1.413 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg1_40_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg2_40_s0 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.466 | 1.466 | tNET | RR | 1 | R21C135[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg1_40_s0/CLK |
| 1.610 | 0.144 | tC2Q | RR | 1 | R21C135[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg1_40_s0/Q |
| 1.688 | 0.078 | tNET | RR | 1 | R21C135[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg2_40_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.466 | 1.466 | tNET | RR | 1 | R21C135[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg2_40_s0/CLK |
| 1.413 | -0.053 | tHld | 1 | R21C135[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg2_40_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.466, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.466, 100.000% |
Path12
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.700 |
| Data Required Time | 1.425 |
| From | u_mac_rx_model/rx_data_cnt_0_s3 |
| To | u_mac_rx_model/rx_data_cnt_0_s3 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.400 | 1.400 | tNET | RR | 1 | R14C149[0][A] | u_mac_rx_model/rx_data_cnt_0_s3/CLK |
| 1.541 | 0.141 | tC2Q | RF | 5 | R14C149[0][A] | u_mac_rx_model/rx_data_cnt_0_s3/Q |
| 1.547 | 0.006 | tNET | FF | 1 | R14C149[0][A] | u_mac_rx_model/n440_s5/I2 |
| 1.700 | 0.153 | tINS | FF | 1 | R14C149[0][A] | u_mac_rx_model/n440_s5/F |
| 1.700 | 0.000 | tNET | FF | 1 | R14C149[0][A] | u_mac_rx_model/rx_data_cnt_0_s3/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.400 | 1.400 | tNET | RR | 1 | R14C149[0][A] | u_mac_rx_model/rx_data_cnt_0_s3/CLK |
| 1.425 | 0.025 | tHld | 1 | R14C149[0][A] | u_mac_rx_model/rx_data_cnt_0_s3 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.400, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.400, 100.000% |
Path13
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.692 |
| Data Required Time | 1.417 |
| From | u_mac_rx_model/rx_data_cnt_pause_1_s1 |
| To | u_mac_rx_model/rx_data_cnt_pause_1_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.392 | 1.392 | tNET | RR | 1 | R13C148[1][A] | u_mac_rx_model/rx_data_cnt_pause_1_s1/CLK |
| 1.533 | 0.141 | tC2Q | RF | 5 | R13C148[1][A] | u_mac_rx_model/rx_data_cnt_pause_1_s1/Q |
| 1.539 | 0.006 | tNET | FF | 1 | R13C148[1][A] | u_mac_rx_model/n1026_s3/I2 |
| 1.692 | 0.153 | tINS | FF | 1 | R13C148[1][A] | u_mac_rx_model/n1026_s3/F |
| 1.692 | 0.000 | tNET | FF | 1 | R13C148[1][A] | u_mac_rx_model/rx_data_cnt_pause_1_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.392 | 1.392 | tNET | RR | 1 | R13C148[1][A] | u_mac_rx_model/rx_data_cnt_pause_1_s1/CLK |
| 1.417 | 0.025 | tHld | 1 | R13C148[1][A] | u_mac_rx_model/rx_data_cnt_pause_1_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.392, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.392, 100.000% |
Path14
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.692 |
| Data Required Time | 1.417 |
| From | u_mac_rx_model/rx_data_cnt_pause_3_s1 |
| To | u_mac_rx_model/rx_data_cnt_pause_3_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.392 | 1.392 | tNET | RR | 1 | R13C148[0][A] | u_mac_rx_model/rx_data_cnt_pause_3_s1/CLK |
| 1.533 | 0.141 | tC2Q | RF | 3 | R13C148[0][A] | u_mac_rx_model/rx_data_cnt_pause_3_s1/Q |
| 1.539 | 0.006 | tNET | FF | 1 | R13C148[0][A] | u_mac_rx_model/n1024_s2/I3 |
| 1.692 | 0.153 | tINS | FF | 1 | R13C148[0][A] | u_mac_rx_model/n1024_s2/F |
| 1.692 | 0.000 | tNET | FF | 1 | R13C148[0][A] | u_mac_rx_model/rx_data_cnt_pause_3_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.392 | 1.392 | tNET | RR | 1 | R13C148[0][A] | u_mac_rx_model/rx_data_cnt_pause_3_s1/CLK |
| 1.417 | 0.025 | tHld | 1 | R13C148[0][A] | u_mac_rx_model/rx_data_cnt_pause_3_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.392, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.392, 100.000% |
Path15
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.696 |
| Data Required Time | 1.421 |
| From | u_mac_rx_model/rx_data_cnt_pause_9_s1 |
| To | u_mac_rx_model/rx_data_cnt_pause_9_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.396 | 1.396 | tNET | RR | 1 | R14C148[0][A] | u_mac_rx_model/rx_data_cnt_pause_9_s1/CLK |
| 1.537 | 0.141 | tC2Q | RF | 5 | R14C148[0][A] | u_mac_rx_model/rx_data_cnt_pause_9_s1/Q |
| 1.543 | 0.006 | tNET | FF | 1 | R14C148[0][A] | u_mac_rx_model/n1018_s2/I3 |
| 1.696 | 0.153 | tINS | FF | 1 | R14C148[0][A] | u_mac_rx_model/n1018_s2/F |
| 1.696 | 0.000 | tNET | FF | 1 | R14C148[0][A] | u_mac_rx_model/rx_data_cnt_pause_9_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.396 | 1.396 | tNET | RR | 1 | R14C148[0][A] | u_mac_rx_model/rx_data_cnt_pause_9_s1/CLK |
| 1.421 | 0.025 | tHld | 1 | R14C148[0][A] | u_mac_rx_model/rx_data_cnt_pause_9_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.396, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.396, 100.000% |
Path16
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.696 |
| Data Required Time | 1.421 |
| From | u_mac_rx_model/rx_data_cnt_pause_12_s1 |
| To | u_mac_rx_model/rx_data_cnt_pause_12_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.396 | 1.396 | tNET | RR | 1 | R14C148[1][A] | u_mac_rx_model/rx_data_cnt_pause_12_s1/CLK |
| 1.537 | 0.141 | tC2Q | RF | 3 | R14C148[1][A] | u_mac_rx_model/rx_data_cnt_pause_12_s1/Q |
| 1.543 | 0.006 | tNET | FF | 1 | R14C148[1][A] | u_mac_rx_model/n1015_s2/I3 |
| 1.696 | 0.153 | tINS | FF | 1 | R14C148[1][A] | u_mac_rx_model/n1015_s2/F |
| 1.696 | 0.000 | tNET | FF | 1 | R14C148[1][A] | u_mac_rx_model/rx_data_cnt_pause_12_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.396 | 1.396 | tNET | RR | 1 | R14C148[1][A] | u_mac_rx_model/rx_data_cnt_pause_12_s1/CLK |
| 1.421 | 0.025 | tHld | 1 | R14C148[1][A] | u_mac_rx_model/rx_data_cnt_pause_12_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.396, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.396, 100.000% |
Path17
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.692 |
| Data Required Time | 1.417 |
| From | u_mac_rx_model/rx_data_cnt_pause_13_s1 |
| To | u_mac_rx_model/rx_data_cnt_pause_13_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.392 | 1.392 | tNET | RR | 1 | R14C147[1][A] | u_mac_rx_model/rx_data_cnt_pause_13_s1/CLK |
| 1.533 | 0.141 | tC2Q | RF | 4 | R14C147[1][A] | u_mac_rx_model/rx_data_cnt_pause_13_s1/Q |
| 1.539 | 0.006 | tNET | FF | 1 | R14C147[1][A] | u_mac_rx_model/n1014_s6/I2 |
| 1.692 | 0.153 | tINS | FF | 1 | R14C147[1][A] | u_mac_rx_model/n1014_s6/F |
| 1.692 | 0.000 | tNET | FF | 1 | R14C147[1][A] | u_mac_rx_model/rx_data_cnt_pause_13_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.392 | 1.392 | tNET | RR | 1 | R14C147[1][A] | u_mac_rx_model/rx_data_cnt_pause_13_s1/CLK |
| 1.417 | 0.025 | tHld | 1 | R14C147[1][A] | u_mac_rx_model/rx_data_cnt_pause_13_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.392, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.392, 100.000% |
Path18
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.696 |
| Data Required Time | 1.421 |
| From | u_mac_rx_model/rx_data_cnt_2_s1 |
| To | u_mac_rx_model/rx_data_cnt_2_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.396 | 1.396 | tNET | RR | 1 | R14C152[0][A] | u_mac_rx_model/rx_data_cnt_2_s1/CLK |
| 1.537 | 0.141 | tC2Q | RF | 4 | R14C152[0][A] | u_mac_rx_model/rx_data_cnt_2_s1/Q |
| 1.543 | 0.006 | tNET | FF | 1 | R14C152[0][A] | u_mac_rx_model/n438_s2/I3 |
| 1.696 | 0.153 | tINS | FF | 1 | R14C152[0][A] | u_mac_rx_model/n438_s2/F |
| 1.696 | 0.000 | tNET | FF | 1 | R14C152[0][A] | u_mac_rx_model/rx_data_cnt_2_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.396 | 1.396 | tNET | RR | 1 | R14C152[0][A] | u_mac_rx_model/rx_data_cnt_2_s1/CLK |
| 1.421 | 0.025 | tHld | 1 | R14C152[0][A] | u_mac_rx_model/rx_data_cnt_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.396, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.396, 100.000% |
Path19
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.696 |
| Data Required Time | 1.421 |
| From | u_mac_rx_model/rx_data_cnt_3_s1 |
| To | u_mac_rx_model/rx_data_cnt_3_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.396 | 1.396 | tNET | RR | 1 | R14C152[1][A] | u_mac_rx_model/rx_data_cnt_3_s1/CLK |
| 1.537 | 0.141 | tC2Q | RF | 3 | R14C152[1][A] | u_mac_rx_model/rx_data_cnt_3_s1/Q |
| 1.543 | 0.006 | tNET | FF | 1 | R14C152[1][A] | u_mac_rx_model/n437_s2/I3 |
| 1.696 | 0.153 | tINS | FF | 1 | R14C152[1][A] | u_mac_rx_model/n437_s2/F |
| 1.696 | 0.000 | tNET | FF | 1 | R14C152[1][A] | u_mac_rx_model/rx_data_cnt_3_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.396 | 1.396 | tNET | RR | 1 | R14C152[1][A] | u_mac_rx_model/rx_data_cnt_3_s1/CLK |
| 1.421 | 0.025 | tHld | 1 | R14C152[1][A] | u_mac_rx_model/rx_data_cnt_3_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.396, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.396, 100.000% |
Path20
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.696 |
| Data Required Time | 1.421 |
| From | u_mac_rx_model/rx_data_cnt_15_s1 |
| To | u_mac_rx_model/rx_data_cnt_15_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.396 | 1.396 | tNET | RR | 1 | R13C153[1][A] | u_mac_rx_model/rx_data_cnt_15_s1/CLK |
| 1.537 | 0.141 | tC2Q | RF | 2 | R13C153[1][A] | u_mac_rx_model/rx_data_cnt_15_s1/Q |
| 1.543 | 0.006 | tNET | FF | 1 | R13C153[1][A] | u_mac_rx_model/n425_s2/I3 |
| 1.696 | 0.153 | tINS | FF | 1 | R13C153[1][A] | u_mac_rx_model/n425_s2/F |
| 1.696 | 0.000 | tNET | FF | 1 | R13C153[1][A] | u_mac_rx_model/rx_data_cnt_15_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.396 | 1.396 | tNET | RR | 1 | R13C153[1][A] | u_mac_rx_model/rx_data_cnt_15_s1/CLK |
| 1.421 | 0.025 | tHld | 1 | R13C153[1][A] | u_mac_rx_model/rx_data_cnt_15_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.396, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.396, 100.000% |
Path21
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.746 |
| Data Required Time | 1.471 |
| From | u_mac_tx_model/tx_data_cnt_11_s3 |
| To | u_mac_tx_model/tx_data_cnt_11_s3 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.446 | 1.446 | tNET | RR | 1 | R15C138[0][A] | u_mac_tx_model/tx_data_cnt_11_s3/CLK |
| 1.587 | 0.141 | tC2Q | RF | 5 | R15C138[0][A] | u_mac_tx_model/tx_data_cnt_11_s3/Q |
| 1.593 | 0.006 | tNET | FF | 1 | R15C138[0][A] | u_mac_tx_model/n646_s5/I2 |
| 1.746 | 0.153 | tINS | FF | 1 | R15C138[0][A] | u_mac_tx_model/n646_s5/F |
| 1.746 | 0.000 | tNET | FF | 1 | R15C138[0][A] | u_mac_tx_model/tx_data_cnt_11_s3/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.446 | 1.446 | tNET | RR | 1 | R15C138[0][A] | u_mac_tx_model/tx_data_cnt_11_s3/CLK |
| 1.471 | 0.025 | tHld | 1 | R15C138[0][A] | u_mac_tx_model/tx_data_cnt_11_s3 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.446, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.446, 100.000% |
Path22
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.742 |
| Data Required Time | 1.467 |
| From | u_mac_tx_model/tx_data_cnt_14_s3 |
| To | u_mac_tx_model/tx_data_cnt_14_s3 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R14C138[1][A] | u_mac_tx_model/tx_data_cnt_14_s3/CLK |
| 1.583 | 0.141 | tC2Q | RF | 3 | R14C138[1][A] | u_mac_tx_model/tx_data_cnt_14_s3/Q |
| 1.589 | 0.006 | tNET | FF | 1 | R14C138[1][A] | u_mac_tx_model/n643_s6/I2 |
| 1.742 | 0.153 | tINS | FF | 1 | R14C138[1][A] | u_mac_tx_model/n643_s6/F |
| 1.742 | 0.000 | tNET | FF | 1 | R14C138[1][A] | u_mac_tx_model/tx_data_cnt_14_s3/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R14C138[1][A] | u_mac_tx_model/tx_data_cnt_14_s3/CLK |
| 1.467 | 0.025 | tHld | 1 | R14C138[1][A] | u_mac_tx_model/tx_data_cnt_14_s3 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
Path23
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.742 |
| Data Required Time | 1.467 |
| From | u_mac_tx_model/tx_data_cnt_15_s1 |
| To | u_mac_tx_model/tx_data_cnt_15_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R14C138[0][A] | u_mac_tx_model/tx_data_cnt_15_s1/CLK |
| 1.583 | 0.141 | tC2Q | RF | 2 | R14C138[0][A] | u_mac_tx_model/tx_data_cnt_15_s1/Q |
| 1.589 | 0.006 | tNET | FF | 1 | R14C138[0][A] | u_mac_tx_model/n642_s2/I3 |
| 1.742 | 0.153 | tINS | FF | 1 | R14C138[0][A] | u_mac_tx_model/n642_s2/F |
| 1.742 | 0.000 | tNET | FF | 1 | R14C138[0][A] | u_mac_tx_model/tx_data_cnt_15_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R14C138[0][A] | u_mac_tx_model/tx_data_cnt_15_s1/CLK |
| 1.467 | 0.025 | tHld | 1 | R14C138[0][A] | u_mac_tx_model/tx_data_cnt_15_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
Path24
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.730 |
| Data Required Time | 1.455 |
| From | u_mac_tx_model/data_increase_7_s1 |
| To | u_mac_tx_model/data_increase_7_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.430 | 1.430 | tNET | RR | 1 | R13C140[0][A] | u_mac_tx_model/data_increase_7_s1/CLK |
| 1.571 | 0.141 | tC2Q | RF | 2 | R13C140[0][A] | u_mac_tx_model/data_increase_7_s1/Q |
| 1.577 | 0.006 | tNET | FF | 1 | R13C140[0][A] | u_mac_tx_model/n595_s1/I3 |
| 1.730 | 0.153 | tINS | FF | 1 | R13C140[0][A] | u_mac_tx_model/n595_s1/F |
| 1.730 | 0.000 | tNET | FF | 1 | R13C140[0][A] | u_mac_tx_model/data_increase_7_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.430 | 1.430 | tNET | RR | 1 | R13C140[0][A] | u_mac_tx_model/data_increase_7_s1/CLK |
| 1.455 | 0.025 | tHld | 1 | R13C140[0][A] | u_mac_tx_model/data_increase_7_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.430, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.430, 100.000% |
Path25
Path Summary:
| Slack | 0.275 |
| Data Arrival Time | 1.738 |
| Data Required Time | 1.463 |
| From | u_mac_tx_model/wait_cnt_1_s0 |
| To | u_mac_tx_model/wait_cnt_1_s0 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.438 | 1.438 | tNET | RR | 1 | R14C141[0][A] | u_mac_tx_model/wait_cnt_1_s0/CLK |
| 1.579 | 0.141 | tC2Q | RF | 4 | R14C141[0][A] | u_mac_tx_model/wait_cnt_1_s0/Q |
| 1.585 | 0.006 | tNET | FF | 1 | R14C141[0][A] | u_mac_tx_model/n91_s3/I1 |
| 1.738 | 0.153 | tINS | FF | 1 | R14C141[0][A] | u_mac_tx_model/n91_s3/F |
| 1.738 | 0.000 | tNET | FF | 1 | R14C141[0][A] | u_mac_tx_model/wait_cnt_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.438 | 1.438 | tNET | RR | 1 | R14C141[0][A] | u_mac_tx_model/wait_cnt_1_s0/CLK |
| 1.463 | 0.025 | tHld | 1 | R14C141[0][A] | u_mac_tx_model/wait_cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.438, 100.000% |
| Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.438, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 1.261 |
| Data Arrival Time | 10.012 |
| Data Required Time | 11.273 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 10.012 | 2.361 | tNET | FF | 1 | R24C153[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.620 | 3.620 | tNET | RR | 1 | R24C153[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
| 11.273 | -0.347 | tSu | 1 | R24C153[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
| Clock Skew | 0.412 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.361, 84.218%; tC2Q: 0.442, 15.782% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.620, 100.000% |
Path2
Path Summary:
| Slack | 1.261 |
| Data Arrival Time | 10.012 |
| Data Required Time | 11.273 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 10.012 | 2.361 | tNET | FF | 1 | R24C153[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.620 | 3.620 | tNET | RR | 1 | R24C153[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
| 11.273 | -0.347 | tSu | 1 | R24C153[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
| Clock Skew | 0.412 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.361, 84.218%; tC2Q: 0.442, 15.782% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.620, 100.000% |
Path3
Path Summary:
| Slack | 1.453 |
| Data Arrival Time | 9.811 |
| Data Required Time | 11.263 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 9.811 | 2.160 | tNET | FF | 1 | R24C152[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.611 | 3.611 | tNET | RR | 1 | R24C152[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
| 11.263 | -0.347 | tSu | 1 | R24C152[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
| Clock Skew | 0.403 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.160, 82.997%; tC2Q: 0.442, 17.003% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.611, 100.000% |
Path4
Path Summary:
| Slack | 1.453 |
| Data Arrival Time | 9.811 |
| Data Required Time | 11.263 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 9.811 | 2.160 | tNET | FF | 1 | R24C152[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.611 | 3.611 | tNET | RR | 1 | R24C152[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
| 11.263 | -0.347 | tSu | 1 | R24C152[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
| Clock Skew | 0.403 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.160, 82.997%; tC2Q: 0.442, 17.003% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.611, 100.000% |
Path5
Path Summary:
| Slack | 1.453 |
| Data Arrival Time | 9.811 |
| Data Required Time | 11.263 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 9.811 | 2.160 | tNET | FF | 1 | R24C152[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.611 | 3.611 | tNET | RR | 1 | R24C152[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
| 11.263 | -0.347 | tSu | 1 | R24C152[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
| Clock Skew | 0.403 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.160, 82.997%; tC2Q: 0.442, 17.003% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.611, 100.000% |
Path6
Path Summary:
| Slack | 1.606 |
| Data Arrival Time | 9.662 |
| Data Required Time | 11.268 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 9.662 | 2.011 | tNET | FF | 1 | R22C154[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.616 | 3.616 | tNET | RR | 1 | R22C154[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
| 11.268 | -0.347 | tSu | 1 | R22C154[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
| Clock Skew | 0.408 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.011, 81.966%; tC2Q: 0.442, 18.034% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.616, 100.000% |
Path7
Path Summary:
| Slack | 1.606 |
| Data Arrival Time | 9.662 |
| Data Required Time | 11.268 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 9.662 | 2.011 | tNET | FF | 1 | R22C154[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.616 | 3.616 | tNET | RR | 1 | R22C154[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
| 11.268 | -0.347 | tSu | 1 | R22C154[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
| Clock Skew | 0.408 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.011, 81.966%; tC2Q: 0.442, 18.034% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.616, 100.000% |
Path8
Path Summary:
| Slack | 1.606 |
| Data Arrival Time | 9.662 |
| Data Required Time | 11.268 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 9.662 | 2.011 | tNET | FF | 1 | R22C154[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.616 | 3.616 | tNET | RR | 1 | R22C154[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
| 11.268 | -0.347 | tSu | 1 | R22C154[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
| Clock Skew | 0.408 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.011, 81.966%; tC2Q: 0.442, 18.034% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.616, 100.000% |
Path9
Path Summary:
| Slack | 1.606 |
| Data Arrival Time | 9.662 |
| Data Required Time | 11.268 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 9.662 | 2.011 | tNET | FF | 1 | R22C154[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.616 | 3.616 | tNET | RR | 1 | R22C154[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
| 11.268 | -0.347 | tSu | 1 | R22C154[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
| Clock Skew | 0.408 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.011, 81.966%; tC2Q: 0.442, 18.034% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.616, 100.000% |
Path10
Path Summary:
| Slack | 1.661 |
| Data Arrival Time | 9.601 |
| Data Required Time | 11.261 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 9.601 | 1.950 | tNET | FF | 1 | R21C151[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.609 | 3.609 | tNET | RR | 1 | R21C151[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK |
| 11.261 | -0.347 | tSu | 1 | R21C151[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Path Statistics:
| Clock Skew | 0.401 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.950, 81.505%; tC2Q: 0.442, 18.495% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.609, 100.000% |
Path11
Path Summary:
| Slack | 1.661 |
| Data Arrival Time | 9.601 |
| Data Required Time | 11.261 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 9.601 | 1.950 | tNET | FF | 1 | R21C151[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.609 | 3.609 | tNET | RR | 1 | R21C151[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK |
| 11.261 | -0.347 | tSu | 1 | R21C151[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Path Statistics:
| Clock Skew | 0.401 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.950, 81.505%; tC2Q: 0.442, 18.495% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.609, 100.000% |
Path12
Path Summary:
| Slack | 1.663 |
| Data Arrival Time | 9.601 |
| Data Required Time | 11.263 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 9.601 | 1.950 | tNET | FF | 1 | R24C150[0][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.611 | 3.611 | tNET | RR | 1 | R24C150[0][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK |
| 11.263 | -0.347 | tSu | 1 | R24C150[0][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
| Clock Skew | 0.403 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.950, 81.505%; tC2Q: 0.442, 18.495% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.611, 100.000% |
Path13
Path Summary:
| Slack | 3.443 |
| Data Arrival Time | 7.772 |
| Data Required Time | 11.215 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_3_s0 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.676 | 3.676 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 4.043 | 0.368 | tC2Q | RF | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 7.772 | 3.729 | tNET | FF | 1 | R12C154[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.563 | 3.563 | tNET | RR | 1 | R12C154[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_3_s0/CLK |
| 11.215 | -0.347 | tSu | 1 | R12C154[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_3_s0 |
Path Statistics:
| Clock Skew | -0.113 |
| Setup Relationship | 8.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.729, 91.028%; tC2Q: 0.368, 8.972% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.563, 100.000% |
Path14
Path Summary:
| Slack | 3.541 |
| Data Arrival Time | 7.719 |
| Data Required Time | 11.261 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_2_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.676 | 3.676 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 4.043 | 0.368 | tC2Q | RF | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 7.719 | 3.676 | tNET | FF | 1 | R7C146[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.608 | 3.608 | tNET | RR | 1 | R7C146[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_2_s1/CLK |
| 11.261 | -0.347 | tSu | 1 | R7C146[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_2_s1 |
Path Statistics:
| Clock Skew | -0.068 |
| Setup Relationship | 8.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.676, 90.912%; tC2Q: 0.368, 9.088% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.608, 100.000% |
Path15
Path Summary:
| Slack | 3.541 |
| Data Arrival Time | 7.719 |
| Data Required Time | 11.261 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_9_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.676 | 3.676 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 4.043 | 0.368 | tC2Q | RF | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 7.719 | 3.676 | tNET | FF | 1 | R7C146[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_9_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.608 | 3.608 | tNET | RR | 1 | R7C146[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_9_s1/CLK |
| 11.261 | -0.347 | tSu | 1 | R7C146[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_9_s1 |
Path Statistics:
| Clock Skew | -0.068 |
| Setup Relationship | 8.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.676, 90.912%; tC2Q: 0.368, 9.088% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.608, 100.000% |
Path16
Path Summary:
| Slack | 3.541 |
| Data Arrival Time | 7.719 |
| Data Required Time | 11.261 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_10_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.676 | 3.676 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 4.043 | 0.368 | tC2Q | RF | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 7.719 | 3.676 | tNET | FF | 1 | R7C146[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_10_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.608 | 3.608 | tNET | RR | 1 | R7C146[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_10_s1/CLK |
| 11.261 | -0.347 | tSu | 1 | R7C146[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_10_s1 |
Path Statistics:
| Clock Skew | -0.068 |
| Setup Relationship | 8.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.676, 90.912%; tC2Q: 0.368, 9.088% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.608, 100.000% |
Path17
Path Summary:
| Slack | 3.541 |
| Data Arrival Time | 7.719 |
| Data Required Time | 11.261 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_16_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.676 | 3.676 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 4.043 | 0.368 | tC2Q | RF | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 7.719 | 3.676 | tNET | FF | 1 | R7C146[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_16_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.608 | 3.608 | tNET | RR | 1 | R7C146[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_16_s1/CLK |
| 11.261 | -0.347 | tSu | 1 | R7C146[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_16_s1 |
Path Statistics:
| Clock Skew | -0.068 |
| Setup Relationship | 8.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.676, 90.912%; tC2Q: 0.368, 9.088% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.608, 100.000% |
Path18
Path Summary:
| Slack | 3.541 |
| Data Arrival Time | 7.719 |
| Data Required Time | 11.261 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_17_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.676 | 3.676 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 4.043 | 0.368 | tC2Q | RF | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 7.719 | 3.676 | tNET | FF | 1 | R7C146[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_17_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.608 | 3.608 | tNET | RR | 1 | R7C146[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_17_s1/CLK |
| 11.261 | -0.347 | tSu | 1 | R7C146[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_17_s1 |
Path Statistics:
| Clock Skew | -0.068 |
| Setup Relationship | 8.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.676, 90.912%; tC2Q: 0.368, 9.088% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.608, 100.000% |
Path19
Path Summary:
| Slack | 3.541 |
| Data Arrival Time | 7.719 |
| Data Required Time | 11.261 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_18_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.676 | 3.676 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 4.043 | 0.368 | tC2Q | RF | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 7.719 | 3.676 | tNET | FF | 1 | R7C146[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_18_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.608 | 3.608 | tNET | RR | 1 | R7C146[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_18_s1/CLK |
| 11.261 | -0.347 | tSu | 1 | R7C146[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/dest_addr_reg_18_s1 |
Path Statistics:
| Clock Skew | -0.068 |
| Setup Relationship | 8.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.676, 90.912%; tC2Q: 0.368, 9.088% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.608, 100.000% |
Path20
Path Summary:
| Slack | 1.823 |
| Data Arrival Time | 9.443 |
| Data Required Time | 11.266 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 9.443 | 1.793 | tNET | FF | 1 | R23C154[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.613 | 3.613 | tNET | RR | 1 | R23C154[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
| 11.266 | -0.347 | tSu | 1 | R23C154[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
| Clock Skew | 0.405 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.793, 80.201%; tC2Q: 0.442, 19.799% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.613, 100.000% |
Path21
Path Summary:
| Slack | 1.823 |
| Data Arrival Time | 9.443 |
| Data Required Time | 11.266 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 9.443 | 1.793 | tNET | FF | 1 | R23C154[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.613 | 3.613 | tNET | RR | 1 | R23C154[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
| 11.266 | -0.347 | tSu | 1 | R23C154[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
| Clock Skew | 0.405 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.793, 80.201%; tC2Q: 0.442, 19.799% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.613, 100.000% |
Path22
Path Summary:
| Slack | 1.823 |
| Data Arrival Time | 9.443 |
| Data Required Time | 11.266 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
| Launch Clk | rx_mac_clk:[F] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.000 | 4.000 | active clock edge time | ||||
| 4.000 | 0.000 | rx_mac_clk | ||||
| 4.000 | 0.000 | tCL | FF | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.208 | 3.208 | tNET | FF | 1 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 7.651 | 0.442 | tC2Q | FF | 53 | R31C163[0][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 9.443 | 1.793 | tNET | FF | 1 | R23C154[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.613 | 3.613 | tNET | RR | 1 | R23C154[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK |
| 11.266 | -0.347 | tSu | 1 | R23C154[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Path Statistics:
| Clock Skew | 0.405 |
| Setup Relationship | 4.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.208, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.793, 80.201%; tC2Q: 0.442, 19.799% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.613, 100.000% |
Path23
Path Summary:
| Slack | 3.652 |
| Data Arrival Time | 7.571 |
| Data Required Time | 11.222 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_8_s0 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.676 | 3.676 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 4.043 | 0.368 | tC2Q | RF | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 7.571 | 3.528 | tNET | FF | 1 | R11C155[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.570 | 3.570 | tNET | RR | 1 | R11C155[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_8_s0/CLK |
| 11.222 | -0.347 | tSu | 1 | R11C155[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_8_s0 |
Path Statistics:
| Clock Skew | -0.106 |
| Setup Relationship | 8.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.528, 90.565%; tC2Q: 0.368, 9.435% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.570, 100.000% |
Path24
Path Summary:
| Slack | 3.652 |
| Data Arrival Time | 7.571 |
| Data Required Time | 11.222 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_er_err_o_s0 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.676 | 3.676 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 4.043 | 0.368 | tC2Q | RF | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 7.571 | 3.528 | tNET | FF | 1 | R11C155[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_er_err_o_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.570 | 3.570 | tNET | RR | 1 | R11C155[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_er_err_o_s0/CLK |
| 11.222 | -0.347 | tSu | 1 | R11C155[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_er_err_o_s0 |
Path Statistics:
| Clock Skew | -0.106 |
| Setup Relationship | 8.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.528, 90.565%; tC2Q: 0.368, 9.435% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.570, 100.000% |
Path25
Path Summary:
| Slack | 3.661 |
| Data Arrival Time | 7.571 |
| Data Required Time | 11.232 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_tmp_6_s0 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.676 | 3.676 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 4.043 | 0.368 | tC2Q | RF | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 7.571 | 3.528 | tNET | FF | 1 | R11C154[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_tmp_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.000 | 8.000 | active clock edge time | ||||
| 8.000 | 0.000 | rx_mac_clk | ||||
| 8.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 11.579 | 3.579 | tNET | RR | 1 | R11C154[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_tmp_6_s0/CLK |
| 11.232 | -0.347 | tSu | 1 | R11C154[0][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_pause_val_o_tmp_6_s0 |
Path Statistics:
| Clock Skew | -0.096 |
| Setup Relationship | 8.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.676, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.528, 90.565%; tC2Q: 0.368, 9.435% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.579, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.392 |
| Data Arrival Time | 1.772 |
| Data Required Time | 1.380 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.772 | 0.201 | tNET | RR | 1 | R6C141[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.433 | 1.433 | tNET | RR | 1 | R6C141[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5/CLK |
| 1.380 | -0.053 | tHld | 1 | R6C141[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5 |
Path Statistics:
| Clock Skew | 0.006 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.201, 58.261%; tC2Q: 0.144, 41.739% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.433, 100.000% |
Path2
Path Summary:
| Slack | 0.394 |
| Data Arrival Time | 1.766 |
| Data Required Time | 1.372 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_int_tmp_3_s0 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.766 | 0.195 | tNET | RR | 1 | R6C143[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_int_tmp_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.425 | 1.425 | tNET | RR | 1 | R6C143[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_int_tmp_3_s0/CLK |
| 1.372 | -0.053 | tHld | 1 | R6C143[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_int_tmp_3_s0 |
Path Statistics:
| Clock Skew | -0.002 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.195, 57.522%; tC2Q: 0.144, 42.478% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.425, 100.000% |
Path3
Path Summary:
| Slack | 0.401 |
| Data Arrival Time | 1.774 |
| Data Required Time | 1.373 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/sync_status_d2_s0 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.774 | 0.203 | tNET | RR | 1 | R8C141[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/sync_status_d2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.426 | 1.426 | tNET | RR | 1 | R8C141[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/sync_status_d2_s0/CLK |
| 1.373 | -0.053 | tHld | 1 | R8C141[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/sync_status_d2_s0 |
Path Statistics:
| Clock Skew | -0.001 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 58.501%; tC2Q: 0.144, 41.499% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.426, 100.000% |
Path4
Path Summary:
| Slack | 0.407 |
| Data Arrival Time | 1.776 |
| Data Required Time | 1.369 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_13_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.776 | 0.205 | tNET | RR | 1 | R8C142[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_13_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.422 | 1.422 | tNET | RR | 1 | R8C142[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_13_s1/CLK |
| 1.369 | -0.053 | tHld | 1 | R8C142[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_13_s1 |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.422, 100.000% |
Path5
Path Summary:
| Slack | 0.407 |
| Data Arrival Time | 1.776 |
| Data Required Time | 1.369 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_14_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.776 | 0.205 | tNET | RR | 1 | R8C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_14_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.422 | 1.422 | tNET | RR | 1 | R8C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_14_s1/CLK |
| 1.369 | -0.053 | tHld | 1 | R8C142[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_14_s1 |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.422, 100.000% |
Path6
Path Summary:
| Slack | 0.407 |
| Data Arrival Time | 1.776 |
| Data Required Time | 1.369 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_15_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.776 | 0.205 | tNET | RR | 1 | R8C142[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_15_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.422 | 1.422 | tNET | RR | 1 | R8C142[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_15_s1/CLK |
| 1.369 | -0.053 | tHld | 1 | R8C142[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_15_s1 |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.422, 100.000% |
Path7
Path Summary:
| Slack | 0.407 |
| Data Arrival Time | 1.776 |
| Data Required Time | 1.369 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.776 | 0.205 | tNET | RR | 1 | R8C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.422 | 1.422 | tNET | RR | 1 | R8C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1/CLK |
| 1.369 | -0.053 | tHld | 1 | R8C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_16_s1 |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.422, 100.000% |
Path8
Path Summary:
| Slack | 0.410 |
| Data Arrival Time | 1.778 |
| Data Required Time | 1.368 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_0_s3 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.778 | 0.207 | tNET | RR | 1 | R9C141[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_0_s3/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.421 | 1.421 | tNET | RR | 1 | R9C141[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_0_s3/CLK |
| 1.368 | -0.053 | tHld | 1 | R9C141[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_0_s3 |
Path Statistics:
| Clock Skew | -0.006 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.207, 58.974%; tC2Q: 0.144, 41.026% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.421, 100.000% |
Path9
Path Summary:
| Slack | 0.410 |
| Data Arrival Time | 1.778 |
| Data Required Time | 1.368 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_1_s3 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.778 | 0.207 | tNET | RR | 1 | R9C141[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_1_s3/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.421 | 1.421 | tNET | RR | 1 | R9C141[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_1_s3/CLK |
| 1.368 | -0.053 | tHld | 1 | R9C141[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_1_s3 |
Path Statistics:
| Clock Skew | -0.006 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.207, 58.974%; tC2Q: 0.144, 41.026% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.421, 100.000% |
Path10
Path Summary:
| Slack | 0.410 |
| Data Arrival Time | 1.778 |
| Data Required Time | 1.368 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_4_s3 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.778 | 0.207 | tNET | RR | 1 | R9C141[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_4_s3/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.421 | 1.421 | tNET | RR | 1 | R9C141[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_4_s3/CLK |
| 1.368 | -0.053 | tHld | 1 | R9C141[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/an_sync_status_fail_cnt_4_s3 |
Path Statistics:
| Clock Skew | -0.006 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.207, 58.974%; tC2Q: 0.144, 41.026% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.421, 100.000% |
Path11
Path Summary:
| Slack | 0.411 |
| Data Arrival Time | 1.780 |
| Data Required Time | 1.369 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.780 | 0.209 | tNET | RR | 1 | R8C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.422 | 1.422 | tNET | RR | 1 | R8C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1/CLK |
| 1.369 | -0.053 | tHld | 1 | R8C144[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_8_s1 |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.209, 59.207%; tC2Q: 0.144, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.422, 100.000% |
Path12
Path Summary:
| Slack | 0.411 |
| Data Arrival Time | 1.780 |
| Data Required Time | 1.369 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.780 | 0.209 | tNET | RR | 1 | R8C144[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.422 | 1.422 | tNET | RR | 1 | R8C144[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1/CLK |
| 1.369 | -0.053 | tHld | 1 | R8C144[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_9_s1 |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.209, 59.207%; tC2Q: 0.144, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.422, 100.000% |
Path13
Path Summary:
| Slack | 0.411 |
| Data Arrival Time | 1.780 |
| Data Required Time | 1.369 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_10_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.780 | 0.209 | tNET | RR | 1 | R8C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_10_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.422 | 1.422 | tNET | RR | 1 | R8C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_10_s1/CLK |
| 1.369 | -0.053 | tHld | 1 | R8C144[3][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_10_s1 |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.209, 59.207%; tC2Q: 0.144, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.422, 100.000% |
Path14
Path Summary:
| Slack | 0.411 |
| Data Arrival Time | 1.780 |
| Data Required Time | 1.369 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.780 | 0.209 | tNET | RR | 1 | R8C144[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.422 | 1.422 | tNET | RR | 1 | R8C144[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1/CLK |
| 1.369 | -0.053 | tHld | 1 | R8C144[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_11_s1 |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.209, 59.207%; tC2Q: 0.144, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.422, 100.000% |
Path15
Path Summary:
| Slack | 0.411 |
| Data Arrival Time | 1.780 |
| Data Required Time | 1.369 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_12_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.780 | 0.209 | tNET | RR | 1 | R8C144[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_12_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.422 | 1.422 | tNET | RR | 1 | R8C144[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_12_s1/CLK |
| 1.369 | -0.053 | tHld | 1 | R8C144[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_12_s1 |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.209, 59.207%; tC2Q: 0.144, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.422, 100.000% |
Path16
Path Summary:
| Slack | 0.412 |
| Data Arrival Time | 1.776 |
| Data Required Time | 1.364 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_17_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.776 | 0.205 | tNET | RR | 1 | R9C142[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_17_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.417 | 1.417 | tNET | RR | 1 | R9C142[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_17_s1/CLK |
| 1.364 | -0.053 | tHld | 1 | R9C142[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_17_s1 |
Path Statistics:
| Clock Skew | -0.010 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.417, 100.000% |
Path17
Path Summary:
| Slack | 0.414 |
| Data Arrival Time | 1.803 |
| Data Required Time | 1.389 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_9_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/CLK |
| 1.586 | 0.144 | tC2Q | RR | 506 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q |
| 1.803 | 0.217 | tNET | RR | 1 | R15C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_9_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R15C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_9_s1/CLK |
| 1.389 | -0.053 | tHld | 1 | R15C135[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_9_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 60.111%; tC2Q: 0.144, 39.889% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
Path18
Path Summary:
| Slack | 0.414 |
| Data Arrival Time | 1.803 |
| Data Required Time | 1.389 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_10_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/CLK |
| 1.586 | 0.144 | tC2Q | RR | 506 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q |
| 1.803 | 0.217 | tNET | RR | 1 | R15C135[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_10_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R15C135[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_10_s1/CLK |
| 1.389 | -0.053 | tHld | 1 | R15C135[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_10_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 60.111%; tC2Q: 0.144, 39.889% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
Path19
Path Summary:
| Slack | 0.414 |
| Data Arrival Time | 1.803 |
| Data Required Time | 1.389 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_12_s1 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/CLK |
| 1.586 | 0.144 | tC2Q | RR | 506 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q |
| 1.803 | 0.217 | tNET | RR | 1 | R15C135[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_12_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R15C135[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_12_s1/CLK |
| 1.389 | -0.053 | tHld | 1 | R15C135[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_12_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 60.111%; tC2Q: 0.144, 39.889% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
Path20
Path Summary:
| Slack | 0.415 |
| Data Arrival Time | 1.780 |
| Data Required Time | 1.365 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.780 | 0.209 | tNET | RR | 1 | R8C143[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.418 | 1.418 | tNET | RR | 1 | R8C143[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1/CLK |
| 1.365 | -0.053 | tHld | 1 | R8C143[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_18_s1 |
Path Statistics:
| Clock Skew | -0.009 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.209, 59.207%; tC2Q: 0.144, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.418, 100.000% |
Path21
Path Summary:
| Slack | 0.415 |
| Data Arrival Time | 1.780 |
| Data Required Time | 1.365 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s1 |
| Launch Clk | rx_mac_clk:[R] |
| Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.427 | 1.427 | tNET | RR | 1 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/CLK |
| 1.571 | 0.144 | tC2Q | RR | 651 | R7C142[1][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_rx_temp_s0/Q |
| 1.780 | 0.209 | tNET | RR | 1 | R8C143[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | rx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1012 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 1.418 | 1.418 | tNET | RR | 1 | R8C143[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s1/CLK |
| 1.365 | -0.053 | tHld | 1 | R8C143[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/link_timer_cnt_20_s1 |
Path Statistics:
| Clock Skew | -0.009 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.427, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.209, 59.207%; tC2Q: 0.144, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.418, 100.000% |
Path22
Path Summary:
| Slack | 0.417 |
| Data Arrival Time | 1.805 |
| Data Required Time | 1.388 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_latch_0_s3 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/CLK |
| 1.586 | 0.144 | tC2Q | RR | 506 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q |
| 1.805 | 0.219 | tNET | RR | 1 | R17C136[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_latch_0_s3/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.441 | 1.441 | tNET | RR | 1 | R17C136[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_latch_0_s3/CLK |
| 1.388 | -0.053 | tHld | 1 | R17C136[2][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_latch_0_s3 |
Path Statistics:
| Clock Skew | -0.002 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.219, 60.331%; tC2Q: 0.144, 39.669% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.441, 100.000% |
Path23
Path Summary:
| Slack | 0.417 |
| Data Arrival Time | 1.805 |
| Data Required Time | 1.388 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/clk_ena_s0 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/CLK |
| 1.586 | 0.144 | tC2Q | RR | 506 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q |
| 1.805 | 0.219 | tNET | RR | 1 | R17C136[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/clk_ena_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.441 | 1.441 | tNET | RR | 1 | R17C136[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/clk_ena_s0/CLK |
| 1.388 | -0.053 | tHld | 1 | R17C136[0][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/clk_ena_s0 |
Path Statistics:
| Clock Skew | -0.002 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.219, 60.331%; tC2Q: 0.144, 39.669% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.441, 100.000% |
Path24
Path Summary:
| Slack | 0.417 |
| Data Arrival Time | 1.805 |
| Data Required Time | 1.388 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_0_s0 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/CLK |
| 1.586 | 0.144 | tC2Q | RR | 506 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q |
| 1.805 | 0.219 | tNET | RR | 1 | R17C136[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.441 | 1.441 | tNET | RR | 1 | R17C136[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_0_s0/CLK |
| 1.388 | -0.053 | tHld | 1 | R17C136[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_reg2_0_s0 |
Path Statistics:
| Clock Skew | -0.002 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.219, 60.331%; tC2Q: 0.144, 39.669% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.441, 100.000% |
Path25
Path Summary:
| Slack | 0.417 |
| Data Arrival Time | 1.805 |
| Data Required Time | 1.388 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg2_6_s0 |
| Launch Clk | tx_mac_clk:[R] |
| Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.442 | 1.442 | tNET | RR | 1 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/CLK |
| 1.586 | 0.144 | tC2Q | RR | 506 | R15C137[2][A] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_tx_temp_s0/Q |
| 1.805 | 0.219 | tNET | RR | 1 | R17C136[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg2_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | tx_mac_clk | ||||
| 0.000 | 0.000 | tCL | RR | 638 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 1.441 | 1.441 | tNET | RR | 1 | R17C136[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg2_6_s0/CLK |
| 1.388 | -0.053 | tHld | 1 | R17C136[1][B] | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_reg2_6_s0 |
Path Statistics:
| Clock Skew | -0.002 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.442, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.219, 60.331%; tC2Q: 0.144, 39.669% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.441, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 1.075 |
| Actual Width: | 2.075 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | rx_mac_clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | rx_mac_clk | ||
| 0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.596 | 3.596 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.000 | 0.000 | active clock edge time | ||
| 4.000 | 0.000 | rx_mac_clk | ||
| 4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 5.671 | 1.671 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
MPW2
MPW Summary:
| Slack: | 1.080 |
| Actual Width: | 2.080 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | rx_mac_clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | rx_mac_clk | ||
| 0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 3.587 | 3.587 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.000 | 0.000 | active clock edge time | ||
| 4.000 | 0.000 | rx_mac_clk | ||
| 4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 5.667 | 1.667 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB |
MPW3
MPW Summary:
| Slack: | 1.160 |
| Actual Width: | 2.160 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | rx_mac_clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.000 | 0.000 | active clock edge time | ||
| 4.000 | 0.000 | rx_mac_clk | ||
| 4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.246 | 3.246 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.000 | 0.000 | active clock edge time | ||
| 8.000 | 0.000 | rx_mac_clk | ||
| 8.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 9.406 | 1.406 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
MPW4
MPW Summary:
| Slack: | 1.165 |
| Actual Width: | 2.165 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | rx_mac_clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.000 | 0.000 | active clock edge time | ||
| 4.000 | 0.000 | rx_mac_clk | ||
| 4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 7.237 | 3.237 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.000 | 0.000 | active clock edge time | ||
| 8.000 | 0.000 | rx_mac_clk | ||
| 8.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
| 9.402 | 1.402 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB |
MPW5
MPW Summary:
| Slack: | 1.548 |
| Actual Width: | 1.798 |
| Required Width: | 0.250 |
| Type: | High Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_fabric_tx_vld_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | tx_mac_clk | ||
| 0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 3.976 | 3.976 | tNET | RR | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_fabric_tx_vld_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.000 | 0.000 | active clock edge time | ||
| 4.000 | 0.000 | tx_mac_clk | ||
| 4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 5.774 | 1.774 | tNET | FF | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_fabric_tx_vld_s0/CLK |
MPW6
MPW Summary:
| Slack: | 1.591 |
| Actual Width: | 1.841 |
| Required Width: | 0.250 |
| Type: | High Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg2_4_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | tx_mac_clk | ||
| 0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 3.936 | 3.936 | tNET | RR | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg2_4_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.000 | 0.000 | active clock edge time | ||
| 4.000 | 0.000 | tx_mac_clk | ||
| 4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 5.777 | 1.777 | tNET | FF | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_ifg_delay_reg2_4_s0/CLK |
MPW7
MPW Summary:
| Slack: | 1.591 |
| Actual Width: | 1.841 |
| Required Width: | 0.250 |
| Type: | High Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_latch_12_s3 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | tx_mac_clk | ||
| 0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 3.936 | 3.936 | tNET | RR | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_latch_12_s3/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.000 | 0.000 | active clock edge time | ||
| 4.000 | 0.000 | tx_mac_clk | ||
| 4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 5.777 | 1.777 | tNET | FF | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_val_latch_12_s3/CLK |
MPW8
MPW Summary:
| Slack: | 1.591 |
| Actual Width: | 1.841 |
| Required Width: | 0.250 |
| Type: | High Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/u_crc_gen/crc_reg_27_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | tx_mac_clk | ||
| 0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 3.936 | 3.936 | tNET | RR | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/u_crc_gen/crc_reg_27_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.000 | 0.000 | active clock edge time | ||
| 4.000 | 0.000 | tx_mac_clk | ||
| 4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 5.777 | 1.777 | tNET | FF | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/u_crc_gen/crc_reg_27_s1/CLK |
MPW9
MPW Summary:
| Slack: | 1.591 |
| Actual Width: | 1.841 |
| Required Width: | 0.250 |
| Type: | High Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_19_s3 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | tx_mac_clk | ||
| 0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 3.936 | 3.936 | tNET | RR | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_19_s3/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.000 | 0.000 | active clock edge time | ||
| 4.000 | 0.000 | tx_mac_clk | ||
| 4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 5.777 | 1.777 | tNET | FF | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_19_s3/CLK |
MPW10
MPW Summary:
| Slack: | 1.591 |
| Actual Width: | 1.841 |
| Required Width: | 0.250 |
| Type: | High Pulse Width |
| Clock: | tx_mac_clk |
| Objects: | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_17_s3 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | tx_mac_clk | ||
| 0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 3.936 | 3.936 | tNET | RR | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_17_s3/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.000 | 0.000 | active clock edge time | ||
| 4.000 | 0.000 | tx_mac_clk | ||
| 4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
| 5.777 | 1.777 | tNET | FF | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_17_s3/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 1012 | rx_mac_clk | 0.671 | 3.725 |
| 638 | tx_mac_clk | 2.246 | 3.976 |
| 208 | gw_gao_inst_0/control0[0] | 43.337 | 5.719 |
| 128 | u_mac_rx_model/cur_state[0] | 3.752 | 1.644 |
| 128 | u_mac_rx_model/cur_state[1] | 3.856 | 2.030 |
| 87 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/clk_ena | 2.228 | 2.645 |
| 83 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/c_state_reg[0] | 3.613 | 1.571 |
| 83 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/c_state_reg[1] | 3.704 | 1.349 |
| 81 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_dv_reg[0] | 3.249 | 1.353 |
| 77 | u_mac_rx_model/shift_reg_pause_143_13 | 4.564 | 1.140 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R2C2 | 100.00% |
| R2C35 | 100.00% |
| R2C51 | 100.00% |
| R2C59 | 100.00% |
| R2C63 | 100.00% |
| R2C65 | 100.00% |
| R2C66 | 100.00% |
| R3C14 | 100.00% |
| R4C90 | 100.00% |
| R7C62 | 100.00% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name rx_mac_clk -period 8 -waveform {0 4} [get_pins {u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK}] |
| TC_CLOCK | Actived | create_clock -name clk_in -period 19.048 -waveform {0 9.524} [get_pins {u_osc/OSCOUT}] |
| TC_CLOCK | Actived | create_clock -name tck -period 50 -waveform {0 25} [get_pins {gw_gao_inst_0/tck_ibuf/I}] |
| TC_CLOCK | Actived | create_clock -name tx_mac_clk -period 8 -waveform {0 4} [get_pins {u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk_in tck}] -to [get_clocks {rx_mac_clk tx_mac_clk}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {rx_mac_clk}] -to [get_clocks {clk_in tx_mac_clk tck}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {tx_mac_clk}] -to [get_clocks {rx_mac_clk clk_in}] |