Power Messages

Report Title	Power Analysis Report
Design File	E:\IP_Release\1G_Serial_Ethernet_Over_Serdes\191201\Gowin_1G_Serial_Ethernet_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\IP_Release\1G_Serial_Ethernet_Over_Serdes\191201\Gowin_1G_Serial_Ethernet_RefDesign\project\src\fpga_project.cst
Timing Constraints File	E:\IP_Release\1G_Serial_Ethernet_Over_Serdes\191201\Gowin_1G_Serial_Ethernet_RefDesign\project\src\fpga_project.sdc
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW5AST-LV138FPG676AES
Device	GW5AST-138
Device Version	B
Created Time	Tue Dec 30 10:25:02 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade	Commercial
Process	Typical
Ambient Temperature	25.000
Use Custom Theta JA	false
Heat Sink	None
Air Flow	LFM_0
Use Custom Theta SA	false
Board Thermal Model	None
Use Custom Theta JB	false
Related Vcd File
Related Saif File
Filter Glitches	false
Default IO Toggle Rate	0.125
Default Remain Toggle Rate	0.125

Power Summary

Power Information:

Total Power (mW)	110.470
Quiescent Power (mW)	100.654
Dynamic Power (mW)	9.815

Thermal Information:

Junction Temperature	26.350
Theta JA	12.222
Max Allowed Ambient Temperature	83.650

Supply Information:

Voltage Source	Voltage	Dynamic Current(mA)	Quiescent Current(mA)	Power(mW)
VCC	0.900	9.876	80.004	80.892
VCCX	1.800	0.180	7.200	13.285
VCCIO33	3.300	0.183	3.009	10.533
VCCLDO	1.200	0.000	4.800	5.760

Power Details

Power By Block Type:

Block Type	Total Power(mW)	Static Power(mW)	Average Toggle Rate(millions of transitions/sec)
Logic	1.376	NA	13.809
IO	11.542	10.453	13.125
BSRAM	7.329	NA	NA

Power By Hierarchy:

Hierarchy Entity	Total Power(mW)	Block Dynamic Power(mW)
top	8.705	8.705(8.687)
top/gw_gao_inst_0/	7.430	7.430(7.430)
top/gw_gao_inst_0/u_icon_top/	0.002	0.002(0.000)
top/gw_gao_inst_0/u_la0_top/	7.428	7.428(7.377)
top/gw_gao_inst_0/u_la0_top/u_ao_crc32/	0.004	0.004(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/	3.430	3.430(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_match_0/	0.001	0.001(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/	3.942	3.942(0.000)
top/u_SerDes_Top/	1.016	1.016(1.016)
top/u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/	1.016	1.016(1.016)
top/u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/	1.016	1.016(1.000)
top/u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_encoder_8b10b_disparity/	0.004	0.004(0.000)
top/u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/	0.119	0.119(0.000)
top/u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/	0.154	0.154(0.000)
top/u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_sync/	0.030	0.030(0.000)
top/u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_tx/	0.086	0.086(0.000)
top/u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/	0.260	0.260(0.044)
top/u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/	0.044	0.044(0.000)
top/u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/	0.341	0.341(0.072)
top/u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/u_crc_gen/	0.049	0.049(0.000)
top/u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/u_lfsr/	0.022	0.022(0.000)
top/u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/	0.006	0.006(0.000)
top/u_mac_rx_model/	0.161	0.161(0.000)
top/u_mac_tx_model/	0.080	0.080(0.000)

Power By Clock Domain:

Clock Domain	Clock Frequency(Mhz)	Total Dynamic Power(mW)
rx_mac_clk	125.000	7.144
tx_mac_clk	125.000	0.535
NO CLOCK DOMAIN	0.000	0.000
clk_in	52.499	0.002
tck	20.000	1.045