Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\IP_Release\1G_Serial_Ethernet_Over_Serdes\191201\Gowin_1G_Serial_Ethernet_RefDesign\project\src\mac_rx_model.v E:\IP_Release\1G_Serial_Ethernet_Over_Serdes\191201\Gowin_1G_Serial_Ethernet_RefDesign\project\src\mac_tx_model.v E:\IP_Release\1G_Serial_Ethernet_Over_Serdes\191201\Gowin_1G_Serial_Ethernet_RefDesign\project\src\serdes\giga_serial_ethernet\giga_serial_ethernet.v E:\IP_Release\1G_Serial_Ethernet_Over_Serdes\191201\Gowin_1G_Serial_Ethernet_RefDesign\project\src\serdes\serdes.v E:\IP_Release\1G_Serial_Ethernet_Over_Serdes\191201\Gowin_1G_Serial_Ethernet_RefDesign\project\src\top.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top_138.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\gw_jtag.v E:\IP_Release\1G_Serial_Ethernet_Over_Serdes\191201\Gowin_1G_Serial_Ethernet_RefDesign\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Dec 30 10:24:01 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.921s, Elapsed time = 0h 0m 1s, Peak memory usage = 277.422MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.262s, Peak memory usage = 277.422MB Optimizing Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.188s, Peak memory usage = 277.422MB Optimizing Phase 2: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.723s, Peak memory usage = 277.422MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.318s, Peak memory usage = 277.422MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 277.422MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 277.422MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 277.422MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.585s, Peak memory usage = 277.422MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.146s, Peak memory usage = 277.422MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 277.422MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 294.465MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.226s, Peak memory usage = 294.465MB Generate output files: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.257s, Peak memory usage = 294.465MB |
| Total Time and Memory Usage | CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 294.465MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 7 |
| I/O Buf | 7 |
| IBUF | 4 |
| OBUF | 3 |
| Register | 1859 |
| DFFRE | 45 |
| DFFPE | 113 |
| DFFCE | 1701 |
| LUT | 2215 |
| LUT2 | 319 |
| LUT3 | 512 |
| LUT4 | 1384 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 73 |
| ALU | 73 |
| INV | 19 |
| INV | 19 |
| BSRAM | 2 |
| SDPB | 2 |
| CLOCK | 1 |
| OSC | 1 |
| Black Box | 2 |
| GW_JTAG | 1 |
| GTR12_QUAD | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2315(2242 LUT, 73 ALU) / 138240 | 2% |
| Register | 1859 / 139140 | 2% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 1859 / 139140 | 2% |
| BSRAM | 2 / 340 | <1% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | u_osc/OSCOUT.default_clk | Base | 19.048 | 52.500 | 0.000 | 9.524 | u_osc/OSCOUT | ||
| 2 | gw_gao_inst_0/u_icon_top/n31_6 | Base | 10.000 | 100.000 | 0.000 | 5.000 | gw_gao_inst_0/u_icon_top/n31_s2/F | ||
| 3 | gw_gao_inst_0/u_la0_top/n15_6 | Base | 10.000 | 100.000 | 0.000 | 5.000 | gw_gao_inst_0/u_la0_top/n15_s2/F |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | u_osc/OSCOUT.default_clk | 52.500(MHz) | 856.531(MHz) | 1 | TOP |
| 2 | gw_gao_inst_0/u_icon_top/n31_6 | 100.000(MHz) | 1164.484(MHz) | 1 | TOP |
| 3 | gw_gao_inst_0/u_la0_top/n15_6 | 100.000(MHz) | 1164.484(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 9.141 |
| Data Arrival Time | 1.207 |
| Data Required Time | 10.349 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0 |
| To | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| Launch Clk | gw_gao_inst_0/u_la0_top/n15_6[R] |
| Latch Clk | gw_gao_inst_0/u_la0_top/n15_6[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw_gao_inst_0/u_la0_top/n15_6 | |||
| 0.000 | 0.000 | tCL | RR | 2 | gw_gao_inst_0/u_la0_top/n15_s2/F |
| 0.413 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | gw_gao_inst_0/u_la0_top/n15_6 | |||
| 10.000 | 0.000 | tCL | RR | 2 | gw_gao_inst_0/u_la0_top/n15_s2/F |
| 10.413 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.413, 51.887%; tC2Q: 0.382, 48.113% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 9.141 |
| Data Arrival Time | 1.207 |
| Data Required Time | 10.349 |
| From | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
| To | gw_gao_inst_0/u_icon_top/enable_reg_0_s0 |
| Launch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| Latch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 0.000 | 0.000 | tCL | RR | 4 | gw_gao_inst_0/u_icon_top/n31_s2/F |
| 0.413 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 3 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 10.000 | 0.000 | tCL | RR | 4 | gw_gao_inst_0/u_icon_top/n31_s2/F |
| 10.413 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_0_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | gw_gao_inst_0/u_icon_top/enable_reg_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.413, 51.887%; tC2Q: 0.382, 48.113% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 9.141 |
| Data Arrival Time | 1.207 |
| Data Required Time | 10.349 |
| From | gw_gao_inst_0/u_icon_top/enable_reg_2_s0 |
| To | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
| Launch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| Latch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 0.000 | 0.000 | tCL | RR | 4 | gw_gao_inst_0/u_icon_top/n31_s2/F |
| 0.413 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 3 | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 10.000 | 0.000 | tCL | RR | 4 | gw_gao_inst_0/u_icon_top/n31_s2/F |
| 10.413 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.413, 51.887%; tC2Q: 0.382, 48.113% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 17.880 |
| Data Arrival Time | 1.208 |
| Data Required Time | 19.088 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_pll_ok_d3_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_fabric_rstn_temp_s0 |
| Launch Clk | u_osc/OSCOUT.default_clk[R] |
| Latch Clk | u_osc/OSCOUT.default_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_osc/OSCOUT.default_clk | |||
| 0.000 | 0.000 | tCL | RR | 7 | u_osc/OSCOUT |
| 0.413 | 0.413 | tNET | RR | 1 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_pll_ok_d3_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_pll_ok_d3_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_fabric_rstn_temp_s0/RESET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 19.048 | 0.000 | u_osc/OSCOUT.default_clk | |||
| 19.048 | 0.000 | tCL | RR | 7 | u_osc/OSCOUT |
| 19.460 | 0.413 | tNET | RR | 1 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_fabric_rstn_temp_s0/CLK |
| 19.088 | -0.373 | tSu | 1 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_fabric_rstn_temp_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 19.048 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.413, 51.887%; tC2Q: 0.382, 48.113% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 18.189 |
| Data Arrival Time | 1.208 |
| Data Required Time | 19.396 |
| From | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/rstn_d3_s0 |
| To | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_fabric_rstn_temp_s0 |
| Launch Clk | u_osc/OSCOUT.default_clk[R] |
| Latch Clk | u_osc/OSCOUT.default_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_osc/OSCOUT.default_clk | |||
| 0.000 | 0.000 | tCL | RR | 7 | u_osc/OSCOUT |
| 0.413 | 0.413 | tNET | RR | 1 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/rstn_d3_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/rstn_d3_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_fabric_rstn_temp_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 19.048 | 0.000 | u_osc/OSCOUT.default_clk | |||
| 19.048 | 0.000 | tCL | RR | 7 | u_osc/OSCOUT |
| 19.460 | 0.413 | tNET | RR | 1 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_fabric_rstn_temp_s0/CLK |
| 19.396 | -0.064 | tSu | 1 | u_SerDes_Top/Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/serdes_fabric_rstn_temp_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 19.048 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.413, 51.887%; tC2Q: 0.382, 48.113% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |