Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\UARTTOBUS\data\uart_bus_core_encryption.v C:\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\UARTTOBUS\data\uart_to_bus_top.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-2 |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Jun 20 15:14:52 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Uart_to_Bus_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.401s, Peak memory usage = 49.781MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 49.781MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 49.781MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 49.781MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 49.781MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 49.781MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 49.781MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 49.781MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 49.781MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 49.781MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 49.781MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 49.781MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 61.047MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 61.047MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 61.047MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 61.047MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 318 |
| I/O Buf | 318 |
| IBUF | 102 |
| OBUF | 216 |
| Register | 659 |
| DFFRE | 12 |
| DFFPE | 9 |
| DFFCE | 638 |
| LUT | 658 |
| LUT2 | 123 |
| LUT3 | 115 |
| LUT4 | 420 |
| ALU | 40 |
| ALU | 40 |
| SSRAM | 25 |
| RAM16SDP4 | 25 |
| INV | 11 |
| INV | 11 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 859(669 LUTs, 40 ALUs, 25 SSRAMs) / 138240 | <1% |
| Register | 659 / 139140 | <1% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 659 / 139140 | <1% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_i_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_i | 100.0(MHz) | 197.2(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.928 |
| Data Arrival Time | 5.899 |
| Data Required Time | 10.828 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 684 | clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 24 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s63/I1 |
| 1.887 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s63/F |
| 2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s59/I3 |
| 2.495 | 0.371 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s59/F |
| 2.732 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s50/I1 |
| 3.287 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s50/F |
| 3.524 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s46/I1 |
| 4.079 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s46/F |
| 4.316 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s49/I1 |
| 4.871 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s49/F |
| 5.108 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n264_s43/I1 |
| 5.662 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n264_s43/F |
| 5.899 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 684 | clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.146, 62.458%; route: 1.659, 32.936%; tC2Q: 0.232, 4.606% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 4.966 |
| Data Arrival Time | 5.862 |
| Data Required Time | 10.828 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 684 | clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 24 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s63/I1 |
| 1.887 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s63/F |
| 2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s59/I3 |
| 2.495 | 0.371 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s59/F |
| 2.732 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s50/I1 |
| 3.287 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s50/F |
| 3.524 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s46/I1 |
| 4.079 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s46/F |
| 4.316 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s49/I1 |
| 4.871 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s49/F |
| 5.108 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n260_s44/I0 |
| 5.625 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n260_s44/F |
| 5.862 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 684 | clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.108, 62.172%; route: 1.659, 33.187%; tC2Q: 0.232, 4.641% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 4.966 |
| Data Arrival Time | 5.862 |
| Data Required Time | 10.828 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 684 | clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 24 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s63/I1 |
| 1.887 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s63/F |
| 2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s59/I3 |
| 2.495 | 0.371 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s59/F |
| 2.732 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s50/I1 |
| 3.287 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s50/F |
| 3.524 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s46/I1 |
| 4.079 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s46/F |
| 4.316 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s49/I1 |
| 4.871 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s49/F |
| 5.108 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n259_s43/I0 |
| 5.625 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n259_s43/F |
| 5.862 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 684 | clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.108, 62.172%; route: 1.659, 33.187%; tC2Q: 0.232, 4.641% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 5.638 |
| Data Arrival Time | 5.189 |
| Data Required Time | 10.828 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_33_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 684 | clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_33_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_33_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s65/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s65/F |
| 2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s61/I1 |
| 2.679 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s61/F |
| 2.916 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s52/I2 |
| 3.369 | 0.453 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s52/F |
| 3.606 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s46/I1 |
| 4.161 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s46/F |
| 4.398 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s45/I1 |
| 4.952 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s45/F |
| 5.189 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 684 | clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.673, 61.775%; route: 1.422, 32.863%; tC2Q: 0.232, 5.362% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 5.650 |
| Data Arrival Time | 5.178 |
| Data Required Time | 10.828 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_23_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 684 | clk_i_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_23_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_23_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s61/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s61/F |
| 2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s55/I1 |
| 2.679 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s55/F |
| 2.916 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s52/I0 |
| 3.433 | 0.517 | tINS | FF | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s52/F |
| 3.670 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s44/I0 |
| 4.187 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s44/F |
| 4.424 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s43/I0 |
| 4.941 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s43/F |
| 5.178 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 684 | clk_i_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.661, 61.668%; route: 1.422, 32.955%; tC2Q: 0.232, 5.377% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |