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	  Example JESD204B Design Read Me
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Object device:GW5AST-LV138FPG676AES
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File List:
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.
|-- doc
|   `-- Readme.txt                                       -->  Read Me file (this file)
|-- tb                                                   
|   `-- tb_top.v                                         -->  TestBench for example design
|   `-- prim_sim.v                                       -->  Gowin Simulation lib
|-- project                                              
|   `-- jesd204b_demo.gprj          	                 -->   GOWIN FPGA Designer Project File for Example Design
|   `-- jesd204b_demo.gprj.user                          -->   GOWIN FPGA Designer Project File for Example Design
|   |-- impl                                             
|   |   `-- project_process_config.json                  
|   |   |-- gwsynthesis                                  
|   |   |-- pnr                                            
|   |-- src                                              
|       `-- top.v                                        -->  File for  GOWIN FPGA Designer Project
|       `-- top.cst                                      -->  File for  GOWIN FPGA Designer Project
|       `-- top.rao                                      -->  File for  GOWIN FPGA Designer Project
|       `-- top.sdc                                      -->  File for  GOWIN FPGA Designer Project 
|       `-- sysreg.v                                     -->  File for  GOWIN FPGA Designer Project 
|       |-- gowin_pll                                    
|       |   `-- gowin_pll.v                              -->  File for  GOWIN FPGA Designer Project
|       |   `-- gowin_pll.mod                            -->  File for  GOWIN FPGA Designer Project
|       |   `-- gowin_pll.ipc                            -->  File for  GOWIN FPGA Designer Project
|       |   `-- gowin_pll_tmp.v                          -->  File for  GOWIN FPGA Designer Project
|       |-- serdes                                       
|       |   `-- serdes.csr                               -->  File for  GOWIN FPGA Designer Project
|       |   `-- serdes.ipc                               -->  File for  GOWIN FPGA Designer Project
|       |   `-- serdes.mod                               -->  File for  GOWIN FPGA Designer Project
|       |   `-- serdes.toml                              -->  File for  GOWIN FPGA Designer Project
|       |   `-- serdes.v                                 -->  File for  GOWIN FPGA Designer Project
|       |   `-- serdes_temp.csr                          -->  File for  GOWIN FPGA Designer Project
|       |   `-- serdes_temp.toml                         -->  File for  GOWIN FPGA Designer Project
|       |   `-- serdes_tmp.v                             -->  File for  GOWIN FPGA Designer Project
|       |   |-- jesd204b                                 
|       |   |   `-- jesd204b.ipc                         -->  File for  GOWIN FPGA Designer Project
|       |   |   `-- jesd204b.v                           -->  File for  GOWIN FPGA Designer Project
|       |   |   `-- jesd204b.vo                          -->  File for  GOWIN FPGA Designer Project
|       |   |   `-- jesd204b_tmp.v                       -->  File for  GOWIN FPGA Designer Project
|       |   |   |-- temp                      
|       |-- dds          
|       |   `-- cos_sin_table.v                          -->  File for  GOWIN FPGA Designer Project
|       |-- uart_to_bus          
|       |   `-- uart_to_bus.ipc                          -->  File for  GOWIN FPGA Designer Project
|       |   `-- uart_to_bus.v                            -->  File for  GOWIN FPGA Designer Project
|       |   `-- uart_to_bus.vo                           -->  File for  GOWIN FPGA Designer Project
|       |   `-- uart_to_bus_tmp.v                        -->  File for  GOWIN FPGA Designer Project
|-- simulation
|   |-- Modelsim                                   
|       `-- cmd.do          	                         -->  File for Simulation 
|       `-- do.bat                                       -->  File for Simulation
|-- tool
|   `-- teraterm.rar                                     -->  Tera Term setup file 
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HOW TO OPEN A PROJECT IN  GOWIN FPGA Designer:
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1. Unzip the respective design files.
2. Launch  GOWIN FPGA Designer and select "File -> Open -> Project"
3. In the Open Project dialog, enter the Project location -- "project",select the project"jesd204b_demo.gprj".
4. Click Finish. Now the project is successfully loaded. 

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HOW TO RUN SYNTHESIZE, PLACE AND ROUTE, IP CORE GENERATION, AND TIMING ANALYSIS IN  GOWIN FPGA Designer:
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1. Click the Process tab in the process panel of the  GOWIN FPGA Designer dashboard. 
   Double click on Synthsize. This will bring the design through synthesis.
2. Click the Process tab in the process panel of the  GOWIN FPGA Designer dashboard. 
   Double click on Place & Route. This will bring the design through mapping, place and route.
3. Once Place & Route is done, user can double click on Timing Analysis Report to get 
   the timing analysis result.
4. Click on "Project -> Configuration -> Place & Route" to configurate the Post-Place File 
   and SDF File of the design.
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HOW TO RUN SIMULATION
1. User can run functional simulation by software Modelsim. 
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HOW TO  GENERATE IP CORE
1. Click the IP Core Generator tab in the Window panel of the  GOWIN FPGA Designer dashboard.
   Double click on "Serdes",Select protocol "JESD204B",then click Create. This will generate the IP Core for the design.
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