Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\SERDES_IP\IPlib\JESD204B\data\jesd204b_core_encryption.v
C:\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\SERDES_IP\IPlib\JESD204B\data\jesd204b_top.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-2
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Fri Jun 30 10:33:49 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module JESD204B_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.968s, Elapsed time = 0h 0m 0.989s, Peak memory usage = 87.695MB
Running netlist conversion:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.129s, Peak memory usage = 87.695MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.818s, Peak memory usage = 87.695MB
    Optimizing Phase 1: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.281s, Peak memory usage = 87.695MB
    Optimizing Phase 2: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.746s, Peak memory usage = 87.695MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.247s, Peak memory usage = 87.695MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 87.695MB
    Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 87.695MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 87.695MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.82s, Peak memory usage = 87.695MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.144s, Peak memory usage = 87.695MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.193s, Peak memory usage = 87.695MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 14s, Elapsed time = 0h 0m 14s, Peak memory usage = 98.047MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.921s, Elapsed time = 0h 0m 0.912s, Peak memory usage = 98.047MB
Generate output files:
    CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 1s, Peak memory usage = 99.578MB
Total Time and Memory Usage CPU time = 0h 0m 20s, Elapsed time = 0h 0m 20s, Peak memory usage = 99.578MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 969
I/O Buf 793
    IBUF 258
    OBUF 535
Register 4288
    DFFSE 65
    DFFRE 4223
LUT 4748
    LUT2 573
    LUT3 1802
    LUT4 2373
ALU 1032
    ALU 1032
SSRAM 39
    RAM16S4 1
    RAM16SDP4 38
INV 97
    INV 97
BSRAM 2
    SDPX9B 2

Resource Utilization Summary

Resource Usage Utilization
Logic 6111(4845 LUTs, 1032 ALUs, 39 SSRAMs) / 138240 5%
Register 4288 / 139140 4%
  --Register as Latch 0 / 139140 0%
  --Register as FF 4288 / 139140 4%
BSRAM 2 / 340 <1%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
tx_core_clk_i Base 10.000 100.0 0.000 5.000 tx_core_clk_i_ibuf/I
tx_cfg_clk_i Base 10.000 100.0 0.000 5.000 tx_cfg_clk_i_ibuf/I
rx_core_clk_i Base 10.000 100.0 0.000 5.000 rx_core_clk_i_ibuf/I
rx_cfg_clk_i Base 10.000 100.0 0.000 5.000 rx_cfg_clk_i_ibuf/I
u_jesd204b_core/u1.u_jesd204b_tx/u_tx_lmfc_ctrl/n7_6 Base 10.000 100.0 0.000 5.000 u_jesd204b_core/u1.u_jesd204b_tx/u_tx_lmfc_ctrl/n7_s2/O
u_jesd204b_core/u2.u_jesd204b_rx/u_rx_lmfc_ctrl/n6_6 Base 10.000 100.0 0.000 5.000 u_jesd204b_core/u2.u_jesd204b_rx/u_rx_lmfc_ctrl/n6_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 tx_core_clk_i 100.0(MHz) 227.9(MHz) 6 TOP
2 tx_cfg_clk_i 100.0(MHz) 247.5(MHz) 7 TOP
3 rx_core_clk_i 100.0(MHz) 225.9(MHz) 6 TOP
4 rx_cfg_clk_i 100.0(MHz) 243.8(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.849
Data Arrival Time 12.642
Data Required Time 10.793
From u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0
To u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_7_s1
Launch Clk tx_cfg_clk_i[R]
Latch Clk tx_core_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 tx_cfg_clk_i
0.000 0.000 tCL RR 1 tx_cfg_clk_i_ibuf/I
0.683 0.683 tINS RR 213 tx_cfg_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0/CLK
1.095 0.232 tC2Q RF 6 u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0/Q
1.332 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n125_s/I1
1.901 0.570 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n125_s/COUT
1.901 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s/CIN
1.937 0.035 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s/COUT
1.937 0.000 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s/CIN
2.407 0.470 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s/SUM
2.644 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s0/I0
3.193 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s0/COUT
3.193 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n122_s0/CIN
3.663 0.470 tINS RF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n122_s0/SUM
3.900 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s0/I0
4.449 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s0/COUT
4.449 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s0/CIN
4.919 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s0/SUM
5.156 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s6/I0
5.705 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s6/COUT
5.705 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s6/CIN
6.175 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s6/SUM
6.412 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s9/I0
6.961 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s9/COUT
6.961 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s9/CIN
7.431 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s9/SUM
7.668 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s11/I0
8.217 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s11/COUT
8.217 0.000 tNET RR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_7_s11/CIN
8.687 0.470 tINS RF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_7_s11/SUM
8.924 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n646_s5/I1
9.479 0.555 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n646_s5/F
9.716 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n646_s4/I1
10.271 0.555 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n646_s4/F
10.508 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n646_s3/I2
10.961 0.453 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n646_s3/F
11.198 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n646_s1/I2
11.651 0.453 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n646_s1/F
11.888 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n646_s0/I0
12.405 0.517 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n646_s0/F
12.642 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_7_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 tx_core_clk_i
10.000 0.000 tCL RR 1 tx_core_clk_i_ibuf/I
10.682 0.683 tINS RR 1122 tx_core_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_7_s1/CLK
10.828 -0.035 tUnc u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_7_s1
10.793 -0.035 tSu 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.703, 73.886%; route: 2.844, 24.144%; tC2Q: 0.232, 1.970%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack -1.811
Data Arrival Time 12.604
Data Required Time 10.793
From u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0
To u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_7_s1
Launch Clk tx_cfg_clk_i[R]
Latch Clk tx_core_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 tx_cfg_clk_i
0.000 0.000 tCL RR 1 tx_cfg_clk_i_ibuf/I
0.683 0.683 tINS RR 213 tx_cfg_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0/CLK
1.095 0.232 tC2Q RF 6 u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0/Q
1.332 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n125_s/I1
1.901 0.570 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n125_s/COUT
1.901 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s/CIN
1.937 0.035 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s/COUT
1.937 0.000 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s/CIN
2.407 0.470 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s/SUM
2.644 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s0/I0
3.193 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s0/COUT
3.193 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n122_s0/CIN
3.663 0.470 tINS RF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n122_s0/SUM
3.900 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s0/I0
4.449 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s0/COUT
4.449 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s0/CIN
4.919 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s0/SUM
5.156 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s6/I0
5.705 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s6/COUT
5.705 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s6/CIN
6.175 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s6/SUM
6.412 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s9/I0
6.961 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s9/COUT
6.961 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s9/CIN
7.431 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s9/SUM
7.668 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s11/I0
8.217 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s11/COUT
8.217 0.000 tNET RR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_7_s11/CIN
8.687 0.470 tINS RF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_7_s11/SUM
8.924 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n646_s5/I1
9.479 0.555 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n646_s5/F
9.716 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n646_s4/I0
10.233 0.517 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n646_s4/F
10.470 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n646_s3/I2
10.923 0.453 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n646_s3/F
11.160 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n646_s1/I2
11.613 0.453 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n646_s1/F
11.850 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n646_s0/I0
12.367 0.517 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n646_s0/F
12.604 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_7_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 tx_core_clk_i
10.000 0.000 tCL RR 1 tx_core_clk_i_ibuf/I
10.682 0.683 tINS RR 1122 tx_core_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_7_s1/CLK
10.828 -0.035 tUnc u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_7_s1
10.793 -0.035 tSu 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.665, 73.802%; route: 2.844, 24.222%; tC2Q: 0.232, 1.976%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack -1.185
Data Arrival Time 11.978
Data Required Time 10.793
From u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0
To u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte1_7_s1
Launch Clk tx_cfg_clk_i[R]
Latch Clk tx_core_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 tx_cfg_clk_i
0.000 0.000 tCL RR 1 tx_cfg_clk_i_ibuf/I
0.683 0.683 tINS RR 213 tx_cfg_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0/CLK
1.095 0.232 tC2Q RF 6 u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0/Q
1.332 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n125_s/I1
1.901 0.570 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n125_s/COUT
1.901 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s/CIN
1.937 0.035 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s/COUT
1.937 0.000 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s/CIN
2.407 0.470 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s/SUM
2.644 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s0/I0
3.193 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s0/COUT
3.193 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n122_s0/CIN
3.663 0.470 tINS RF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n122_s0/SUM
3.900 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s0/I0
4.449 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s0/COUT
4.449 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s0/CIN
4.919 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s0/SUM
5.156 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s6/I0
5.705 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s6/COUT
5.705 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s6/CIN
6.175 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s6/SUM
6.412 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s9/I0
6.961 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s9/COUT
6.961 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s9/CIN
7.431 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s9/SUM
7.668 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s11/I0
8.217 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s11/COUT
8.217 0.000 tNET RR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_7_s11/CIN
8.687 0.470 tINS RF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_7_s11/SUM
8.924 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n500_s7/I0
9.441 0.517 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n500_s7/F
9.678 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n500_s3/I0
10.195 0.517 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n500_s3/F
10.432 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n500_s1/I1
10.987 0.555 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n500_s1/F
11.224 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n500_s0/I0
11.741 0.517 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n500_s0/F
11.978 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte1_7_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 tx_core_clk_i
10.000 0.000 tCL RR 1 tx_core_clk_i_ibuf/I
10.682 0.683 tINS RR 1122 tx_core_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte1_7_s1/CLK
10.828 -0.035 tUnc u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte1_7_s1
10.793 -0.035 tSu 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte1_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.276, 74.459%; route: 2.607, 23.454%; tC2Q: 0.232, 2.087%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack -1.124
Data Arrival Time 11.917
Data Required Time 10.793
From u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0
To u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_6_s1
Launch Clk tx_cfg_clk_i[R]
Latch Clk tx_core_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 tx_cfg_clk_i
0.000 0.000 tCL RR 1 tx_cfg_clk_i_ibuf/I
0.683 0.683 tINS RR 213 tx_cfg_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0/CLK
1.095 0.232 tC2Q RF 6 u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0/Q
1.332 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n125_s/I1
1.901 0.570 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n125_s/COUT
1.901 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s/CIN
2.372 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s/SUM
2.609 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s0/I0
3.158 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s0/COUT
3.158 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s0/CIN
3.628 0.470 tINS RF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s0/SUM
3.865 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_2_s0/I0
4.413 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_2_s0/COUT
4.413 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s0/CIN
4.883 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s0/SUM
5.120 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s6/I0
5.669 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s6/COUT
5.669 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s6/CIN
6.139 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s6/SUM
6.376 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s9/I0
6.925 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s9/COUT
6.925 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s9/CIN
7.395 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s9/SUM
7.632 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s11/I0
8.181 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s11/COUT
8.181 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s11/CIN
8.651 0.470 tINS RF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s11/SUM
8.888 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n647_s4/I1
9.443 0.555 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n647_s4/F
9.681 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n647_s3/I0
10.198 0.517 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n647_s3/F
10.435 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n647_s1/I2
10.888 0.453 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n647_s1/F
11.125 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n647_s0/I1
11.680 0.555 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/n647_s0/F
11.917 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 tx_core_clk_i
10.000 0.000 tCL RR 1 tx_core_clk_i_ibuf/I
10.682 0.683 tINS RR 1122 tx_core_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_6_s1/CLK
10.828 -0.035 tUnc u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_6_s1
10.793 -0.035 tSu 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[1].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.215, 74.317%; route: 2.607, 23.584%; tC2Q: 0.232, 2.099%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack -1.124
Data Arrival Time 11.917
Data Required Time 10.793
From u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0
To u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_6_s1
Launch Clk tx_cfg_clk_i[R]
Latch Clk tx_core_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 tx_cfg_clk_i
0.000 0.000 tCL RR 1 tx_cfg_clk_i_ibuf/I
0.683 0.683 tINS RR 213 tx_cfg_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0/CLK
1.095 0.232 tC2Q RF 6 u_jesd204b_core/u1.u_jesd204b_tx/u_tx_local2reg/o_ilas_cfg_bid_0_s0/Q
1.332 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n125_s/I1
1.901 0.570 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n125_s/COUT
1.901 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s/CIN
2.372 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s/SUM
2.609 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s0/I0
3.158 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n124_s0/COUT
3.158 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s0/CIN
3.628 0.470 tINS RF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n123_s0/SUM
3.865 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_2_s0/I0
4.413 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_2_s0/COUT
4.413 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s0/CIN
4.883 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s0/SUM
5.120 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s6/I0
5.669 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_3_s6/COUT
5.669 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s6/CIN
6.139 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s6/SUM
6.376 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s9/I0
6.925 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_4_s9/COUT
6.925 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s9/CIN
7.395 0.470 tINS RF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s9/SUM
7.632 0.237 tNET FF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s11/I0
8.181 0.549 tINS FR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_5_s11/COUT
8.181 0.000 tNET RR 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s11/CIN
8.651 0.470 tINS RF 2 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/cfg_data_field[13]_6_s11/SUM
8.888 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n647_s4/I1
9.443 0.555 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n647_s4/F
9.681 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n647_s3/I1
10.236 0.555 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n647_s3/F
10.473 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n647_s1/I2
10.926 0.453 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n647_s1/F
11.163 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n647_s0/I0
11.680 0.517 tINS FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/n647_s0/F
11.917 0.237 tNET FF 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 tx_core_clk_i
10.000 0.000 tCL RR 1 tx_core_clk_i_ibuf/I
10.682 0.683 tINS RR 1122 tx_core_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_6_s1/CLK
10.828 -0.035 tUnc u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_6_s1
10.793 -0.035 tSu 1 u_jesd204b_core/u1.u_jesd204b_tx/tx_lane[0].u_jesd204b_tx_lane/u_tx_ilas/ilas_byte3_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.215, 74.317%; route: 2.607, 23.584%; tC2Q: 0.232, 2.099%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%