Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.8.11\IDE\ipcore\Adder_Subtractor\data\adder_subtractor_wrap.v
C:\Gowin\Gowin_V1.9.8.11\IDE\ipcore\Adder_Subtractor\data\adder_subtractor.v
C:\Gowin\Gowin_V1.9.8.11\IDE\ipcore\Adder_Subtractor\data\static_macro_define.v
GowinSynthesis Constraints File ---
Version V1.9.8.11
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Created Time Wed Mar 01 08:59:37 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Adder_Subtractor_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.249s, Peak memory usage = 44.395MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 44.395MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 44.395MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 44.395MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 44.395MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 44.395MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 44.395MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 44.395MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 44.395MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 44.395MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 44.395MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 44.395MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.331s, Peak memory usage = 54.359MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 54.359MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 54.359MB
Total Time and Memory Usage CPU time = 0h 0m 0.653s, Elapsed time = 0h 0m 0.648s, Peak memory usage = 54.359MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 52
I/O Buf 52
    IBUF 34
    OBUF 18
Register 166
    DFF 4
    DFFC 153
    DFFCE 9
LUT 61
    LUT2 8
    LUT3 23
    LUT4 30
SSRAM 4
    RAM16S4 4
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 86(62 LUTs, 0 ALUs, 4 SSRAMs) / 54720 <1%
Register 166 / 41997 <1%
  --Register as Latch 0 / 41997 0%
  --Register as FF 166 / 41997 <1%
BSRAM 0 / 140 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 199.4(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.986
Data Arrival Time 5.841
Data Required Time 10.828
From adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4
To adder_subtractor_inst/adder_loop[10].u_adder_loop/cout_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 170 clk_ibuf/O
0.863 0.180 tNET RR 1 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/CLK
1.095 0.232 tC2Q RF 22 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/Q
1.332 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/I1
1.887 0.555 tINS FF 9 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/F
2.124 0.237 tNET FF 4 adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/AD[0]
2.641 0.517 tINS FF 2 adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/DO[2]
2.878 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/I1
3.433 0.555 tINS FF 3 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/F
3.670 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s1/I2
4.122 0.453 tINS FF 2 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s1/F
4.359 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/reg_result_5_s0/I2
4.813 0.453 tINS FF 2 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/reg_result_5_s0/F
5.049 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/temp_6_s/I1
5.604 0.555 tINS FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/temp_6_s/F
5.841 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/cout_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 170 clk_ibuf/O
10.863 0.180 tNET RR 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/cout_s0/CLK
10.828 -0.035 tSu 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/cout_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.088, 62.020%; route: 1.659, 33.320%; tC2Q: 0.232, 4.660%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 4.986
Data Arrival Time 5.841
Data Required Time 10.828
From adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4
To adder_subtractor_inst/adder_loop[10].u_adder_loop/result_13_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 170 clk_ibuf/O
0.863 0.180 tNET RR 1 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/CLK
1.095 0.232 tC2Q RF 22 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/Q
1.332 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/I1
1.887 0.555 tINS FF 9 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/F
2.124 0.237 tNET FF 4 adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/AD[0]
2.641 0.517 tINS FF 2 adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/DO[2]
2.878 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/I1
3.433 0.555 tINS FF 3 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/F
3.670 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[2].u_full_adder/reg_result_2_s0/I2
4.122 0.453 tINS FF 2 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[2].u_full_adder/reg_result_2_s0/F
4.359 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[3].u_full_adder/reg_result_3_s0/I1
4.914 0.555 tINS FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[3].u_full_adder/reg_result_3_s0/F
5.151 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[3].u_full_adder/reg_result_3_s/I2
5.604 0.453 tINS FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[3].u_full_adder/reg_result_3_s/F
5.841 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/result_13_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 170 clk_ibuf/O
10.863 0.180 tNET RR 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/result_13_s0/CLK
10.828 -0.035 tSu 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/result_13_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.088, 62.020%; route: 1.659, 33.320%; tC2Q: 0.232, 4.660%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 5.024
Data Arrival Time 5.804
Data Required Time 10.828
From adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4
To adder_subtractor_inst/adder_loop[10].u_adder_loop/result_15_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 170 clk_ibuf/O
0.863 0.180 tNET RR 1 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/CLK
1.095 0.232 tC2Q RF 22 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/Q
1.332 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/I1
1.887 0.555 tINS FF 9 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/F
2.124 0.237 tNET FF 4 adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/AD[0]
2.641 0.517 tINS FF 2 adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/DO[2]
2.878 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/I1
3.433 0.555 tINS FF 3 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/F
3.670 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s1/I2
4.122 0.453 tINS FF 2 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s1/F
4.359 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/reg_result_5_s0/I2
4.813 0.453 tINS FF 2 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/reg_result_5_s0/F
5.049 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/reg_result_5_s/I0
5.567 0.517 tINS FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/reg_result_5_s/F
5.804 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/result_15_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 170 clk_ibuf/O
10.863 0.180 tNET RR 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/result_15_s0/CLK
10.828 -0.035 tSu 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/result_15_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.050, 61.729%; route: 1.659, 33.576%; tC2Q: 0.232, 4.695%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 5.106
Data Arrival Time 5.721
Data Required Time 10.828
From adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4
To adder_subtractor_inst/adder_loop[10].u_adder_loop/result_14_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 170 clk_ibuf/O
0.863 0.180 tNET RR 1 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/CLK
1.095 0.232 tC2Q RF 22 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/Q
1.332 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/I1
1.887 0.555 tINS FF 9 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/F
2.124 0.237 tNET FF 4 adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/AD[0]
2.641 0.517 tINS FF 2 adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/DO[2]
2.878 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/I1
3.433 0.555 tINS FF 3 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/F
3.670 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s1/I2
4.122 0.453 tINS FF 2 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s1/F
4.359 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s0/I0
4.877 0.517 tINS FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s0/F
5.114 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s/I3
5.484 0.371 tINS FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s/F
5.721 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/result_14_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 170 clk_ibuf/O
10.863 0.180 tNET RR 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/result_14_s0/CLK
10.828 -0.035 tSu 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/result_14_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.968, 61.082%; route: 1.659, 34.143%; tC2Q: 0.232, 4.775%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 5.778
Data Arrival Time 5.049
Data Required Time 10.828
From adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4
To adder_subtractor_inst/adder_loop[10].u_adder_loop/result_12_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 170 clk_ibuf/O
0.863 0.180 tNET RR 1 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/CLK
1.095 0.232 tC2Q RF 22 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/Q
1.332 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/I1
1.887 0.555 tINS FF 9 adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/F
2.124 0.237 tNET FF 4 adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/AD[0]
2.641 0.517 tINS FF 2 adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/DO[2]
2.878 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/I1
3.433 0.555 tINS FF 3 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/F
3.670 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[2].u_full_adder/reg_result_2_s0/I2
4.122 0.453 tINS FF 2 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[2].u_full_adder/reg_result_2_s0/F
4.359 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[2].u_full_adder/reg_result_2_s/I2
4.813 0.453 tINS FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[2].u_full_adder/reg_result_2_s/F
5.049 0.237 tNET FF 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/result_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 170 clk_ibuf/O
10.863 0.180 tNET RR 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/result_12_s0/CLK
10.828 -0.035 tSu 1 adder_subtractor_inst/adder_loop[10].u_adder_loop/result_12_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.533, 60.497%; route: 1.422, 33.962%; tC2Q: 0.232, 5.541%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%