Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\1.9.8.11\Gowin_Adder_Subtractor\Gowin_Adder_Subtractor_RefDesign\proj\src\adder_subtractor\adder_subtractor.v
E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\1.9.8.11\Gowin_Adder_Subtractor\Gowin_Adder_Subtractor_RefDesign\proj\src\gw2a_top.v
C:\Gowin\Gowin_V1.9.8.11\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.8.11\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.8.11\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.8.11\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.8.11\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.8.11\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\1.9.8.11\Gowin_Adder_Subtractor\Gowin_Adder_Subtractor_RefDesign\proj\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Version V1.9.8.11
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Created Time Wed Mar 01 10:27:10 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw2a_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.572s, Peak memory usage = 704.250MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 704.250MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 704.250MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 704.250MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 704.250MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 704.250MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 704.250MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 704.250MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 704.250MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 704.250MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 704.250MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 704.250MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 704.250MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 704.250MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 2s, Peak memory usage = 704.250MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 56
I/O Buf 56
    IBUF 5
    OBUF 51
Register 564
    DFF 39
    DFFP 1
    DFFPE 33
    DFFC 199
    DFFCE 286
    DFFNP 2
    DFFNC 4
LUT 477
    LUT2 65
    LUT3 128
    LUT4 284
MUX 1
    MUX16 1
ALU 17
    ALU 17
SSRAM 14
    RAM16S4 14
INV 5
    INV 5
BSRAM 3
    SDPB 2
    pROM 1
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 591(490 LUTs, 17 ALUs, 14 SSRAMs) / 54720 2%
Register 564 / 41997 2%
  --Register as Latch 0 / 41997 0%
  --Register as FF 564 / 41997 2%
BSRAM 3 / 140 3%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 199.4(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.986
Data Arrival Time 5.841
Data Required Time 10.828
From Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4
To Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/cout_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 284 clk_ibuf/O
0.863 0.180 tNET RR 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/CLK
1.095 0.232 tC2Q RF 22 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/Q
1.332 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/I1
1.887 0.555 tINS FF 9 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/F
2.124 0.237 tNET FF 4 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/AD[0]
2.641 0.517 tINS FF 2 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/DO[2]
2.878 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/I1
3.433 0.555 tINS FF 3 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/F
3.670 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s1/I2
4.122 0.453 tINS FF 2 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s1/F
4.359 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/reg_result_5_s0/I2
4.813 0.453 tINS FF 2 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/reg_result_5_s0/F
5.049 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/temp_6_s/I1
5.604 0.555 tINS FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/temp_6_s/F
5.841 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/cout_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 284 clk_ibuf/O
10.863 0.180 tNET RR 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/cout_s0/CLK
10.828 -0.035 tSu 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/cout_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.088, 62.020%; route: 1.659, 33.320%; tC2Q: 0.232, 4.660%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 4.986
Data Arrival Time 5.841
Data Required Time 10.828
From Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4
To Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_13_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 284 clk_ibuf/O
0.863 0.180 tNET RR 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/CLK
1.095 0.232 tC2Q RF 22 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/Q
1.332 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/I1
1.887 0.555 tINS FF 9 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/F
2.124 0.237 tNET FF 4 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/AD[0]
2.641 0.517 tINS FF 2 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/DO[2]
2.878 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/I1
3.433 0.555 tINS FF 3 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/F
3.670 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[2].u_full_adder/reg_result_2_s0/I2
4.122 0.453 tINS FF 2 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[2].u_full_adder/reg_result_2_s0/F
4.359 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[3].u_full_adder/reg_result_3_s0/I1
4.914 0.555 tINS FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[3].u_full_adder/reg_result_3_s0/F
5.151 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[3].u_full_adder/reg_result_3_s/I2
5.604 0.453 tINS FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[3].u_full_adder/reg_result_3_s/F
5.841 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_13_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 284 clk_ibuf/O
10.863 0.180 tNET RR 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_13_s0/CLK
10.828 -0.035 tSu 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_13_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.088, 62.020%; route: 1.659, 33.320%; tC2Q: 0.232, 4.660%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 5.024
Data Arrival Time 5.804
Data Required Time 10.828
From Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4
To Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_15_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 284 clk_ibuf/O
0.863 0.180 tNET RR 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/CLK
1.095 0.232 tC2Q RF 22 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/Q
1.332 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/I1
1.887 0.555 tINS FF 9 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/F
2.124 0.237 tNET FF 4 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/AD[0]
2.641 0.517 tINS FF 2 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/DO[2]
2.878 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/I1
3.433 0.555 tINS FF 3 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/F
3.670 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s1/I2
4.122 0.453 tINS FF 2 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s1/F
4.359 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/reg_result_5_s0/I2
4.813 0.453 tINS FF 2 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/reg_result_5_s0/F
5.049 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/reg_result_5_s/I0
5.567 0.517 tINS FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[5].u_full_adder/reg_result_5_s/F
5.804 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_15_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 284 clk_ibuf/O
10.863 0.180 tNET RR 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_15_s0/CLK
10.828 -0.035 tSu 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_15_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.050, 61.729%; route: 1.659, 33.576%; tC2Q: 0.232, 4.695%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 5.106
Data Arrival Time 5.721
Data Required Time 10.828
From Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4
To Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_14_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 284 clk_ibuf/O
0.863 0.180 tNET RR 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/CLK
1.095 0.232 tC2Q RF 22 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/Q
1.332 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/I1
1.887 0.555 tINS FF 9 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/F
2.124 0.237 tNET FF 4 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/AD[0]
2.641 0.517 tINS FF 2 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/DO[2]
2.878 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/I1
3.433 0.555 tINS FF 3 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/F
3.670 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s1/I2
4.122 0.453 tINS FF 2 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s1/F
4.359 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s0/I0
4.877 0.517 tINS FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s0/F
5.114 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s/I3
5.484 0.371 tINS FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[4].u_full_adder/reg_result_4_s/F
5.721 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_14_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 284 clk_ibuf/O
10.863 0.180 tNET RR 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_14_s0/CLK
10.828 -0.035 tSu 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_14_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.968, 61.082%; route: 1.659, 34.143%; tC2Q: 0.232, 4.775%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 5.778
Data Arrival Time 5.049
Data Required Time 10.828
From Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4
To Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_12_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 284 clk_ibuf/O
0.863 0.180 tNET RR 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/CLK
1.095 0.232 tC2Q RF 22 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s4/Q
1.332 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/I1
1.887 0.555 tINS FF 9 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/data_a_pipe[1]_8_s101/F
2.124 0.237 tNET FF 4 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/AD[0]
2.641 0.517 tINS FF 2 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[1].u_adder_loop/out_a_8_s4/DO[2]
2.878 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/I1
3.433 0.555 tINS FF 3 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[1].u_full_adder/reg_result_1_s0/F
3.670 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[2].u_full_adder/reg_result_2_s0/I2
4.122 0.453 tINS FF 2 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[2].u_full_adder/reg_result_2_s0/F
4.359 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[2].u_full_adder/reg_result_2_s/I2
4.813 0.453 tINS FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/full_adder[2].u_full_adder/reg_result_2_s/F
5.049 0.237 tNET FF 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 284 clk_ibuf/O
10.863 0.180 tNET RR 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_12_s0/CLK
10.828 -0.035 tSu 1 Adder_Subtractor_Top_inst/adder_subtractor_inst/adder_loop[10].u_adder_loop/result_12_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.533, 60.497%; route: 1.422, 33.962%; tC2Q: 0.232, 5.541%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%