Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\SPIFlashInterface\data\spi_flash_interface_top.v
D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\SPIFlashInterface\data\spiflash.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.10
Part Number GW1NSR-LV4CQN48PC7/I6
Device GW1NSR-4
Device Version C
Created Time Tue Dec 13 10:31:12 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module SPI_Flash_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.406s, Peak memory usage = 44.199MB
Running netlist conversion:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 44.199MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 44.199MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 44.199MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 44.199MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 44.199MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 44.199MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 44.199MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 44.199MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 44.199MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 44.199MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 44.199MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 57.348MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.157s, Peak memory usage = 57.348MB
Generate output files:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.095s, Peak memory usage = 57.348MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 5s, Peak memory usage = 57.348MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 110
I/O Buf 83
    IBUF 44
    OBUF 37
    IOBUF 2
Register 366
    DFF 2
    DFFP 8
    DFFPE 17
    DFFC 89
    DFFCE 245
    DFFNC 1
    DFFNCE 2
    DL 1
    DLN 1
LUT 728
    LUT2 60
    LUT3 181
    LUT4 487
ALU 65
    ALU 65
INV 7
    INV 7
BSRAM 2
    SDPB 2

Resource Utilization Summary

Resource Usage Utilization
Logic 800(735 LUTs, 65 ALUs) / 4608 18%
Register 366 / 3570 11%
  --Register as Latch 2 / 3570 <1%
  --Register as FF 364 / 3570 11%
BSRAM 2 / 10 20%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_pclk Base 20.000 50.0 0.000 10.000 I_pclk_ibuf/I
I_spi_clock Base 20.000 50.0 0.000 10.000 I_spi_clock_ibuf/I
O_flash_ck_d Base 20.000 50.0 0.000 10.000 spiflash_inst/u_spi_spiif/O_flash_ck_d_s/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_pclk 50.0(MHz) 129.8(MHz) 7 TOP
2 I_spi_clock 50.0(MHz) 58.2(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.269
Data Arrival Time 9.490
Data Required Time 10.759
From spiflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0
To spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1
Launch Clk I_pclk[F]
Latch Clk I_spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_pclk
0.000 0.000 tCL RR 1 I_pclk_ibuf/I
0.728 0.728 tINS RR 209 I_pclk_ibuf/O
0.997 0.269 tNET RR 1 spiflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
1.336 0.340 tC2Q RF 3 spiflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.692 0.356 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s16/I1
2.466 0.774 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s16/COUT
2.466 0.000 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s17/CIN
2.508 0.042 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s17/COUT
2.508 0.000 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s18/CIN
2.551 0.042 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s18/COUT
2.551 0.000 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s19/CIN
2.593 0.042 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s19/COUT
2.593 0.000 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s20/CIN
2.635 0.042 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s20/COUT
2.635 0.000 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s21/CIN
2.677 0.042 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s21/COUT
2.677 0.000 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s22/CIN
2.720 0.042 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s22/COUT
3.075 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/period_cnt_r_7_s5/I1
3.890 0.814 tINS FF 2 spiflash_inst/u_spi_spiif/period_cnt_r_7_s5/F
4.245 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_ns_2_s14/I2
4.854 0.609 tINS FF 6 spiflash_inst/u_spi_spiif/spi_ns_2_s14/F
5.210 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_ns_2_s10/I1
6.024 0.814 tINS FF 5 spiflash_inst/u_spi_spiif/spi_ns_2_s10/F
6.380 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_ns_2_s8/I1
7.195 0.814 tINS FF 8 spiflash_inst/u_spi_spiif/spi_ns_2_s8/F
7.550 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/master_clk_en_s4/I0
8.315 0.765 tINS FF 3 spiflash_inst/u_spi_spiif/master_clk_en_s4/F
8.671 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/master_clk_en_s0/I3
9.134 0.464 tINS FF 2 spiflash_inst/u_spi_spiif/master_clk_en_s0/F
9.490 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_spi_clock
10.000 0.000 tCL FF 1 I_spi_clock_ibuf/I
10.729 0.729 tINS FF 160 I_spi_clock_ibuf/O
11.085 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1/CLK
11.055 -0.030 tUnc spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1
10.759 -0.296 tSu 1 spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 5.309, 62.500%; route: 2.845, 33.501%; tC2Q: 0.340, 3.999%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 2

Path Summary:
Slack 5.296
Data Arrival Time 15.374
Data Required Time 20.670
From spiflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0
To spiflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0
Launch Clk I_pclk[R]
Latch Clk I_spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_pclk
0.000 0.000 tCL RR 1 I_pclk_ibuf/I
0.728 0.728 tINS RR 209 I_pclk_ibuf/O
0.997 0.269 tNET RR 1 spiflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
1.336 0.340 tC2Q RF 3 spiflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.692 0.356 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s16/I1
2.466 0.774 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s16/COUT
2.466 0.000 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s17/CIN
2.508 0.042 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s17/COUT
2.508 0.000 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s18/CIN
2.551 0.042 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s18/COUT
2.551 0.000 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s19/CIN
2.593 0.042 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s19/COUT
2.593 0.000 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s20/CIN
2.635 0.042 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s20/COUT
2.635 0.000 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s21/CIN
2.677 0.042 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s21/COUT
2.677 0.000 tNET FF 2 spiflash_inst/u_spi_spiif/n149_s22/CIN
2.720 0.042 tINS FF 1 spiflash_inst/u_spi_spiif/n149_s22/COUT
3.075 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/period_cnt_r_7_s5/I1
3.890 0.814 tINS FF 2 spiflash_inst/u_spi_spiif/period_cnt_r_7_s5/F
4.245 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_ns_2_s14/I2
4.854 0.609 tINS FF 6 spiflash_inst/u_spi_spiif/spi_ns_2_s14/F
5.210 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_ns_2_s10/I1
6.024 0.814 tINS FF 5 spiflash_inst/u_spi_spiif/spi_ns_2_s10/F
6.380 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_ns_2_s8/I1
7.195 0.814 tINS FF 8 spiflash_inst/u_spi_spiif/spi_ns_2_s8/F
7.550 0.356 tNET FF 1 spiflash_inst/u_spi_ctrl/data_cnt_r_8_s6/I0
8.315 0.765 tINS FF 5 spiflash_inst/u_spi_ctrl/data_cnt_r_8_s6/F
8.671 0.356 tNET FF 1 spiflash_inst/u_spi_ctrl/n244_s20/I1
9.485 0.814 tINS FF 5 spiflash_inst/u_spi_ctrl/n244_s20/F
9.841 0.356 tNET FF 1 spiflash_inst/u_spi_ctrl/n244_s18/I1
10.655 0.814 tINS FF 35 spiflash_inst/u_spi_ctrl/n244_s18/F
11.011 0.356 tNET FF 1 spiflash_inst/u_spi_ctrl/txf_rd_Z_s/I0
11.775 0.765 tINS FF 29 spiflash_inst/u_spi_ctrl/txf_rd_Z_s/F
12.131 0.356 tNET FF 1 spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_0_s0/I1
12.945 0.814 tINS FF 2 spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_0_s0/F
13.301 0.356 tNET FF 2 spiflash_inst/u_spi_fifo/u_spi_txfifo/n163_s0/I0
14.011 0.710 tINS FF 1 spiflash_inst/u_spi_fifo/u_spi_txfifo/n163_s0/COUT
14.011 0.000 tNET FF 2 spiflash_inst/u_spi_fifo/u_spi_txfifo/n164_s0/CIN
14.053 0.042 tINS FF 1 spiflash_inst/u_spi_fifo/u_spi_txfifo/n164_s0/COUT
14.409 0.356 tNET FF 1 spiflash_inst/u_spi_fifo/u_spi_txfifo/rempty_val_s1/I2
15.018 0.609 tINS FF 1 spiflash_inst/u_spi_fifo/u_spi_txfifo/rempty_val_s1/F
15.374 0.356 tNET FF 1 spiflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_spi_clock
20.000 0.000 tCL RR 1 I_spi_clock_ibuf/I
20.728 0.728 tINS RR 160 I_spi_clock_ibuf/O
20.997 0.269 tNET RR 1 spiflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0/CLK
20.967 -0.030 tUnc spiflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0
20.670 -0.296 tSu 1 spiflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 9.414, 65.477%; route: 4.624, 32.161%; tC2Q: 0.340, 2.362%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 3

Path Summary:
Slack 5.344
Data Arrival Time 15.356
Data Required Time 20.700
From spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1
To spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1
Launch Clk I_spi_clock[R]
Latch Clk I_spi_clock[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_spi_clock
10.000 0.000 tCL FF 1 I_spi_clock_ibuf/I
10.729 0.729 tINS FF 160 I_spi_clock_ibuf/O
11.085 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/CLK
11.425 0.340 tC2Q FF 1 spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/Q
11.780 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/I1
12.595 0.814 tINS FF 1 spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/F
12.950 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/I1
13.061 0.110 tINS FF 4 spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/O
13.417 0.356 tNET FF 1 spiflash_inst/u_spi_ctrl/n1079_s2/I0
14.181 0.765 tINS FF 8 spiflash_inst/u_spi_ctrl/n1079_s2/F
14.537 0.356 tNET FF 1 spiflash_inst/u_spi_ctrl/n1079_s5/I3
15.001 0.464 tINS FF 1 spiflash_inst/u_spi_ctrl/n1079_s5/F
15.356 0.356 tNET FF 1 spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_spi_clock
20.000 0.000 tCL RR 1 I_spi_clock_ibuf/I
20.728 0.728 tINS RR 160 I_spi_clock_ibuf/O
20.997 0.269 tNET RR 1 spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1/CLK
20.700 -0.296 tSu 1 spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1
Path Statistics:
Clock Skew: -0.089
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.729, 67.222%; route: 0.356, 32.778%
Arrival Data Path Delay: cell: 2.153, 50.414%; route: 1.778, 41.635%; tC2Q: 0.340, 7.951%
Required Clock Path Delay: cell: 0.729, 67.222%; route: 0.356, 32.778%

Path 4

Path Summary:
Slack 5.344
Data Arrival Time 15.356
Data Required Time 20.700
From spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1
To spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1
Launch Clk I_spi_clock[R]
Latch Clk I_spi_clock[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_spi_clock
10.000 0.000 tCL FF 1 I_spi_clock_ibuf/I
10.729 0.729 tINS FF 160 I_spi_clock_ibuf/O
11.085 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/CLK
11.425 0.340 tC2Q FF 1 spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/Q
11.780 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/I1
12.595 0.814 tINS FF 1 spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/F
12.950 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/I1
13.061 0.110 tINS FF 4 spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/O
13.417 0.356 tNET FF 1 spiflash_inst/u_spi_ctrl/n1078_s2/I0
14.181 0.765 tINS FF 8 spiflash_inst/u_spi_ctrl/n1078_s2/F
14.537 0.356 tNET FF 1 spiflash_inst/u_spi_ctrl/n1078_s3/I3
15.001 0.464 tINS FF 1 spiflash_inst/u_spi_ctrl/n1078_s3/F
15.356 0.356 tNET FF 1 spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_spi_clock
20.000 0.000 tCL RR 1 I_spi_clock_ibuf/I
20.728 0.728 tINS RR 160 I_spi_clock_ibuf/O
20.997 0.269 tNET RR 1 spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1/CLK
20.700 -0.296 tSu 1 spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1
Path Statistics:
Clock Skew: -0.089
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.729, 67.222%; route: 0.356, 32.778%
Arrival Data Path Delay: cell: 2.153, 50.414%; route: 1.778, 41.635%; tC2Q: 0.340, 7.951%
Required Clock Path Delay: cell: 0.729, 67.222%; route: 0.356, 32.778%

Path 5

Path Summary:
Slack 5.344
Data Arrival Time 15.356
Data Required Time 20.700
From spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1
To spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1
Launch Clk I_spi_clock[R]
Latch Clk I_spi_clock[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_spi_clock
10.000 0.000 tCL FF 1 I_spi_clock_ibuf/I
10.729 0.729 tINS FF 160 I_spi_clock_ibuf/O
11.085 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/CLK
11.425 0.340 tC2Q FF 1 spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/Q
11.780 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/I1
12.595 0.814 tINS FF 1 spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/F
12.950 0.356 tNET FF 1 spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/I1
13.061 0.110 tINS FF 4 spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/O
13.417 0.356 tNET FF 1 spiflash_inst/u_spi_ctrl/n1077_s2/I0
14.181 0.765 tINS FF 8 spiflash_inst/u_spi_ctrl/n1077_s2/F
14.537 0.356 tNET FF 1 spiflash_inst/u_spi_ctrl/n1077_s3/I3
15.001 0.464 tINS FF 1 spiflash_inst/u_spi_ctrl/n1077_s3/F
15.356 0.356 tNET FF 1 spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_spi_clock
20.000 0.000 tCL RR 1 I_spi_clock_ibuf/I
20.728 0.728 tINS RR 160 I_spi_clock_ibuf/O
20.997 0.269 tNET RR 1 spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1/CLK
20.700 -0.296 tSu 1 spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1
Path Statistics:
Clock Skew: -0.089
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.729, 67.222%; route: 0.356, 32.778%
Arrival Data Path Delay: cell: 2.153, 50.414%; route: 1.778, 41.635%; tC2Q: 0.340, 7.951%
Required Clock Path Delay: cell: 0.729, 67.222%; route: 0.356, 32.778%