Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\SPIFlashInterface\data\spi_flash_interface_top.v D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\SPIFlashInterface\data\spiflash.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.10 |
| Part Number | GW1NSR-LV4CQN48PC7/I6 |
| Device | GW1NSR-4 |
| Device Version | C |
| Created Time | Tue Dec 13 09:46:58 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | SPI_Flash_Interface_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.404s, Peak memory usage = 44.375MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 44.375MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 44.375MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 44.375MB Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 44.375MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 44.375MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 44.375MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 44.375MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 44.375MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 44.375MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 44.375MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 44.375MB Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 6s, Peak memory usage = 57.941MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.183s, Peak memory usage = 57.941MB Generate output files: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.15s, Peak memory usage = 57.941MB |
| Total Time and Memory Usage | CPU time = 0h 0m 6s, Elapsed time = 0h 0m 7s, Peak memory usage = 57.941MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 114 |
| I/O Buf | 86 |
| IBUF | 45 |
| OBUF | 37 |
| IOBUF | 4 |
| Register | 385 |
| DFF | 4 |
| DFFP | 8 |
| DFFPE | 21 |
| DFFC | 96 |
| DFFCE | 249 |
| DFFNC | 1 |
| DFFNCE | 4 |
| DL | 1 |
| DLN | 1 |
| LUT | 802 |
| LUT2 | 83 |
| LUT3 | 226 |
| LUT4 | 493 |
| ALU | 79 |
| ALU | 79 |
| INV | 8 |
| INV | 8 |
| BSRAM | 2 |
| SDPB | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 889(810 LUTs, 79 ALUs) / 4608 | 20% |
| Register | 385 / 3570 | 11% |
| --Register as Latch | 2 / 3570 | <1% |
| --Register as FF | 383 / 3570 | 11% |
| BSRAM | 2 / 10 | 20% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_hclk | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_hclk_ibuf/I | ||
| I_spi_clock | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_spi_clock_ibuf/I | ||
| O_flash_ck_d | Base | 20.000 | 50.0 | 0.000 | 10.000 | spiflash_inst/u_spi_spiif/O_flash_ck_d_s/F |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_hclk | 50.0(MHz) | 102.7(MHz) | 9 | TOP |
| 2 | I_spi_clock | 50.0(MHz) | 57.8(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.219 |
| Data Arrival Time | 9.540 |
| Data Required Time | 10.759 |
| From | spiflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0 |
| To | spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1 |
| Launch Clk | I_hclk[F] |
| Latch Clk | I_spi_clock[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_hclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_hclk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 220 | I_hclk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | spiflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/CLK |
| 1.336 | 0.340 | tC2Q | RF | 3 | spiflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/Q |
| 1.692 | 0.356 | tNET | FF | 2 | spiflash_inst/u_spi_spiif/n150_s16/I1 |
| 2.466 | 0.774 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/n150_s16/COUT |
| 2.466 | 0.000 | tNET | FF | 2 | spiflash_inst/u_spi_spiif/n150_s17/CIN |
| 2.508 | 0.042 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/n150_s17/COUT |
| 2.508 | 0.000 | tNET | FF | 2 | spiflash_inst/u_spi_spiif/n150_s18/CIN |
| 2.551 | 0.042 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/n150_s18/COUT |
| 2.551 | 0.000 | tNET | FF | 2 | spiflash_inst/u_spi_spiif/n150_s19/CIN |
| 2.593 | 0.042 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/n150_s19/COUT |
| 2.593 | 0.000 | tNET | FF | 2 | spiflash_inst/u_spi_spiif/n150_s20/CIN |
| 2.635 | 0.042 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/n150_s20/COUT |
| 2.635 | 0.000 | tNET | FF | 2 | spiflash_inst/u_spi_spiif/n150_s21/CIN |
| 2.677 | 0.042 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/n150_s21/COUT |
| 2.677 | 0.000 | tNET | FF | 2 | spiflash_inst/u_spi_spiif/n150_s22/CIN |
| 2.720 | 0.042 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/n150_s22/COUT |
| 3.075 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/period_cnt_r_7_s5/I1 |
| 3.890 | 0.814 | tINS | FF | 5 | spiflash_inst/u_spi_spiif/period_cnt_r_7_s5/F |
| 4.245 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_ns_2_s13/I2 |
| 4.854 | 0.609 | tINS | FF | 3 | spiflash_inst/u_spi_spiif/spi_ns_2_s13/F |
| 5.210 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_ns_0_s10/I1 |
| 6.024 | 0.814 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/spi_ns_0_s10/F |
| 6.380 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_ns_0_s9/I1 |
| 7.195 | 0.814 | tINS | FF | 7 | spiflash_inst/u_spi_spiif/spi_ns_0_s9/F |
| 7.550 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/master_clk_en_s2/I1 |
| 8.365 | 0.814 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/master_clk_en_s2/F |
| 8.720 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/master_clk_en_s0/I3 |
| 9.184 | 0.464 | tINS | FF | 2 | spiflash_inst/u_spi_spiif/master_clk_en_s0/F |
| 9.540 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_spi_clock | |||
| 10.000 | 0.000 | tCL | FF | 1 | I_spi_clock_ibuf/I |
| 10.729 | 0.729 | tINS | FF | 166 | I_spi_clock_ibuf/O |
| 11.085 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1/CLK |
| 11.055 | -0.030 | tUnc | spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1 | ||
| 10.759 | -0.296 | tSu | 1 | spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1 |
| Clock Skew: | 0.089 |
| Setup Relationship: | 10.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 5.358, 62.719%; route: 2.845, 33.306%; tC2Q: 0.340, 3.975% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 2
Path Summary:| Slack | 3.823 |
| Data Arrival Time | 16.877 |
| Data Required Time | 20.700 |
| From | spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1 |
| To | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1 |
| Launch Clk | I_spi_clock[R] |
| Latch Clk | I_spi_clock[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_spi_clock | |||
| 10.000 | 0.000 | tCL | FF | 1 | I_spi_clock_ibuf/I |
| 10.729 | 0.729 | tINS | FF | 166 | I_spi_clock_ibuf/O |
| 11.085 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/CLK |
| 11.425 | 0.340 | tC2Q | FF | 1 | spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/Q |
| 11.780 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/I1 |
| 12.595 | 0.814 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/F |
| 12.950 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/I1 |
| 13.061 | 0.110 | tINS | FF | 4 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/O |
| 13.417 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n1129_s5/I1 |
| 14.231 | 0.814 | tINS | FF | 2 | spiflash_inst/u_spi_ctrl/n1129_s5/F |
| 14.587 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n1129_s3/I0 |
| 15.351 | 0.765 | tINS | FF | 8 | spiflash_inst/u_spi_ctrl/n1129_s3/F |
| 15.707 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n1129_s11/I1 |
| 16.521 | 0.814 | tINS | FF | 1 | spiflash_inst/u_spi_ctrl/n1129_s11/F |
| 16.877 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_spi_clock | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_spi_clock_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 166 | I_spi_clock_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1/CLK |
| 20.700 | -0.296 | tSu | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1 |
| Clock Skew: | -0.089 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
| Arrival Data Path Delay: | cell: 3.318, 57.290%; route: 2.134, 36.846%; tC2Q: 0.340, 5.864% |
| Required Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
Path 3
Path Summary:| Slack | 3.823 |
| Data Arrival Time | 16.877 |
| Data Required Time | 20.700 |
| From | spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1 |
| To | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1 |
| Launch Clk | I_spi_clock[R] |
| Latch Clk | I_spi_clock[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_spi_clock | |||
| 10.000 | 0.000 | tCL | FF | 1 | I_spi_clock_ibuf/I |
| 10.729 | 0.729 | tINS | FF | 166 | I_spi_clock_ibuf/O |
| 11.085 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/CLK |
| 11.425 | 0.340 | tC2Q | FF | 1 | spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/Q |
| 11.780 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/I1 |
| 12.595 | 0.814 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/F |
| 12.950 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/I1 |
| 13.061 | 0.110 | tINS | FF | 4 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/O |
| 13.417 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n1128_s5/I1 |
| 14.231 | 0.814 | tINS | FF | 2 | spiflash_inst/u_spi_ctrl/n1128_s5/F |
| 14.587 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n1128_s3/I0 |
| 15.351 | 0.765 | tINS | FF | 8 | spiflash_inst/u_spi_ctrl/n1128_s3/F |
| 15.707 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n1128_s10/I1 |
| 16.521 | 0.814 | tINS | FF | 1 | spiflash_inst/u_spi_ctrl/n1128_s10/F |
| 16.877 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_spi_clock | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_spi_clock_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 166 | I_spi_clock_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1/CLK |
| 20.700 | -0.296 | tSu | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1 |
| Clock Skew: | -0.089 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
| Arrival Data Path Delay: | cell: 3.318, 57.290%; route: 2.134, 36.846%; tC2Q: 0.340, 5.864% |
| Required Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
Path 4
Path Summary:| Slack | 3.823 |
| Data Arrival Time | 16.877 |
| Data Required Time | 20.700 |
| From | spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1 |
| To | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1 |
| Launch Clk | I_spi_clock[R] |
| Latch Clk | I_spi_clock[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_spi_clock | |||
| 10.000 | 0.000 | tCL | FF | 1 | I_spi_clock_ibuf/I |
| 10.729 | 0.729 | tINS | FF | 166 | I_spi_clock_ibuf/O |
| 11.085 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/CLK |
| 11.425 | 0.340 | tC2Q | FF | 1 | spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/Q |
| 11.780 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/I1 |
| 12.595 | 0.814 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/F |
| 12.950 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/I1 |
| 13.061 | 0.110 | tINS | FF | 4 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/O |
| 13.417 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n1129_s5/I1 |
| 14.231 | 0.814 | tINS | FF | 2 | spiflash_inst/u_spi_ctrl/n1129_s5/F |
| 14.587 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n1127_s3/I0 |
| 15.351 | 0.765 | tINS | FF | 8 | spiflash_inst/u_spi_ctrl/n1127_s3/F |
| 15.707 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n1127_s5/I1 |
| 16.521 | 0.814 | tINS | FF | 1 | spiflash_inst/u_spi_ctrl/n1127_s5/F |
| 16.877 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_spi_clock | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_spi_clock_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 166 | I_spi_clock_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1/CLK |
| 20.700 | -0.296 | tSu | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1 |
| Clock Skew: | -0.089 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
| Arrival Data Path Delay: | cell: 3.318, 57.290%; route: 2.134, 36.846%; tC2Q: 0.340, 5.864% |
| Required Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
Path 5
Path Summary:| Slack | 3.823 |
| Data Arrival Time | 16.877 |
| Data Required Time | 20.700 |
| From | spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1 |
| To | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_s1 |
| Launch Clk | I_spi_clock[R] |
| Latch Clk | I_spi_clock[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_spi_clock | |||
| 10.000 | 0.000 | tCL | FF | 1 | I_spi_clock_ibuf/I |
| 10.729 | 0.729 | tINS | FF | 166 | I_spi_clock_ibuf/O |
| 11.085 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/CLK |
| 11.425 | 0.340 | tC2Q | FF | 1 | spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s1/Q |
| 11.780 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/I1 |
| 12.595 | 0.814 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1/F |
| 12.950 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/I1 |
| 13.061 | 0.110 | tINS | FF | 4 | spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s/O |
| 13.417 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n1128_s5/I1 |
| 14.231 | 0.814 | tINS | FF | 2 | spiflash_inst/u_spi_ctrl/n1128_s5/F |
| 14.587 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n1126_s3/I0 |
| 15.351 | 0.765 | tINS | FF | 8 | spiflash_inst/u_spi_ctrl/n1126_s3/F |
| 15.707 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n1126_s5/I1 |
| 16.521 | 0.814 | tINS | FF | 1 | spiflash_inst/u_spi_ctrl/n1126_s5/F |
| 16.877 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_spi_clock | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_spi_clock_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 166 | I_spi_clock_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_s1/CLK |
| 20.700 | -0.296 | tSu | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_s1 |
| Clock Skew: | -0.089 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
| Arrival Data Path Delay: | cell: 3.318, 57.290%; route: 2.134, 36.846%; tC2Q: 0.340, 5.864% |
| Required Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |