Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\PID_Controller_3p3z\PID_controller_3p3z_RefDesign\project\src\input_gen.v E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\PID_Controller_3p3z\PID_controller_3p3z_RefDesign\project\src\pid_controller_3p3z\pid_controller_3p3z.v E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\PID_Controller_3p3z\PID_controller_3p3z_RefDesign\project\src\top.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\PID_Controller_3p3z\PID_controller_3p3z_RefDesign\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.07 |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Wed Jul 06 11:00:56 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.906s, Elapsed time = 0h 0m 1s, Peak memory usage = 391.172MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.151s, Peak memory usage = 391.172MB Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.09s, Peak memory usage = 391.172MB Optimizing Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 391.172MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 391.172MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 391.172MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 391.172MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 391.172MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 391.172MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 391.172MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 391.172MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 391.172MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.134s, Peak memory usage = 391.172MB Generate output files: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.161s, Peak memory usage = 391.172MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 4s, Peak memory usage = 391.172MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 25 |
| I/O Buf | 25 |
| IBUF | 5 |
| OBUF | 20 |
| Register | 2287 |
| DFF | 405 |
| DFFS | 17 |
| DFFR | 15 |
| DFFP | 4 |
| DFFPE | 39 |
| DFFC | 246 |
| DFFCE | 1555 |
| DFFNP | 2 |
| DFFNC | 4 |
| LUT | 1325 |
| LUT2 | 71 |
| LUT3 | 526 |
| LUT4 | 728 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 80 |
| ALU | 80 |
| SSRAM | 4 |
| RAM16S4 | 4 |
| INV | 7 |
| INV | 7 |
| DSP | 1 |
| MULTADDALU18X18 | 1 |
| BSRAM | 10 |
| SDPX9B | 10 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1444(1340 LUTs, 80 ALUs, 4 SSRAMs) / 20736 | 7% |
| Register | 2287 / 16173 | 14% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 2287 / 16173 | 14% |
| BSRAM | 10 / 46 | 22% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 100.0(MHz) | 272.2(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 6.326 |
| Data Arrival Time | 4.501 |
| Data Required Time | 10.828 |
| From | input_gen_inst/u_data_ch0_0_s0 |
| To | controller_3p3z_inst/controller_3p3z_inst/ram_en0_din_15_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1753 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | input_gen_inst/u_data_ch0_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | input_gen_inst/u_data_ch0_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | input_gen_inst/data_fdb_i_Z_0_s0/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | input_gen_inst/data_fdb_i_Z_0_s0/F |
| 2.124 | 0.237 | tNET | FF | 1 | input_gen_inst/data_fdb_i_Z_0_s/I3 |
| 2.495 | 0.371 | tINS | FF | 2 | input_gen_inst/data_fdb_i_Z_0_s/F |
| 2.732 | 0.237 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n409_s/I1 |
| 3.302 | 0.570 | tINS | FR | 1 | controller_3p3z_inst/controller_3p3z_inst/n409_s/COUT |
| 3.302 | 0.000 | tNET | RR | 2 | controller_3p3z_inst/controller_3p3z_inst/n408_s/CIN |
| 3.337 | 0.035 | tINS | RF | 1 | controller_3p3z_inst/controller_3p3z_inst/n408_s/COUT |
| 3.337 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n407_s/CIN |
| 3.372 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n407_s/COUT |
| 3.372 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n406_s/CIN |
| 3.407 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n406_s/COUT |
| 3.407 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n405_s/CIN |
| 3.442 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n405_s/COUT |
| 3.442 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n404_s/CIN |
| 3.478 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n404_s/COUT |
| 3.478 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n403_s/CIN |
| 3.513 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n403_s/COUT |
| 3.513 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n402_s/CIN |
| 3.548 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n402_s/COUT |
| 3.548 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n401_s/CIN |
| 3.583 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n401_s/COUT |
| 3.583 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n400_s/CIN |
| 3.618 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n400_s/COUT |
| 3.618 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n399_s/CIN |
| 3.654 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n399_s/COUT |
| 3.654 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n398_s/CIN |
| 3.689 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n398_s/COUT |
| 3.689 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n397_s/CIN |
| 3.724 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n397_s/COUT |
| 3.724 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n396_s/CIN |
| 3.759 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n396_s/COUT |
| 3.759 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n395_s/CIN |
| 3.794 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n395_s/COUT |
| 3.794 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n394_s/CIN |
| 4.264 | 0.470 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n394_s/SUM |
| 4.501 | 0.237 | tNET | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/ram_en0_din_15_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1753 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | controller_3p3z_inst/controller_3p3z_inst/ram_en0_din_15_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | controller_3p3z_inst/controller_3p3z_inst/ram_en0_din_15_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.459, 67.571%; route: 0.948, 26.053%; tC2Q: 0.232, 6.376% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 6.328 |
| Data Arrival Time | 4.500 |
| Data Required Time | 10.828 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1753 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 13 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1079_s3/I1 |
| 1.887 | 0.555 | tINS | FF | 4 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1079_s3/F |
| 2.124 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1076_s4/I1 |
| 2.679 | 0.555 | tINS | FF | 3 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1076_s4/F |
| 2.916 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1075_s3/I1 |
| 3.471 | 0.555 | tINS | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1075_s3/F |
| 3.708 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1075_s1/I1 |
| 4.263 | 0.555 | tINS | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1075_s1/F |
| 4.500 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1753 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.220, 61.039%; route: 1.185, 32.582%; tC2Q: 0.232, 6.379% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 6.361 |
| Data Arrival Time | 4.466 |
| Data Required Time | 10.828 |
| From | input_gen_inst/u_data_ch0_0_s0 |
| To | controller_3p3z_inst/controller_3p3z_inst/ram_en0_din_14_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1753 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | input_gen_inst/u_data_ch0_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | input_gen_inst/u_data_ch0_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | input_gen_inst/data_fdb_i_Z_0_s0/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | input_gen_inst/data_fdb_i_Z_0_s0/F |
| 2.124 | 0.237 | tNET | FF | 1 | input_gen_inst/data_fdb_i_Z_0_s/I3 |
| 2.495 | 0.371 | tINS | FF | 2 | input_gen_inst/data_fdb_i_Z_0_s/F |
| 2.732 | 0.237 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n409_s/I1 |
| 3.302 | 0.570 | tINS | FR | 1 | controller_3p3z_inst/controller_3p3z_inst/n409_s/COUT |
| 3.302 | 0.000 | tNET | RR | 2 | controller_3p3z_inst/controller_3p3z_inst/n408_s/CIN |
| 3.337 | 0.035 | tINS | RF | 1 | controller_3p3z_inst/controller_3p3z_inst/n408_s/COUT |
| 3.337 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n407_s/CIN |
| 3.372 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n407_s/COUT |
| 3.372 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n406_s/CIN |
| 3.407 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n406_s/COUT |
| 3.407 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n405_s/CIN |
| 3.442 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n405_s/COUT |
| 3.442 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n404_s/CIN |
| 3.478 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n404_s/COUT |
| 3.478 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n403_s/CIN |
| 3.513 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n403_s/COUT |
| 3.513 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n402_s/CIN |
| 3.548 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n402_s/COUT |
| 3.548 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n401_s/CIN |
| 3.583 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n401_s/COUT |
| 3.583 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n400_s/CIN |
| 3.618 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n400_s/COUT |
| 3.618 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n399_s/CIN |
| 3.654 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n399_s/COUT |
| 3.654 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n398_s/CIN |
| 3.689 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n398_s/COUT |
| 3.689 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n397_s/CIN |
| 3.724 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n397_s/COUT |
| 3.724 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n396_s/CIN |
| 3.759 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n396_s/COUT |
| 3.759 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n395_s/CIN |
| 4.229 | 0.470 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n395_s/SUM |
| 4.466 | 0.237 | tNET | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/ram_en0_din_14_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1753 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | controller_3p3z_inst/controller_3p3z_inst/ram_en0_din_14_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | controller_3p3z_inst/controller_3p3z_inst/ram_en0_din_14_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.424, 67.255%; route: 0.948, 26.307%; tC2Q: 0.232, 6.438% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 6.397 |
| Data Arrival Time | 4.431 |
| Data Required Time | 10.828 |
| From | input_gen_inst/u_data_ch0_0_s0 |
| To | controller_3p3z_inst/controller_3p3z_inst/ram_en0_din_13_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1753 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | input_gen_inst/u_data_ch0_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | input_gen_inst/u_data_ch0_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | input_gen_inst/data_fdb_i_Z_0_s0/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | input_gen_inst/data_fdb_i_Z_0_s0/F |
| 2.124 | 0.237 | tNET | FF | 1 | input_gen_inst/data_fdb_i_Z_0_s/I3 |
| 2.495 | 0.371 | tINS | FF | 2 | input_gen_inst/data_fdb_i_Z_0_s/F |
| 2.732 | 0.237 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n409_s/I1 |
| 3.302 | 0.570 | tINS | FR | 1 | controller_3p3z_inst/controller_3p3z_inst/n409_s/COUT |
| 3.302 | 0.000 | tNET | RR | 2 | controller_3p3z_inst/controller_3p3z_inst/n408_s/CIN |
| 3.337 | 0.035 | tINS | RF | 1 | controller_3p3z_inst/controller_3p3z_inst/n408_s/COUT |
| 3.337 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n407_s/CIN |
| 3.372 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n407_s/COUT |
| 3.372 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n406_s/CIN |
| 3.407 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n406_s/COUT |
| 3.407 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n405_s/CIN |
| 3.442 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n405_s/COUT |
| 3.442 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n404_s/CIN |
| 3.478 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n404_s/COUT |
| 3.478 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n403_s/CIN |
| 3.513 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n403_s/COUT |
| 3.513 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n402_s/CIN |
| 3.548 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n402_s/COUT |
| 3.548 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n401_s/CIN |
| 3.583 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n401_s/COUT |
| 3.583 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n400_s/CIN |
| 3.618 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n400_s/COUT |
| 3.618 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n399_s/CIN |
| 3.654 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n399_s/COUT |
| 3.654 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n398_s/CIN |
| 3.689 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n398_s/COUT |
| 3.689 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n397_s/CIN |
| 3.724 | 0.035 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n397_s/COUT |
| 3.724 | 0.000 | tNET | FF | 2 | controller_3p3z_inst/controller_3p3z_inst/n396_s/CIN |
| 4.194 | 0.470 | tINS | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/n396_s/SUM |
| 4.431 | 0.237 | tNET | FF | 1 | controller_3p3z_inst/controller_3p3z_inst/ram_en0_din_13_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1753 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | controller_3p3z_inst/controller_3p3z_inst/ram_en0_din_13_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | controller_3p3z_inst/controller_3p3z_inst/ram_en0_din_13_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.388, 66.931%; route: 0.948, 26.567%; tC2Q: 0.232, 6.502% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 6.429 |
| Data Arrival Time | 4.398 |
| Data Required Time | 10.828 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1753 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 12 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s11/I0 |
| 1.849 | 0.517 | tINS | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s11/F |
| 2.086 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s7/I1 |
| 2.641 | 0.555 | tINS | FF | 2 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s7/F |
| 2.878 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s4/I1 |
| 3.433 | 0.555 | tINS | FF | 10 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n1074_s4/F |
| 3.670 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0 |
| 4.219 | 0.549 | tINS | FR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F |
| 4.398 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1753 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.176, 61.539%; route: 1.128, 31.900%; tC2Q: 0.232, 6.561% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |