Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\LPC_PERIPHERAL\data\lpc_peripheral.v
D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\LPC_PERIPHERAL\data\lpc_peripheral_wrap.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.07
Part Number GW1N-LV9LQ144C6/I5
Device GW1N-9C
Created Time Mon Jul 04 16:05:29 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module LPC_Peripheral_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.197s, Peak memory usage = 43.875MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 43.875MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 43.875MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 43.875MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 43.875MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 43.875MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 43.875MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 43.875MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 43.875MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 43.875MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 43.875MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 43.875MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.746s, Peak memory usage = 53.816MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 53.816MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 53.816MB
Total Time and Memory Usage CPU time = 0h 0m 0.919s, Elapsed time = 0h 0m 0.983s, Peak memory usage = 53.816MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 46
I/O Buf 46
    IBUF 14
    OBUF 28
    IOBUF 4
Register 31
    DFFE 24
    DFFS 2
    DFFC 5
LUT 76
    LUT2 13
    LUT3 12
    LUT4 51
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 77(77 LUTs, 0 ALUs) / 8640 1%
Register 31 / 6843 1%
  --Register as Latch 0 / 6843 0%
  --Register as FF 31 / 6843 1%
BSRAM 0 / 26 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
lclk Base 20.000 50.0 0.000 10.000 lclk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 lclk 50.0(MHz) 104.7(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 10.449
Data Arrival Time 10.852
Data Required Time 21.302
From u_lpc_peri/current_state_2_s0
To u_lpc_peri/lpc_addr_0_s0
Launch Clk lclk[R]
Latch Clk lclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 lclk
0.000 0.000 tCL RR 1 lclk_ibuf/I
0.982 0.982 tINS RR 31 lclk_ibuf/O
1.345 0.363 tNET RR 1 u_lpc_peri/current_state_2_s0/CLK
1.803 0.458 tC2Q RF 18 u_lpc_peri/current_state_2_s0/Q
2.283 0.480 tNET FF 1 u_lpc_peri/n423_s8/I1
3.382 1.099 tINS FF 4 u_lpc_peri/n423_s8/F
3.862 0.480 tNET FF 1 u_lpc_peri/n423_s6/I1
4.961 1.099 tINS FF 2 u_lpc_peri/n423_s6/F
5.441 0.480 tNET FF 1 u_lpc_peri/n423_s2/I1
6.540 1.099 tINS FF 2 u_lpc_peri/n423_s2/F
7.020 0.480 tNET FF 1 u_lpc_peri/n420_s1/I2
7.842 0.822 tINS FF 2 u_lpc_peri/n420_s1/F
8.322 0.480 tNET FF 1 u_lpc_peri/next_state_3_s2/I3
8.948 0.626 tINS FF 5 u_lpc_peri/next_state_3_s2/F
9.428 0.480 tNET FF 1 u_lpc_peri/rd_addr_en_0_s1/I1
10.489 1.061 tINS FR 4 u_lpc_peri/rd_addr_en_0_s1/F
10.852 0.363 tNET RR 1 u_lpc_peri/lpc_addr_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 lclk
20.000 0.000 tCL RR 1 lclk_ibuf/I
20.982 0.982 tINS RR 31 lclk_ibuf/O
21.345 0.363 tNET RR 1 u_lpc_peri/lpc_addr_0_s0/CLK
21.302 -0.043 tSu 1 u_lpc_peri/lpc_addr_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 5.806, 61.068%; route: 3.243, 34.111%; tC2Q: 0.458, 4.821%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 10.449
Data Arrival Time 10.852
Data Required Time 21.302
From u_lpc_peri/current_state_2_s0
To u_lpc_peri/lpc_addr_1_s0
Launch Clk lclk[R]
Latch Clk lclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 lclk
0.000 0.000 tCL RR 1 lclk_ibuf/I
0.982 0.982 tINS RR 31 lclk_ibuf/O
1.345 0.363 tNET RR 1 u_lpc_peri/current_state_2_s0/CLK
1.803 0.458 tC2Q RF 18 u_lpc_peri/current_state_2_s0/Q
2.283 0.480 tNET FF 1 u_lpc_peri/n423_s8/I1
3.382 1.099 tINS FF 4 u_lpc_peri/n423_s8/F
3.862 0.480 tNET FF 1 u_lpc_peri/n423_s6/I1
4.961 1.099 tINS FF 2 u_lpc_peri/n423_s6/F
5.441 0.480 tNET FF 1 u_lpc_peri/n423_s2/I1
6.540 1.099 tINS FF 2 u_lpc_peri/n423_s2/F
7.020 0.480 tNET FF 1 u_lpc_peri/n420_s1/I2
7.842 0.822 tINS FF 2 u_lpc_peri/n420_s1/F
8.322 0.480 tNET FF 1 u_lpc_peri/next_state_3_s2/I3
8.948 0.626 tINS FF 5 u_lpc_peri/next_state_3_s2/F
9.428 0.480 tNET FF 1 u_lpc_peri/rd_addr_en_0_s1/I1
10.489 1.061 tINS FR 4 u_lpc_peri/rd_addr_en_0_s1/F
10.852 0.363 tNET RR 1 u_lpc_peri/lpc_addr_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 lclk
20.000 0.000 tCL RR 1 lclk_ibuf/I
20.982 0.982 tINS RR 31 lclk_ibuf/O
21.345 0.363 tNET RR 1 u_lpc_peri/lpc_addr_1_s0/CLK
21.302 -0.043 tSu 1 u_lpc_peri/lpc_addr_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 5.806, 61.068%; route: 3.243, 34.111%; tC2Q: 0.458, 4.821%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 10.449
Data Arrival Time 10.852
Data Required Time 21.302
From u_lpc_peri/current_state_2_s0
To u_lpc_peri/lpc_addr_2_s0
Launch Clk lclk[R]
Latch Clk lclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 lclk
0.000 0.000 tCL RR 1 lclk_ibuf/I
0.982 0.982 tINS RR 31 lclk_ibuf/O
1.345 0.363 tNET RR 1 u_lpc_peri/current_state_2_s0/CLK
1.803 0.458 tC2Q RF 18 u_lpc_peri/current_state_2_s0/Q
2.283 0.480 tNET FF 1 u_lpc_peri/n423_s8/I1
3.382 1.099 tINS FF 4 u_lpc_peri/n423_s8/F
3.862 0.480 tNET FF 1 u_lpc_peri/n423_s6/I1
4.961 1.099 tINS FF 2 u_lpc_peri/n423_s6/F
5.441 0.480 tNET FF 1 u_lpc_peri/n423_s2/I1
6.540 1.099 tINS FF 2 u_lpc_peri/n423_s2/F
7.020 0.480 tNET FF 1 u_lpc_peri/n420_s1/I2
7.842 0.822 tINS FF 2 u_lpc_peri/n420_s1/F
8.322 0.480 tNET FF 1 u_lpc_peri/next_state_3_s2/I3
8.948 0.626 tINS FF 5 u_lpc_peri/next_state_3_s2/F
9.428 0.480 tNET FF 1 u_lpc_peri/rd_addr_en_0_s1/I1
10.489 1.061 tINS FR 4 u_lpc_peri/rd_addr_en_0_s1/F
10.852 0.363 tNET RR 1 u_lpc_peri/lpc_addr_2_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 lclk
20.000 0.000 tCL RR 1 lclk_ibuf/I
20.982 0.982 tINS RR 31 lclk_ibuf/O
21.345 0.363 tNET RR 1 u_lpc_peri/lpc_addr_2_s0/CLK
21.302 -0.043 tSu 1 u_lpc_peri/lpc_addr_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 5.806, 61.068%; route: 3.243, 34.111%; tC2Q: 0.458, 4.821%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 10.449
Data Arrival Time 10.852
Data Required Time 21.302
From u_lpc_peri/current_state_2_s0
To u_lpc_peri/lpc_addr_3_s0
Launch Clk lclk[R]
Latch Clk lclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 lclk
0.000 0.000 tCL RR 1 lclk_ibuf/I
0.982 0.982 tINS RR 31 lclk_ibuf/O
1.345 0.363 tNET RR 1 u_lpc_peri/current_state_2_s0/CLK
1.803 0.458 tC2Q RF 18 u_lpc_peri/current_state_2_s0/Q
2.283 0.480 tNET FF 1 u_lpc_peri/n423_s8/I1
3.382 1.099 tINS FF 4 u_lpc_peri/n423_s8/F
3.862 0.480 tNET FF 1 u_lpc_peri/n423_s6/I1
4.961 1.099 tINS FF 2 u_lpc_peri/n423_s6/F
5.441 0.480 tNET FF 1 u_lpc_peri/n423_s2/I1
6.540 1.099 tINS FF 2 u_lpc_peri/n423_s2/F
7.020 0.480 tNET FF 1 u_lpc_peri/n420_s1/I2
7.842 0.822 tINS FF 2 u_lpc_peri/n420_s1/F
8.322 0.480 tNET FF 1 u_lpc_peri/next_state_3_s2/I3
8.948 0.626 tINS FF 5 u_lpc_peri/next_state_3_s2/F
9.428 0.480 tNET FF 1 u_lpc_peri/rd_addr_en_0_s1/I1
10.489 1.061 tINS FR 4 u_lpc_peri/rd_addr_en_0_s1/F
10.852 0.363 tNET RR 1 u_lpc_peri/lpc_addr_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 lclk
20.000 0.000 tCL RR 1 lclk_ibuf/I
20.982 0.982 tINS RR 31 lclk_ibuf/O
21.345 0.363 tNET RR 1 u_lpc_peri/lpc_addr_3_s0/CLK
21.302 -0.043 tSu 1 u_lpc_peri/lpc_addr_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 5.806, 61.068%; route: 3.243, 34.111%; tC2Q: 0.458, 4.821%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 10.449
Data Arrival Time 10.852
Data Required Time 21.302
From u_lpc_peri/current_state_2_s0
To u_lpc_peri/lpc_addr_8_s0
Launch Clk lclk[R]
Latch Clk lclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 lclk
0.000 0.000 tCL RR 1 lclk_ibuf/I
0.982 0.982 tINS RR 31 lclk_ibuf/O
1.345 0.363 tNET RR 1 u_lpc_peri/current_state_2_s0/CLK
1.803 0.458 tC2Q RF 18 u_lpc_peri/current_state_2_s0/Q
2.283 0.480 tNET FF 1 u_lpc_peri/n423_s8/I1
3.382 1.099 tINS FF 4 u_lpc_peri/n423_s8/F
3.862 0.480 tNET FF 1 u_lpc_peri/n423_s6/I1
4.961 1.099 tINS FF 2 u_lpc_peri/n423_s6/F
5.441 0.480 tNET FF 1 u_lpc_peri/n423_s2/I1
6.540 1.099 tINS FF 2 u_lpc_peri/n423_s2/F
7.020 0.480 tNET FF 1 u_lpc_peri/n420_s1/I2
7.842 0.822 tINS FF 2 u_lpc_peri/n420_s1/F
8.322 0.480 tNET FF 1 u_lpc_peri/next_state_3_s2/I3
8.948 0.626 tINS FF 5 u_lpc_peri/next_state_3_s2/F
9.428 0.480 tNET FF 1 u_lpc_peri/rd_addr_en_2_s1/I1
10.489 1.061 tINS FR 4 u_lpc_peri/rd_addr_en_2_s1/F
10.852 0.363 tNET RR 1 u_lpc_peri/lpc_addr_8_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 lclk
20.000 0.000 tCL RR 1 lclk_ibuf/I
20.982 0.982 tINS RR 31 lclk_ibuf/O
21.345 0.363 tNET RR 1 u_lpc_peri/lpc_addr_8_s0/CLK
21.302 -0.043 tSu 1 u_lpc_peri/lpc_addr_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 5.806, 61.068%; route: 3.243, 34.111%; tC2Q: 0.458, 4.821%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%