Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\Interface\LPC_Peripheral\Gowin_LPC_Peripheral_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	---
Timing Constraint File	---
Version	V1.9.8.07
Part Number	GW1N-LV9LQ144C6/I5
Device	GW1N-9C
Created Time	Tue Jul 12 10:18:36 2022
Legal Announcement	Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	281
Numbers of Endpoints Analyzed	71
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
LCLK	Base	20.000	50.000	0.000	10.000			LCLK_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	LCLK	50.000(MHz)	69.452(MHz)	8	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
LCLK	Setup	0.000	0
LCLK	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.601	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q	io_addr_hit_s1/CE	LCLK:[R]	LCLK:[R]	20.000	0.000	14.355
2	6.551	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q	io_addr_hit_s1/D	LCLK:[R]	LCLK:[R]	20.000	0.000	13.049
3	6.972	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q	cnt_RdDelay_0_s0/D	LCLK:[R]	LCLK:[R]	20.000	0.000	12.628
4	7.029	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q	cnt_RdDelay_2_s0/D	LCLK:[R]	LCLK:[R]	20.000	0.000	12.571
5	7.029	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q	cnt_RdDelay_3_s0/D	LCLK:[R]	LCLK:[R]	20.000	0.000	12.571
6	7.389	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q	cnt_RdDelay_1_s0/D	LCLK:[R]	LCLK:[R]	20.000	0.000	12.211
7	7.406	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_4_s0/CE	LCLK:[R]	LCLK:[R]	20.000	0.000	12.550
8	7.406	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_5_s0/CE	LCLK:[R]	LCLK:[R]	20.000	0.000	12.550
9	7.406	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_6_s0/CE	LCLK:[R]	LCLK:[R]	20.000	0.000	12.550
10	7.779	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_7_s0/CE	LCLK:[R]	LCLK:[R]	20.000	0.000	12.178
11	8.040	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_3_s0/CE	LCLK:[R]	LCLK:[R]	20.000	0.000	11.917
12	8.401	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_0_s0/CE	LCLK:[R]	LCLK:[R]	20.000	0.000	11.555
13	8.401	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_2_s0/CE	LCLK:[R]	LCLK:[R]	20.000	0.000	11.555
14	8.488	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_1_s0/CE	LCLK:[R]	LCLK:[R]	20.000	0.000	11.468
15	8.761	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_8_s0/CE	LCLK:[R]	LCLK:[R]	20.000	0.000	11.196
16	8.761	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_11_s0/CE	LCLK:[R]	LCLK:[R]	20.000	0.000	11.196
17	9.008	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q	cnt_WrDelay_2_s0/D	LCLK:[R]	LCLK:[R]	20.000	0.000	10.592
18	9.008	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q	cnt_WrDelay_3_s0/D	LCLK:[R]	LCLK:[R]	20.000	0.000	10.592
19	9.121	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_9_s0/CE	LCLK:[R]	LCLK:[R]	20.000	0.000	10.836
20	9.121	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_10_s0/CE	LCLK:[R]	LCLK:[R]	20.000	0.000	10.836
21	9.531	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q	lpc_peri_inst/u_lpc_peri/current_state_3_s0/D	LCLK:[R]	LCLK:[R]	20.000	0.000	10.069
22	9.701	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q	cnt_WrDelay_1_s0/D	LCLK:[R]	LCLK:[R]	20.000	0.000	9.899
23	9.990	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0/D	LCLK:[R]	LCLK:[R]	20.000	0.000	9.610
24	10.277	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q	cnt_WrDelay_0_s0/D	LCLK:[R]	LCLK:[R]	20.000	0.000	9.323
25	10.999	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0/SET	LCLK:[R]	LCLK:[R]	20.000	0.000	8.957

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.708	cnt_WrDelay_1_s0/Q	cnt_WrDelay_1_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	0.708
2	0.709	io_rd_data_5_s6/Q	io_rd_data_5_s6/D	LCLK:[R]	LCLK:[R]	0.000	0.000	0.709
3	0.709	cnt_RdDelay_1_s0/Q	cnt_RdDelay_1_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	0.709
4	0.709	cnt_WrDelay_2_s0/Q	cnt_WrDelay_2_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	0.709
5	0.709	cnt_WrDelay_3_s0/Q	cnt_WrDelay_3_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	0.709
6	0.710	cnt_RdDelay_0_s0/Q	cnt_RdDelay_0_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	0.710
7	0.943	cnt_WrDelay_3_s0/Q	io_wr_sync_zero_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	0.943
8	0.944	cnt_RdDelay_2_s0/Q	cnt_RdDelay_3_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	0.944
9	0.950	cnt_RdDelay_1_s0/Q	cnt_RdDelay_2_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	0.950
10	0.957	cnt_RdDelay_2_s0/Q	io_rd_sync_zero_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	0.957
11	1.061	cnt_WrDelay_0_s0/Q	cnt_WrDelay_0_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	1.061
12	1.224	lpc_peri_inst/u_lpc_peri/current_state_1_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_9_s0/CE	LCLK:[R]	LCLK:[R]	0.000	0.000	1.239
13	1.224	lpc_peri_inst/u_lpc_peri/current_state_1_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_10_s0/CE	LCLK:[R]	LCLK:[R]	0.000	0.000	1.239
14	1.481	lpc_peri_inst/u_lpc_peri/current_state_1_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_8_s0/CE	LCLK:[R]	LCLK:[R]	0.000	0.000	1.496
15	1.481	lpc_peri_inst/u_lpc_peri/current_state_1_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_11_s0/CE	LCLK:[R]	LCLK:[R]	0.000	0.000	1.496
16	1.788	lpc_peri_inst/u_lpc_peri/lpc_addr_15_s0/Q	io_addr_hit_s1/CE	LCLK:[R]	LCLK:[R]	0.000	0.000	1.803
17	1.874	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	1.874
18	2.305	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q	lpc_peri_inst/u_lpc_peri/io_wren_sm_d1_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	2.305
19	2.318	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0/SET	LCLK:[R]	LCLK:[R]	0.000	0.000	2.333
20	2.569	lpc_peri_inst/u_lpc_peri/current_state_3_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_15_s0/CE	LCLK:[R]	LCLK:[R]	0.000	0.000	2.584
21	2.635	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q	lpc_peri_inst/u_lpc_peri/current_state_4_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	2.635
22	2.643	lpc_peri_inst/u_lpc_peri/current_state_3_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_12_s0/CE	LCLK:[R]	LCLK:[R]	0.000	0.000	2.658
23	2.643	lpc_peri_inst/u_lpc_peri/current_state_3_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_13_s0/CE	LCLK:[R]	LCLK:[R]	0.000	0.000	2.658
24	2.643	lpc_peri_inst/u_lpc_peri/current_state_3_s0/Q	lpc_peri_inst/u_lpc_peri/lpc_addr_14_s0/CE	LCLK:[R]	LCLK:[R]	0.000	0.000	2.658
25	2.648	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q	lpc_peri_inst/u_lpc_peri/current_state_2_s0/D	LCLK:[R]	LCLK:[R]	0.000	0.000	2.648

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	8.532	9.782	1.250	Low Pulse Width	LCLK	io_wr_sync_zero_s0
2	8.532	9.782	1.250	Low Pulse Width	LCLK	cnt_WrDelay_2_s0
3	8.532	9.782	1.250	Low Pulse Width	LCLK	cnt_RdDelay_3_s0
4	8.532	9.782	1.250	Low Pulse Width	LCLK	lpc_peri_inst/u_lpc_peri/current_state_1_s0
5	8.532	9.782	1.250	Low Pulse Width	LCLK	lpc_peri_inst/u_lpc_peri/lpc_addr_3_s0
6	8.532	9.782	1.250	Low Pulse Width	LCLK	lpc_peri_inst/u_lpc_peri/lpc_addr_4_s0
7	8.532	9.782	1.250	Low Pulse Width	LCLK	lpc_peri_inst/u_lpc_peri/current_state_2_s0
8	8.532	9.782	1.250	Low Pulse Width	LCLK	lpc_peri_inst/u_lpc_peri/lpc_addr_5_s0
9	8.532	9.782	1.250	Low Pulse Width	LCLK	lpc_peri_inst/u_lpc_peri/lpc_addr_6_s0
10	8.532	9.782	1.250	Low Pulse Width	LCLK	io_rd_sync_zero_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.601
Data Arrival Time	15.581
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_0_s0
To	io_addr_hit_s1
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/CLK
1.684	0.458	tC2Q	RF	22	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q
3.013	1.329	tNET	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/I3
3.835	0.822	tINS	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/F
4.656	0.821	tNET	FF	1	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/I2
5.688	1.032	tINS	FF	2	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/F
6.504	0.816	tNET	FF	1	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/I0
7.536	1.032	tINS	FF	4	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/F
8.351	0.815	tNET	FF	1	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/I3
9.383	1.032	tINS	FF	2	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/F
10.524	1.141	tNET	FF	1	R5C5[2][A]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/I2
11.346	0.822	tINS	FF	4	R5C5[2][A]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/F
12.485	1.139	tNET	FF	1	R9C6[1][B]	n35_s0/I1
13.307	0.822	tINS	FF	2	R9C6[1][B]	n35_s0/F
13.318	0.011	tNET	FF	1	R9C6[0][A]	n37_s0/I3
14.379	1.061	tINS	FR	1	R9C6[0][A]	n37_s0/F
15.581	1.202	tNET	RR	1	R9C6[1][A]	io_addr_hit_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R9C6[1][A]	io_addr_hit_s1/CLK
21.182	-0.043	tSu		1	R9C6[1][A]	io_addr_hit_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 6.623, 46.137%; route: 7.274, 50.671%; tC2Q: 0.458, 3.193%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path2

Path Summary:

Slack	6.551
Data Arrival Time	14.275
Data Required Time	20.826
From	lpc_peri_inst/u_lpc_peri/current_state_0_s0
To	io_addr_hit_s1
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/CLK
1.684	0.458	tC2Q	RF	22	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q
3.013	1.329	tNET	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/I3
3.835	0.822	tINS	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/F
4.656	0.821	tNET	FF	1	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/I2
5.688	1.032	tINS	FF	2	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/F
6.504	0.816	tNET	FF	1	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/I0
7.536	1.032	tINS	FF	4	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/F
8.351	0.815	tNET	FF	1	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/I3
9.383	1.032	tINS	FF	2	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/F
10.524	1.141	tNET	FF	1	R5C5[2][A]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/I2
11.346	0.822	tINS	FF	4	R5C5[2][A]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/F
12.485	1.139	tNET	FF	1	R9C6[1][B]	n35_s0/I1
13.307	0.822	tINS	FF	2	R9C6[1][B]	n35_s0/F
14.275	0.968	tNET	FF	1	R9C6[1][A]	io_addr_hit_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R9C6[1][A]	io_addr_hit_s1/CLK
20.826	-0.400	tSu		1	R9C6[1][A]	io_addr_hit_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.562, 42.624%; route: 7.029, 53.864%; tC2Q: 0.458, 3.512%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path3

Path Summary:

Slack	6.972
Data Arrival Time	13.854
Data Required Time	20.826
From	lpc_peri_inst/u_lpc_peri/current_state_0_s0
To	cnt_RdDelay_0_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/CLK
1.684	0.458	tC2Q	RF	22	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q
3.013	1.329	tNET	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/I3
3.835	0.822	tINS	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/F
4.656	0.821	tNET	FF	1	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/I2
5.688	1.032	tINS	FF	2	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/F
6.504	0.816	tNET	FF	1	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/I0
7.536	1.032	tINS	FF	4	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/F
8.351	0.815	tNET	FF	1	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/I3
9.383	1.032	tINS	FF	2	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/F
10.524	1.141	tNET	FF	1	R5C5[2][A]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/I2
11.346	0.822	tINS	FF	4	R5C5[2][A]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/F
12.822	1.476	tNET	FF	1	R12C6[1][A]	n99_s3/I2
13.854	1.032	tINS	FF	1	R12C6[1][A]	n99_s3/F
13.854	0.000	tNET	FF	1	R12C6[1][A]	cnt_RdDelay_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R12C6[1][A]	cnt_RdDelay_0_s0/CLK
20.826	-0.400	tSu		1	R12C6[1][A]	cnt_RdDelay_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.772, 45.707%; route: 6.398, 50.663%; tC2Q: 0.458, 3.629%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path4

Path Summary:

Slack	7.029
Data Arrival Time	13.796
Data Required Time	20.826
From	lpc_peri_inst/u_lpc_peri/current_state_0_s0
To	cnt_RdDelay_2_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/CLK
1.684	0.458	tC2Q	RF	22	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q
3.013	1.329	tNET	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/I3
3.835	0.822	tINS	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/F
4.656	0.821	tNET	FF	1	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/I2
5.688	1.032	tINS	FF	2	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/F
6.504	0.816	tNET	FF	1	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/I0
7.536	1.032	tINS	FF	4	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/F
8.351	0.815	tNET	FF	1	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/I3
9.383	1.032	tINS	FF	2	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/F
10.524	1.141	tNET	FF	1	R5C5[2][A]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/I2
11.346	0.822	tINS	FF	4	R5C5[2][A]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/F
12.337	0.992	tNET	FF	1	R12C5[3][A]	n98_s3/I1
12.963	0.626	tINS	FF	2	R12C5[3][A]	n98_s3/F
12.974	0.011	tNET	FF	1	R12C5[1][B]	n97_s3/I3
13.796	0.822	tINS	FF	1	R12C5[1][B]	n97_s3/F
13.796	0.000	tNET	FF	1	R12C5[1][B]	cnt_RdDelay_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R12C5[1][B]	cnt_RdDelay_2_s0/CLK
20.826	-0.400	tSu		1	R12C5[1][B]	cnt_RdDelay_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 6.188, 49.226%; route: 5.924, 47.128%; tC2Q: 0.458, 3.646%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path5

Path Summary:

Slack	7.029
Data Arrival Time	13.796
Data Required Time	20.826
From	lpc_peri_inst/u_lpc_peri/current_state_0_s0
To	cnt_RdDelay_3_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/CLK
1.684	0.458	tC2Q	RF	22	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q
3.013	1.329	tNET	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/I3
3.835	0.822	tINS	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/F
4.656	0.821	tNET	FF	1	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/I2
5.688	1.032	tINS	FF	2	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/F
6.504	0.816	tNET	FF	1	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/I0
7.536	1.032	tINS	FF	4	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/F
8.351	0.815	tNET	FF	1	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/I3
9.383	1.032	tINS	FF	2	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/F
10.524	1.141	tNET	FF	1	R5C5[2][A]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/I2
11.346	0.822	tINS	FF	4	R5C5[2][A]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/F
12.337	0.992	tNET	FF	1	R12C5[3][A]	n98_s3/I1
12.963	0.626	tINS	FF	2	R12C5[3][A]	n98_s3/F
12.974	0.011	tNET	FF	1	R12C5[2][A]	n96_s1/I3
13.796	0.822	tINS	FF	1	R12C5[2][A]	n96_s1/F
13.796	0.000	tNET	FF	1	R12C5[2][A]	cnt_RdDelay_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R12C5[2][A]	cnt_RdDelay_3_s0/CLK
20.826	-0.400	tSu		1	R12C5[2][A]	cnt_RdDelay_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 6.188, 49.226%; route: 5.924, 47.128%; tC2Q: 0.458, 3.646%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path6

Path Summary:

Slack	7.389
Data Arrival Time	13.436
Data Required Time	20.826
From	lpc_peri_inst/u_lpc_peri/current_state_0_s0
To	cnt_RdDelay_1_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/CLK
1.684	0.458	tC2Q	RF	22	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q
3.013	1.329	tNET	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/I3
3.835	0.822	tINS	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/F
4.656	0.821	tNET	FF	1	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/I2
5.688	1.032	tINS	FF	2	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/F
6.504	0.816	tNET	FF	1	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/I0
7.536	1.032	tINS	FF	4	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/F
8.351	0.815	tNET	FF	1	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/I3
9.383	1.032	tINS	FF	2	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/F
10.524	1.141	tNET	FF	1	R5C5[2][A]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/I2
11.346	0.822	tINS	FF	4	R5C5[2][A]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/F
12.337	0.992	tNET	FF	1	R12C5[0][A]	n98_s4/I3
13.436	1.099	tINS	FF	1	R12C5[0][A]	n98_s4/F
13.436	0.000	tNET	FF	1	R12C5[0][A]	cnt_RdDelay_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R12C5[0][A]	cnt_RdDelay_1_s0/CLK
20.826	-0.400	tSu		1	R12C5[0][A]	cnt_RdDelay_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.839, 47.819%; route: 5.913, 48.428%; tC2Q: 0.458, 3.754%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path7

Path Summary:

Slack	7.406
Data Arrival Time	13.776
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_2_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_4_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.684	0.458	tC2Q	RF	18	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q
3.013	1.329	tNET	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/I2
4.045	1.032	tINS	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/F
4.382	0.336	tNET	FF	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I3
5.481	1.099	tINS	FF	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
6.291	0.810	tNET	FF	1	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/I1
7.113	0.822	tINS	FF	2	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/F
7.124	0.011	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I2
8.223	1.099	tINS	FF	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
9.031	0.809	tNET	FF	1	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3
9.854	0.822	tINS	FF	5	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/F
11.184	1.331	tNET	FF	1	R7C7[3][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_1_s1/I3
12.245	1.061	tINS	FR	4	R7C7[3][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_1_s1/F
13.776	1.531	tNET	RR	1	R7C7[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R7C7[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_4_s0/CLK
21.182	-0.043	tSu		1	R7C7[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.935, 47.290%; route: 6.157, 49.058%; tC2Q: 0.458, 3.652%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path8

Path Summary:

Slack	7.406
Data Arrival Time	13.776
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_2_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_5_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.684	0.458	tC2Q	RF	18	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q
3.013	1.329	tNET	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/I2
4.045	1.032	tINS	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/F
4.382	0.336	tNET	FF	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I3
5.481	1.099	tINS	FF	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
6.291	0.810	tNET	FF	1	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/I1
7.113	0.822	tINS	FF	2	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/F
7.124	0.011	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I2
8.223	1.099	tINS	FF	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
9.031	0.809	tNET	FF	1	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3
9.854	0.822	tINS	FF	5	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/F
11.184	1.331	tNET	FF	1	R7C7[3][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_1_s1/I3
12.245	1.061	tINS	FR	4	R7C7[3][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_1_s1/F
13.776	1.531	tNET	RR	1	R7C7[1][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R7C7[1][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_5_s0/CLK
21.182	-0.043	tSu		1	R7C7[1][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.935, 47.290%; route: 6.157, 49.058%; tC2Q: 0.458, 3.652%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path9

Path Summary:

Slack	7.406
Data Arrival Time	13.776
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_2_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_6_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.684	0.458	tC2Q	RF	18	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q
3.013	1.329	tNET	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/I2
4.045	1.032	tINS	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/F
4.382	0.336	tNET	FF	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I3
5.481	1.099	tINS	FF	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
6.291	0.810	tNET	FF	1	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/I1
7.113	0.822	tINS	FF	2	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/F
7.124	0.011	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I2
8.223	1.099	tINS	FF	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
9.031	0.809	tNET	FF	1	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3
9.854	0.822	tINS	FF	5	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/F
11.184	1.331	tNET	FF	1	R7C7[3][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_1_s1/I3
12.245	1.061	tINS	FR	4	R7C7[3][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_1_s1/F
13.776	1.531	tNET	RR	1	R7C7[2][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R7C7[2][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_6_s0/CLK
21.182	-0.043	tSu		1	R7C7[2][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.935, 47.290%; route: 6.157, 49.058%; tC2Q: 0.458, 3.652%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path10

Path Summary:

Slack	7.779
Data Arrival Time	13.404
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_2_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_7_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.684	0.458	tC2Q	RF	18	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q
3.013	1.329	tNET	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/I2
4.045	1.032	tINS	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/F
4.382	0.336	tNET	FF	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I3
5.481	1.099	tINS	FF	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
6.291	0.810	tNET	FF	1	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/I1
7.113	0.822	tINS	FF	2	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/F
7.124	0.011	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I2
8.223	1.099	tINS	FF	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
9.031	0.809	tNET	FF	1	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3
9.854	0.822	tINS	FF	5	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/F
11.184	1.331	tNET	FF	1	R7C7[3][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_1_s1/I3
12.245	1.061	tINS	FR	4	R7C7[3][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_1_s1/F
13.404	1.159	tNET	RR	1	R7C6[2][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R7C6[2][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_7_s0/CLK
21.182	-0.043	tSu		1	R7C6[2][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.935, 48.735%; route: 5.785, 47.501%; tC2Q: 0.458, 3.764%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path11

Path Summary:

Slack	8.040
Data Arrival Time	13.143
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_2_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_3_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.684	0.458	tC2Q	RF	18	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q
3.013	1.329	tNET	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/I2
4.045	1.032	tINS	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/F
4.382	0.336	tNET	FF	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I3
5.481	1.099	tINS	FF	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
6.291	0.810	tNET	FF	1	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/I1
7.113	0.822	tINS	FF	2	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/F
7.124	0.011	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I2
8.223	1.099	tINS	FF	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
9.031	0.809	tNET	FF	1	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3
9.854	0.822	tINS	FF	5	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/F
11.184	1.331	tNET	FF	1	R7C7[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_0_s1/I1
11.986	0.802	tINS	FR	4	R7C7[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_0_s1/F
13.143	1.156	tNET	RR	1	R7C6[0][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R7C6[0][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_3_s0/CLK
21.182	-0.043	tSu		1	R7C6[0][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.676, 47.630%; route: 5.782, 48.524%; tC2Q: 0.458, 3.846%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path12

Path Summary:

Slack	8.401
Data Arrival Time	12.781
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_2_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_0_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.684	0.458	tC2Q	RF	18	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q
3.013	1.329	tNET	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/I2
4.045	1.032	tINS	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/F
4.382	0.336	tNET	FF	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I3
5.481	1.099	tINS	FF	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
6.291	0.810	tNET	FF	1	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/I1
7.113	0.822	tINS	FF	2	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/F
7.124	0.011	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I2
8.223	1.099	tINS	FF	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
9.031	0.809	tNET	FF	1	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3
9.854	0.822	tINS	FF	5	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/F
11.184	1.331	tNET	FF	1	R7C7[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_0_s1/I1
11.986	0.802	tINS	FR	4	R7C7[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_0_s1/F
12.781	0.795	tNET	RR	1	R8C6[1][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R8C6[1][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_0_s0/CLK
21.182	-0.043	tSu		1	R8C6[1][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.676, 49.120%; route: 5.421, 46.914%; tC2Q: 0.458, 3.966%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path13

Path Summary:

Slack	8.401
Data Arrival Time	12.781
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_2_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_2_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.684	0.458	tC2Q	RF	18	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q
3.013	1.329	tNET	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/I2
4.045	1.032	tINS	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/F
4.382	0.336	tNET	FF	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I3
5.481	1.099	tINS	FF	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
6.291	0.810	tNET	FF	1	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/I1
7.113	0.822	tINS	FF	2	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/F
7.124	0.011	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I2
8.223	1.099	tINS	FF	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
9.031	0.809	tNET	FF	1	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3
9.854	0.822	tINS	FF	5	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/F
11.184	1.331	tNET	FF	1	R7C7[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_0_s1/I1
11.986	0.802	tINS	FR	4	R7C7[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_0_s1/F
12.781	0.795	tNET	RR	1	R8C6[0][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R8C6[0][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_2_s0/CLK
21.182	-0.043	tSu		1	R8C6[0][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.676, 49.120%; route: 5.421, 46.914%; tC2Q: 0.458, 3.966%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path14

Path Summary:

Slack	8.488
Data Arrival Time	12.694
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_2_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_1_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.684	0.458	tC2Q	RF	18	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q
3.013	1.329	tNET	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/I2
4.045	1.032	tINS	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/F
4.382	0.336	tNET	FF	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I3
5.481	1.099	tINS	FF	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
6.291	0.810	tNET	FF	1	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/I1
7.113	0.822	tINS	FF	2	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/F
7.124	0.011	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I2
8.223	1.099	tINS	FF	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
9.031	0.809	tNET	FF	1	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3
9.854	0.822	tINS	FF	5	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/F
11.184	1.331	tNET	FF	1	R7C7[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_0_s1/I1
11.986	0.802	tINS	FR	4	R7C7[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_0_s1/F
12.694	0.708	tNET	RR	1	R8C7[2][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R8C7[2][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_1_s0/CLK
21.182	-0.043	tSu		1	R8C7[2][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.676, 49.493%; route: 5.334, 46.510%; tC2Q: 0.458, 3.997%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path15

Path Summary:

Slack	8.761
Data Arrival Time	12.422
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_2_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_8_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.684	0.458	tC2Q	RF	18	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q
3.013	1.329	tNET	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/I2
4.045	1.032	tINS	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/F
4.382	0.336	tNET	FF	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I3
5.481	1.099	tINS	FF	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
6.291	0.810	tNET	FF	1	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/I1
7.113	0.822	tINS	FF	2	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/F
7.124	0.011	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I2
8.223	1.099	tINS	FF	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
9.031	0.809	tNET	FF	1	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3
9.854	0.822	tINS	FF	5	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/F
10.690	0.836	tNET	FF	1	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/I1
11.716	1.026	tINS	FR	4	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/F
12.422	0.706	tNET	RR	1	R7C6[1][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_8_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R7C6[1][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_8_s0/CLK
21.182	-0.043	tSu		1	R7C6[1][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.900, 52.698%; route: 4.838, 43.208%; tC2Q: 0.458, 4.094%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path16

Path Summary:

Slack	8.761
Data Arrival Time	12.422
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_2_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_11_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.684	0.458	tC2Q	RF	18	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q
3.013	1.329	tNET	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/I2
4.045	1.032	tINS	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/F
4.382	0.336	tNET	FF	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I3
5.481	1.099	tINS	FF	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
6.291	0.810	tNET	FF	1	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/I1
7.113	0.822	tINS	FF	2	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/F
7.124	0.011	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I2
8.223	1.099	tINS	FF	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
9.031	0.809	tNET	FF	1	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3
9.854	0.822	tINS	FF	5	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/F
10.690	0.836	tNET	FF	1	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/I1
11.716	1.026	tINS	FR	4	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/F
12.422	0.706	tNET	RR	1	R7C6[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_11_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R7C6[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_11_s0/CLK
21.182	-0.043	tSu		1	R7C6[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.900, 52.698%; route: 4.838, 43.208%; tC2Q: 0.458, 4.094%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path17

Path Summary:

Slack	9.008
Data Arrival Time	11.817
Data Required Time	20.826
From	lpc_peri_inst/u_lpc_peri/current_state_4_s0
To	cnt_WrDelay_2_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/CLK
1.684	0.458	tC2Q	RF	16	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q
3.008	1.324	tNET	FF	1	R9C5[1][B]	lpc_peri_inst/u_lpc_peri/next_state_1_s10/I1
3.830	0.822	tINS	FF	1	R9C5[1][B]	lpc_peri_inst/u_lpc_peri/next_state_1_s10/F
3.836	0.005	tNET	FF	1	R9C5[3][A]	lpc_peri_inst/u_lpc_peri/next_state_1_s4/I3
4.935	1.099	tINS	FF	4	R9C5[3][A]	lpc_peri_inst/u_lpc_peri/next_state_1_s4/F
5.744	0.810	tNET	FF	1	R7C6[3][B]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s0/I1
6.776	1.032	tINS	FF	3	R7C6[3][B]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s0/F
7.597	0.820	tNET	FF	1	R5C7[3][A]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s/I3
8.629	1.032	tINS	FF	4	R5C7[3][A]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s/F
9.608	0.980	tNET	FF	1	R12C7[1][B]	n66_s3/I0
10.707	1.099	tINS	FF	2	R12C7[1][B]	n66_s3/F
10.718	0.011	tNET	FF	1	R12C7[1][A]	n65_s3/I3
11.817	1.099	tINS	FF	1	R12C7[1][A]	n65_s3/F
11.817	0.000	tNET	FF	1	R12C7[1][A]	cnt_WrDelay_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R12C7[1][A]	cnt_WrDelay_2_s0/CLK
20.826	-0.400	tSu		1	R12C7[1][A]	cnt_WrDelay_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 6.183, 58.377%; route: 3.950, 37.296%; tC2Q: 0.458, 4.327%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path18

Path Summary:

Slack	9.008
Data Arrival Time	11.817
Data Required Time	20.826
From	lpc_peri_inst/u_lpc_peri/current_state_4_s0
To	cnt_WrDelay_3_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/CLK
1.684	0.458	tC2Q	RF	16	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q
3.008	1.324	tNET	FF	1	R9C5[1][B]	lpc_peri_inst/u_lpc_peri/next_state_1_s10/I1
3.830	0.822	tINS	FF	1	R9C5[1][B]	lpc_peri_inst/u_lpc_peri/next_state_1_s10/F
3.836	0.005	tNET	FF	1	R9C5[3][A]	lpc_peri_inst/u_lpc_peri/next_state_1_s4/I3
4.935	1.099	tINS	FF	4	R9C5[3][A]	lpc_peri_inst/u_lpc_peri/next_state_1_s4/F
5.744	0.810	tNET	FF	1	R7C6[3][B]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s0/I1
6.776	1.032	tINS	FF	3	R7C6[3][B]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s0/F
7.597	0.820	tNET	FF	1	R5C7[3][A]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s/I3
8.629	1.032	tINS	FF	4	R5C7[3][A]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s/F
9.608	0.980	tNET	FF	1	R12C7[1][B]	n66_s3/I0
10.707	1.099	tINS	FF	2	R12C7[1][B]	n66_s3/F
10.718	0.011	tNET	FF	1	R12C7[0][A]	n64_s1/I3
11.817	1.099	tINS	FF	1	R12C7[0][A]	n64_s1/F
11.817	0.000	tNET	FF	1	R12C7[0][A]	cnt_WrDelay_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R12C7[0][A]	cnt_WrDelay_3_s0/CLK
20.826	-0.400	tSu		1	R12C7[0][A]	cnt_WrDelay_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 6.183, 58.377%; route: 3.950, 37.296%; tC2Q: 0.458, 4.327%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path19

Path Summary:

Slack	9.121
Data Arrival Time	12.061
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_2_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_9_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.684	0.458	tC2Q	RF	18	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q
3.013	1.329	tNET	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/I2
4.045	1.032	tINS	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/F
4.382	0.336	tNET	FF	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I3
5.481	1.099	tINS	FF	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
6.291	0.810	tNET	FF	1	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/I1
7.113	0.822	tINS	FF	2	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/F
7.124	0.011	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I2
8.223	1.099	tINS	FF	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
9.031	0.809	tNET	FF	1	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3
9.854	0.822	tINS	FF	5	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/F
10.690	0.836	tNET	FF	1	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/I1
11.716	1.026	tINS	FR	4	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/F
12.061	0.346	tNET	RR	1	R7C5[0][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_9_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R7C5[0][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_9_s0/CLK
21.182	-0.043	tSu		1	R7C5[0][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.900, 54.450%; route: 4.477, 41.320%; tC2Q: 0.458, 4.230%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path20

Path Summary:

Slack	9.121
Data Arrival Time	12.061
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_2_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_10_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.684	0.458	tC2Q	RF	18	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q
3.013	1.329	tNET	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/I2
4.045	1.032	tINS	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/F
4.382	0.336	tNET	FF	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I3
5.481	1.099	tINS	FF	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
6.291	0.810	tNET	FF	1	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/I1
7.113	0.822	tINS	FF	2	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/F
7.124	0.011	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I2
8.223	1.099	tINS	FF	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
9.031	0.809	tNET	FF	1	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3
9.854	0.822	tINS	FF	5	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/F
10.690	0.836	tNET	FF	1	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/I1
11.716	1.026	tINS	FR	4	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/F
12.061	0.346	tNET	RR	1	R7C5[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_10_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R7C5[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_10_s0/CLK
21.182	-0.043	tSu		1	R7C5[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.900, 54.450%; route: 4.477, 41.320%; tC2Q: 0.458, 4.230%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path21

Path Summary:

Slack	9.531
Data Arrival Time	11.295
Data Required Time	20.826
From	lpc_peri_inst/u_lpc_peri/current_state_2_s0
To	lpc_peri_inst/u_lpc_peri/current_state_3_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.684	0.458	tC2Q	RF	18	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q
3.013	1.329	tNET	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/I2
4.045	1.032	tINS	FF	1	R9C6[2][B]	lpc_peri_inst/u_lpc_peri/n423_s12/F
4.382	0.336	tNET	FF	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I3
5.481	1.099	tINS	FF	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
6.291	0.810	tNET	FF	1	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/I1
7.113	0.822	tINS	FF	2	R6C6[0][B]	lpc_peri_inst/u_lpc_peri/n423_s2/F
7.124	0.011	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I2
8.223	1.099	tINS	FF	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
9.031	0.809	tNET	FF	1	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3
9.854	0.822	tINS	FF	5	R5C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_3_s2/F
11.295	1.441	tNET	FF	1	R6C6[1][B]	lpc_peri_inst/u_lpc_peri/current_state_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R6C6[1][B]	lpc_peri_inst/u_lpc_peri/current_state_3_s0/CLK
20.826	-0.400	tSu		1	R6C6[1][B]	lpc_peri_inst/u_lpc_peri/current_state_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 4.874, 48.406%; route: 4.737, 47.042%; tC2Q: 0.458, 4.552%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path22

Path Summary:

Slack	9.701
Data Arrival Time	11.125
Data Required Time	20.826
From	lpc_peri_inst/u_lpc_peri/current_state_4_s0
To	cnt_WrDelay_1_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/CLK
1.684	0.458	tC2Q	RF	16	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q
3.008	1.324	tNET	FF	1	R9C5[1][B]	lpc_peri_inst/u_lpc_peri/next_state_1_s10/I1
3.830	0.822	tINS	FF	1	R9C5[1][B]	lpc_peri_inst/u_lpc_peri/next_state_1_s10/F
3.836	0.005	tNET	FF	1	R9C5[3][A]	lpc_peri_inst/u_lpc_peri/next_state_1_s4/I3
4.935	1.099	tINS	FF	4	R9C5[3][A]	lpc_peri_inst/u_lpc_peri/next_state_1_s4/F
5.744	0.810	tNET	FF	1	R7C6[3][B]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s0/I1
6.776	1.032	tINS	FF	3	R7C6[3][B]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s0/F
7.597	0.820	tNET	FF	1	R5C7[3][A]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s/I3
8.629	1.032	tINS	FF	4	R5C7[3][A]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s/F
10.093	1.464	tNET	FF	1	R12C6[0][A]	n66_s4/I2
11.125	1.032	tINS	FF	1	R12C6[0][A]	n66_s4/F
11.125	0.000	tNET	FF	1	R12C6[0][A]	cnt_WrDelay_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R12C6[0][A]	cnt_WrDelay_1_s0/CLK
20.826	-0.400	tSu		1	R12C6[0][A]	cnt_WrDelay_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 5.017, 50.681%; route: 4.424, 44.689%; tC2Q: 0.458, 4.630%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path23

Path Summary:

Slack	9.990
Data Arrival Time	10.836
Data Required Time	20.826
From	lpc_peri_inst/u_lpc_peri/current_state_0_s0
To	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/CLK
1.684	0.458	tC2Q	RF	22	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q
3.013	1.329	tNET	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/I3
3.835	0.822	tINS	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/F
4.656	0.821	tNET	FF	1	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/I2
5.688	1.032	tINS	FF	2	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/F
6.504	0.816	tNET	FF	1	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/I0
7.536	1.032	tINS	FF	4	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/F
8.351	0.815	tNET	FF	1	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/I3
9.383	1.032	tINS	FF	2	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/F
10.836	1.452	tNET	FF	1	R5C5[0][A]	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R5C5[0][A]	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0/CLK
20.826	-0.400	tSu		1	R5C5[0][A]	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 3.918, 40.771%; route: 5.234, 54.460%; tC2Q: 0.458, 4.769%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path24

Path Summary:

Slack	10.277
Data Arrival Time	10.549
Data Required Time	20.826
From	lpc_peri_inst/u_lpc_peri/current_state_4_s0
To	cnt_WrDelay_0_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/CLK
1.684	0.458	tC2Q	RF	16	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q
3.008	1.324	tNET	FF	1	R9C5[1][B]	lpc_peri_inst/u_lpc_peri/next_state_1_s10/I1
3.830	0.822	tINS	FF	1	R9C5[1][B]	lpc_peri_inst/u_lpc_peri/next_state_1_s10/F
3.836	0.005	tNET	FF	1	R9C5[3][A]	lpc_peri_inst/u_lpc_peri/next_state_1_s4/I3
4.935	1.099	tINS	FF	4	R9C5[3][A]	lpc_peri_inst/u_lpc_peri/next_state_1_s4/F
5.744	0.810	tNET	FF	1	R7C6[3][B]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s0/I1
6.776	1.032	tINS	FF	3	R7C6[3][B]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s0/F
7.597	0.820	tNET	FF	1	R5C7[3][A]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s/I3
8.629	1.032	tINS	FF	4	R5C7[3][A]	lpc_peri_inst/u_lpc_peri/io_wr_en_d_s/F
9.923	1.294	tNET	FF	1	R12C6[0][B]	n67_s4/I1
10.549	0.626	tINS	FF	1	R12C6[0][B]	n67_s4/F
10.549	0.000	tNET	FF	1	R12C6[0][B]	cnt_WrDelay_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R12C6[0][B]	cnt_WrDelay_0_s0/CLK
20.826	-0.400	tSu		1	R12C6[0][B]	cnt_WrDelay_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 4.611, 49.459%; route: 4.254, 45.625%; tC2Q: 0.458, 4.916%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Path25

Path Summary:

Slack	10.999
Data Arrival Time	10.183
Data Required Time	21.182
From	lpc_peri_inst/u_lpc_peri/current_state_0_s0
To	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.226	0.244	tNET	RR	1	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/CLK
1.684	0.458	tC2Q	RF	22	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q
3.013	1.329	tNET	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/I3
3.835	0.822	tINS	FF	1	R8C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s13/F
4.656	0.821	tNET	FF	1	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/I2
5.688	1.032	tINS	FF	2	R6C5[0][B]	lpc_peri_inst/u_lpc_peri/n423_s7/F
6.504	0.816	tNET	FF	1	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/I0
7.530	1.026	tINS	FR	4	R5C6[0][A]	lpc_peri_inst/u_lpc_peri/n423_s15/F
7.953	0.423	tNET	RR	1	R5C5[1][B]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s1/I0
8.775	0.822	tINS	RF	2	R5C5[1][B]	lpc_peri_inst/u_lpc_peri/io_rd_en_d_s1/F
8.786	0.011	tNET	FF	1	R5C5[0][B]	lpc_peri_inst/u_lpc_peri/n420_s0/I1
9.847	1.061	tINS	FR	1	R5C5[0][B]	lpc_peri_inst/u_lpc_peri/n420_s0/F
10.183	0.336	tNET	RR	1	R5C5[0][A]	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0/SET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					LCLK
20.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
20.982	0.982	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
21.226	0.244	tNET	RR	1	R5C5[0][A]	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0/CLK
21.182	-0.043	tSu		1	R5C5[0][A]	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%
Arrival Data Path Delay	cell: 4.763, 53.175%; route: 3.736, 41.708%; tC2Q: 0.458, 5.117%
Required Clock Path Delay	cell: 0.982, 80.100%; route: 0.244, 19.900%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.708
Data Arrival Time	1.737
Data Required Time	1.029
From	cnt_WrDelay_1_s0
To	cnt_WrDelay_1_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C6[0][A]	cnt_WrDelay_1_s0/CLK
1.362	0.333	tC2Q	RR	5	R12C6[0][A]	cnt_WrDelay_1_s0/Q
1.365	0.002	tNET	RR	1	R12C6[0][A]	n66_s4/I1
1.737	0.372	tINS	RF	1	R12C6[0][A]	n66_s4/F
1.737	0.000	tNET	FF	1	R12C6[0][A]	cnt_WrDelay_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C6[0][A]	cnt_WrDelay_1_s0/CLK
1.029	0.000	tHld		1	R12C6[0][A]	cnt_WrDelay_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path2

Path Summary:

Slack	0.709
Data Arrival Time	1.738
Data Required Time	1.029
From	io_rd_data_5_s6
To	io_rd_data_5_s6
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C4[0][A]	io_rd_data_5_s6/CLK
1.362	0.333	tC2Q	RR	5	R12C4[0][A]	io_rd_data_5_s6/Q
1.366	0.004	tNET	RR	1	R12C4[0][A]	n106_s5/I0
1.738	0.372	tINS	RF	1	R12C4[0][A]	n106_s5/F
1.738	0.000	tNET	FF	1	R12C4[0][A]	io_rd_data_5_s6/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C4[0][A]	io_rd_data_5_s6/CLK
1.029	0.000	tHld		1	R12C4[0][A]	io_rd_data_5_s6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path3

Path Summary:

Slack	0.709
Data Arrival Time	1.738
Data Required Time	1.029
From	cnt_RdDelay_1_s0
To	cnt_RdDelay_1_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C5[0][A]	cnt_RdDelay_1_s0/CLK
1.362	0.333	tC2Q	RR	6	R12C5[0][A]	cnt_RdDelay_1_s0/Q
1.366	0.004	tNET	RR	1	R12C5[0][A]	n98_s4/I1
1.738	0.372	tINS	RF	1	R12C5[0][A]	n98_s4/F
1.738	0.000	tNET	FF	1	R12C5[0][A]	cnt_RdDelay_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C5[0][A]	cnt_RdDelay_1_s0/CLK
1.029	0.000	tHld		1	R12C5[0][A]	cnt_RdDelay_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path4

Path Summary:

Slack	0.709
Data Arrival Time	1.738
Data Required Time	1.029
From	cnt_WrDelay_2_s0
To	cnt_WrDelay_2_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C7[1][A]	cnt_WrDelay_2_s0/CLK
1.362	0.333	tC2Q	RR	4	R12C7[1][A]	cnt_WrDelay_2_s0/Q
1.366	0.004	tNET	RR	1	R12C7[1][A]	n65_s3/I0
1.738	0.372	tINS	RF	1	R12C7[1][A]	n65_s3/F
1.738	0.000	tNET	FF	1	R12C7[1][A]	cnt_WrDelay_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C7[1][A]	cnt_WrDelay_2_s0/CLK
1.029	0.000	tHld		1	R12C7[1][A]	cnt_WrDelay_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path5

Path Summary:

Slack	0.709
Data Arrival Time	1.738
Data Required Time	1.029
From	cnt_WrDelay_3_s0
To	cnt_WrDelay_3_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C7[0][A]	cnt_WrDelay_3_s0/CLK
1.362	0.333	tC2Q	RR	3	R12C7[0][A]	cnt_WrDelay_3_s0/Q
1.366	0.004	tNET	RR	1	R12C7[0][A]	n64_s1/I2
1.738	0.372	tINS	RF	1	R12C7[0][A]	n64_s1/F
1.738	0.000	tNET	FF	1	R12C7[0][A]	cnt_WrDelay_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C7[0][A]	cnt_WrDelay_3_s0/CLK
1.029	0.000	tHld		1	R12C7[0][A]	cnt_WrDelay_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path6

Path Summary:

Slack	0.710
Data Arrival Time	1.739
Data Required Time	1.029
From	cnt_RdDelay_0_s0
To	cnt_RdDelay_0_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C6[1][A]	cnt_RdDelay_0_s0/CLK
1.362	0.333	tC2Q	RR	7	R12C6[1][A]	cnt_RdDelay_0_s0/Q
1.367	0.005	tNET	RR	1	R12C6[1][A]	n99_s3/I0
1.739	0.372	tINS	RF	1	R12C6[1][A]	n99_s3/F
1.739	0.000	tNET	FF	1	R12C6[1][A]	cnt_RdDelay_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C6[1][A]	cnt_RdDelay_0_s0/CLK
1.029	0.000	tHld		1	R12C6[1][A]	cnt_RdDelay_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path7

Path Summary:

Slack	0.943
Data Arrival Time	1.972
Data Required Time	1.029
From	cnt_WrDelay_3_s0
To	io_wr_sync_zero_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C7[0][A]	cnt_WrDelay_3_s0/CLK
1.362	0.333	tC2Q	RF	3	R12C7[0][A]	cnt_WrDelay_3_s0/Q
1.600	0.238	tNET	FF	1	R12C7[0][B]	n71_s4/I2
1.972	0.372	tINS	FF	1	R12C7[0][B]	n71_s4/F
1.972	0.000	tNET	FF	1	R12C7[0][B]	io_wr_sync_zero_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C7[0][B]	io_wr_sync_zero_s0/CLK
1.029	0.000	tHld		1	R12C7[0][B]	io_wr_sync_zero_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.372, 39.447%; route: 0.238, 25.207%; tC2Q: 0.333, 35.347%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path8

Path Summary:

Slack	0.944
Data Arrival Time	1.973
Data Required Time	1.029
From	cnt_RdDelay_2_s0
To	cnt_RdDelay_3_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C5[1][B]	cnt_RdDelay_2_s0/CLK
1.362	0.333	tC2Q	RR	5	R12C5[1][B]	cnt_RdDelay_2_s0/Q
1.601	0.239	tNET	RR	1	R12C5[2][A]	n96_s1/I0
1.973	0.372	tINS	RF	1	R12C5[2][A]	n96_s1/F
1.973	0.000	tNET	FF	1	R12C5[2][A]	cnt_RdDelay_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C5[2][A]	cnt_RdDelay_3_s0/CLK
1.029	0.000	tHld		1	R12C5[2][A]	cnt_RdDelay_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.372, 39.403%; route: 0.239, 25.289%; tC2Q: 0.333, 35.307%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path9

Path Summary:

Slack	0.950
Data Arrival Time	1.979
Data Required Time	1.029
From	cnt_RdDelay_1_s0
To	cnt_RdDelay_2_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C5[0][A]	cnt_RdDelay_1_s0/CLK
1.362	0.333	tC2Q	RF	6	R12C5[0][A]	cnt_RdDelay_1_s0/Q
1.607	0.245	tNET	FF	1	R12C5[1][B]	n97_s3/I2
1.979	0.372	tINS	FF	1	R12C5[1][B]	n97_s3/F
1.979	0.000	tNET	FF	1	R12C5[1][B]	cnt_RdDelay_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C5[1][B]	cnt_RdDelay_2_s0/CLK
1.029	0.000	tHld		1	R12C5[1][B]	cnt_RdDelay_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.372, 39.155%; route: 0.245, 25.760%; tC2Q: 0.333, 35.085%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path10

Path Summary:

Slack	0.957
Data Arrival Time	1.985
Data Required Time	1.029
From	cnt_RdDelay_2_s0
To	io_rd_sync_zero_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C5[1][B]	cnt_RdDelay_2_s0/CLK
1.362	0.333	tC2Q	RR	5	R12C5[1][B]	cnt_RdDelay_2_s0/Q
1.613	0.251	tNET	RR	1	R12C5[1][A]	n106_s7/I1
1.985	0.372	tINS	RF	1	R12C5[1][A]	n106_s7/F
1.985	0.000	tNET	FF	1	R12C5[1][A]	io_rd_sync_zero_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C5[1][A]	io_rd_sync_zero_s0/CLK
1.029	0.000	tHld		1	R12C5[1][A]	io_rd_sync_zero_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.372, 38.891%; route: 0.251, 26.260%; tC2Q: 0.333, 34.849%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path11

Path Summary:

Slack	1.061
Data Arrival Time	2.090
Data Required Time	1.029
From	cnt_WrDelay_0_s0
To	cnt_WrDelay_0_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C6[0][B]	cnt_WrDelay_0_s0/CLK
1.362	0.333	tC2Q	RR	6	R12C6[0][B]	cnt_WrDelay_0_s0/Q
1.366	0.004	tNET	RR	1	R12C6[0][B]	n67_s4/I0
2.090	0.724	tINS	RR	1	R12C6[0][B]	n67_s4/F
2.090	0.000	tNET	RR	1	R12C6[0][B]	cnt_WrDelay_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R12C6[0][B]	cnt_WrDelay_0_s0/CLK
1.029	0.000	tHld		1	R12C6[0][B]	cnt_WrDelay_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path12

Path Summary:

Slack	1.224
Data Arrival Time	2.268
Data Required Time	1.044
From	lpc_peri_inst/u_lpc_peri/current_state_1_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_9_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R7C7[0][A]	lpc_peri_inst/u_lpc_peri/current_state_1_s0/CLK
1.362	0.333	tC2Q	RR	22	R7C7[0][A]	lpc_peri_inst/u_lpc_peri/current_state_1_s0/Q
1.638	0.276	tNET	RR	1	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/I0
2.023	0.385	tINS	RR	4	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/F
2.268	0.245	tNET	RR	1	R7C5[0][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_9_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R7C5[0][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_9_s0/CLK
1.044	0.015	tHld		1	R7C5[0][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.385, 31.081%; route: 0.520, 42.009%; tC2Q: 0.333, 26.910%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path13

Path Summary:

Slack	1.224
Data Arrival Time	2.268
Data Required Time	1.044
From	lpc_peri_inst/u_lpc_peri/current_state_1_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_10_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R7C7[0][A]	lpc_peri_inst/u_lpc_peri/current_state_1_s0/CLK
1.362	0.333	tC2Q	RR	22	R7C7[0][A]	lpc_peri_inst/u_lpc_peri/current_state_1_s0/Q
1.638	0.276	tNET	RR	1	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/I0
2.023	0.385	tINS	RR	4	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/F
2.268	0.245	tNET	RR	1	R7C5[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_10_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R7C5[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_10_s0/CLK
1.044	0.015	tHld		1	R7C5[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.385, 31.081%; route: 0.520, 42.009%; tC2Q: 0.333, 26.910%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path14

Path Summary:

Slack	1.481
Data Arrival Time	2.525
Data Required Time	1.044
From	lpc_peri_inst/u_lpc_peri/current_state_1_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_8_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R7C7[0][A]	lpc_peri_inst/u_lpc_peri/current_state_1_s0/CLK
1.362	0.333	tC2Q	RR	22	R7C7[0][A]	lpc_peri_inst/u_lpc_peri/current_state_1_s0/Q
1.638	0.276	tNET	RR	1	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/I0
2.023	0.385	tINS	RR	4	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/F
2.525	0.502	tNET	RR	1	R7C6[1][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_8_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R7C6[1][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_8_s0/CLK
1.044	0.015	tHld		1	R7C6[1][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.385, 25.731%; route: 0.778, 51.990%; tC2Q: 0.333, 22.278%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path15

Path Summary:

Slack	1.481
Data Arrival Time	2.525
Data Required Time	1.044
From	lpc_peri_inst/u_lpc_peri/current_state_1_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_11_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R7C7[0][A]	lpc_peri_inst/u_lpc_peri/current_state_1_s0/CLK
1.362	0.333	tC2Q	RR	22	R7C7[0][A]	lpc_peri_inst/u_lpc_peri/current_state_1_s0/Q
1.638	0.276	tNET	RR	1	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/I0
2.023	0.385	tINS	RR	4	R7C5[2][B]	lpc_peri_inst/u_lpc_peri/rd_addr_en_2_s1/F
2.525	0.502	tNET	RR	1	R7C6[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_11_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R7C6[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_11_s0/CLK
1.044	0.015	tHld		1	R7C6[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.385, 25.731%; route: 0.778, 51.990%; tC2Q: 0.333, 22.278%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path16

Path Summary:

Slack	1.788
Data Arrival Time	2.832
Data Required Time	1.044
From	lpc_peri_inst/u_lpc_peri/lpc_addr_15_s0
To	io_addr_hit_s1
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R8C6[2][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_15_s0/CLK
1.362	0.333	tC2Q	RF	1	R8C6[2][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_15_s0/Q
1.594	0.231	tNET	FF	1	R9C6[0][A]	n37_s0/I1
1.979	0.385	tINS	FR	1	R9C6[0][A]	n37_s0/F
2.832	0.854	tNET	RR	1	R9C6[1][A]	io_addr_hit_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R9C6[1][A]	io_addr_hit_s1/CLK
1.044	0.015	tHld		1	R9C6[1][A]	io_addr_hit_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.385, 21.351%; route: 1.085, 60.163%; tC2Q: 0.333, 18.486%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path17

Path Summary:

Slack	1.874
Data Arrival Time	2.903
Data Required Time	1.029
From	lpc_peri_inst/u_lpc_peri/current_state_4_s0
To	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/CLK
1.362	0.333	tC2Q	RF	16	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q
1.631	0.268	tNET	FF	1	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/I0
2.016	0.385	tINS	FR	2	R6C5[2][A]	lpc_peri_inst/u_lpc_peri/n423_s0/F
2.903	0.887	tNET	RR	1	R5C5[0][A]	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R5C5[0][A]	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0/CLK
1.029	0.000	tHld		1	R5C5[0][A]	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.385, 20.545%; route: 1.156, 61.667%; tC2Q: 0.333, 17.788%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path18

Path Summary:

Slack	2.305
Data Arrival Time	3.333
Data Required Time	1.029
From	lpc_peri_inst/u_lpc_peri/current_state_0_s0
To	lpc_peri_inst/u_lpc_peri/io_wren_sm_d1_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/CLK
1.362	0.333	tC2Q	RF	22	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q
1.617	0.255	tNET	FF	1	R5C6[1][A]	lpc_peri_inst/u_lpc_peri/n423_s9/I1
1.989	0.372	tINS	FF	1	R5C6[1][A]	lpc_peri_inst/u_lpc_peri/n423_s9/F
1.994	0.004	tNET	FF	1	R5C6[0][B]	lpc_peri_inst/u_lpc_peri/next_state_0_s2/I2
2.366	0.372	tINS	FF	6	R5C6[0][B]	lpc_peri_inst/u_lpc_peri/next_state_0_s2/F
2.609	0.244	tNET	FF	1	R5C7[0][A]	lpc_peri_inst/u_lpc_peri/n432_s1/I2
3.333	0.724	tINS	FR	1	R5C7[0][A]	lpc_peri_inst/u_lpc_peri/n432_s1/F
3.333	0.000	tNET	RR	1	R5C7[0][A]	lpc_peri_inst/u_lpc_peri/io_wren_sm_d1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R5C7[0][A]	lpc_peri_inst/u_lpc_peri/io_wren_sm_d1_s0/CLK
1.029	0.000	tHld		1	R5C7[0][A]	lpc_peri_inst/u_lpc_peri/io_wren_sm_d1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 1.468, 63.701%; route: 0.503, 21.835%; tC2Q: 0.333, 14.464%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path19

Path Summary:

Slack	2.318
Data Arrival Time	3.362
Data Required Time	1.044
From	lpc_peri_inst/u_lpc_peri/current_state_4_s0
To	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/CLK
1.362	0.333	tC2Q	RF	16	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q
1.610	0.247	tNET	FF	1	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/I1
1.995	0.385	tINS	FR	2	R6C6[1][A]	lpc_peri_inst/u_lpc_peri/n420_s1/F
2.569	0.575	tNET	RR	1	R5C5[0][B]	lpc_peri_inst/u_lpc_peri/n420_s0/I0
3.125	0.556	tINS	RR	1	R5C5[0][B]	lpc_peri_inst/u_lpc_peri/n420_s0/F
3.362	0.237	tNET	RR	1	R5C5[0][A]	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0/SET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R5C5[0][A]	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0/CLK
1.044	0.015	tHld		1	R5C5[0][A]	lpc_peri_inst/u_lpc_peri/io_rden_sm_d1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.941, 40.333%; route: 1.059, 45.380%; tC2Q: 0.333, 14.287%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path20

Path Summary:

Slack	2.569
Data Arrival Time	3.613
Data Required Time	1.044
From	lpc_peri_inst/u_lpc_peri/current_state_3_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_15_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R6C6[1][B]	lpc_peri_inst/u_lpc_peri/current_state_3_s0/CLK
1.362	0.333	tC2Q	RR	21	R6C6[1][B]	lpc_peri_inst/u_lpc_peri/current_state_3_s0/Q
1.903	0.541	tNET	RR	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I2
2.288	0.385	tINS	RR	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
2.555	0.267	tNET	RR	1	R7C6[0][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_3_s3/I1
3.111	0.556	tINS	RR	4	R7C6[0][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_3_s3/F
3.613	0.502	tNET	RR	1	R8C6[2][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_15_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R8C6[2][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_15_s0/CLK
1.044	0.015	tHld		1	R8C6[2][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.941, 36.412%; route: 1.310, 50.689%; tC2Q: 0.333, 12.898%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path21

Path Summary:

Slack	2.635
Data Arrival Time	3.664
Data Required Time	1.029
From	lpc_peri_inst/u_lpc_peri/current_state_4_s0
To	lpc_peri_inst/u_lpc_peri/current_state_4_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/CLK
1.362	0.333	tC2Q	RR	16	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/Q
1.943	0.581	tNET	RR	1	R8C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_4_s3/I3
2.315	0.372	tINS	RF	1	R8C5[1][A]	lpc_peri_inst/u_lpc_peri/next_state_4_s3/F
2.319	0.004	tNET	FF	1	R8C5[1][B]	lpc_peri_inst/u_lpc_peri/next_state_4_s5/I1
2.691	0.372	tINS	FF	8	R8C5[1][B]	lpc_peri_inst/u_lpc_peri/next_state_4_s5/F
3.664	0.972	tNET	FF	1	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0/CLK
1.029	0.000	tHld		1	R6C6[2][A]	lpc_peri_inst/u_lpc_peri/current_state_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.744, 28.239%; route: 1.557, 59.109%; tC2Q: 0.333, 12.652%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path22

Path Summary:

Slack	2.643
Data Arrival Time	3.687
Data Required Time	1.044
From	lpc_peri_inst/u_lpc_peri/current_state_3_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_12_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R6C6[1][B]	lpc_peri_inst/u_lpc_peri/current_state_3_s0/CLK
1.362	0.333	tC2Q	RR	21	R6C6[1][B]	lpc_peri_inst/u_lpc_peri/current_state_3_s0/Q
1.903	0.541	tNET	RR	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I2
2.288	0.385	tINS	RR	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
2.555	0.267	tNET	RR	1	R7C6[0][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_3_s3/I1
3.111	0.556	tINS	RR	4	R7C6[0][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_3_s3/F
3.687	0.576	tNET	RR	1	R8C7[0][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_12_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R8C7[0][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_12_s0/CLK
1.044	0.015	tHld		1	R8C7[0][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.941, 35.399%; route: 1.384, 52.062%; tC2Q: 0.333, 12.539%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path23

Path Summary:

Slack	2.643
Data Arrival Time	3.687
Data Required Time	1.044
From	lpc_peri_inst/u_lpc_peri/current_state_3_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_13_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R6C6[1][B]	lpc_peri_inst/u_lpc_peri/current_state_3_s0/CLK
1.362	0.333	tC2Q	RR	21	R6C6[1][B]	lpc_peri_inst/u_lpc_peri/current_state_3_s0/Q
1.903	0.541	tNET	RR	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I2
2.288	0.385	tINS	RR	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
2.555	0.267	tNET	RR	1	R7C6[0][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_3_s3/I1
3.111	0.556	tINS	RR	4	R7C6[0][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_3_s3/F
3.687	0.576	tNET	RR	1	R8C7[0][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_13_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R8C7[0][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_13_s0/CLK
1.044	0.015	tHld		1	R8C7[0][B]	lpc_peri_inst/u_lpc_peri/lpc_addr_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.941, 35.399%; route: 1.384, 52.062%; tC2Q: 0.333, 12.539%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path24

Path Summary:

Slack	2.643
Data Arrival Time	3.687
Data Required Time	1.044
From	lpc_peri_inst/u_lpc_peri/current_state_3_s0
To	lpc_peri_inst/u_lpc_peri/lpc_addr_14_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R6C6[1][B]	lpc_peri_inst/u_lpc_peri/current_state_3_s0/CLK
1.362	0.333	tC2Q	RR	21	R6C6[1][B]	lpc_peri_inst/u_lpc_peri/current_state_3_s0/Q
1.903	0.541	tNET	RR	1	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/I2
2.288	0.385	tINS	RR	2	R9C6[3][A]	lpc_peri_inst/u_lpc_peri/n423_s6/F
2.555	0.267	tNET	RR	1	R7C6[0][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_3_s3/I1
3.111	0.556	tINS	RR	4	R7C6[0][A]	lpc_peri_inst/u_lpc_peri/rd_addr_en_3_s3/F
3.687	0.576	tNET	RR	1	R8C7[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_14_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R8C7[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_14_s0/CLK
1.044	0.015	tHld		1	R8C7[1][A]	lpc_peri_inst/u_lpc_peri/lpc_addr_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 0.941, 35.399%; route: 1.384, 52.062%; tC2Q: 0.333, 12.539%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Path25

Path Summary:

Slack	2.648
Data Arrival Time	3.677
Data Required Time	1.029
From	lpc_peri_inst/u_lpc_peri/current_state_0_s0
To	lpc_peri_inst/u_lpc_peri/current_state_2_s0
Launch Clk	LCLK:[R]
Latch Clk	LCLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/CLK
1.362	0.333	tC2Q	RR	22	R5C7[2][A]	lpc_peri_inst/u_lpc_peri/current_state_0_s0/Q
1.945	0.583	tNET	RR	1	R6C5[3][B]	lpc_peri_inst/u_lpc_peri/next_state_2_s2/I0
2.317	0.372	tINS	RF	2	R6C5[3][B]	lpc_peri_inst/u_lpc_peri/next_state_2_s2/F
2.326	0.009	tNET	FF	1	R6C5[1][B]	lpc_peri_inst/u_lpc_peri/next_state_2_s1/I0
3.052	0.726	tINS	FR	4	R6C5[1][B]	lpc_peri_inst/u_lpc_peri/next_state_2_s1/F
3.677	0.625	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					LCLK
0.000	0.000	tCL	RR	1	IOL15[A]	LCLK_ibuf/I
0.844	0.844	tINS	RR	35	IOL15[A]	LCLK_ibuf/O
1.029	0.185	tNET	RR	1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK
1.029	0.000	tHld		1	R6C5[0][A]	lpc_peri_inst/u_lpc_peri/current_state_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay	cell: 1.098, 41.466%; route: 1.217, 45.946%; tC2Q: 0.333, 12.588%
Required Clock Path Delay	cell: 0.844, 82.061%; route: 0.185, 17.939%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	8.532
Actual Width:	9.782
Required Width:	1.250
Type:	Low Pulse Width
Clock:	LCLK
Objects:	io_wr_sync_zero_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			LCLK
10.000	0.000	tCL	FF	LCLK_ibuf/I
10.984	0.984	tINS	FF	LCLK_ibuf/O
11.247	0.262	tNET	FF	io_wr_sync_zero_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			LCLK
20.000	0.000	tCL	RR	LCLK_ibuf/I
20.844	0.844	tINS	RR	LCLK_ibuf/O
21.029	0.185	tNET	RR	io_wr_sync_zero_s0/CLK

MPW2

MPW Summary:

Slack:	8.532
Actual Width:	9.782
Required Width:	1.250
Type:	Low Pulse Width
Clock:	LCLK
Objects:	cnt_WrDelay_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			LCLK
10.000	0.000	tCL	FF	LCLK_ibuf/I
10.984	0.984	tINS	FF	LCLK_ibuf/O
11.247	0.262	tNET	FF	cnt_WrDelay_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			LCLK
20.000	0.000	tCL	RR	LCLK_ibuf/I
20.844	0.844	tINS	RR	LCLK_ibuf/O
21.029	0.185	tNET	RR	cnt_WrDelay_2_s0/CLK

MPW3

MPW Summary:

Slack:	8.532
Actual Width:	9.782
Required Width:	1.250
Type:	Low Pulse Width
Clock:	LCLK
Objects:	cnt_RdDelay_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			LCLK
10.000	0.000	tCL	FF	LCLK_ibuf/I
10.984	0.984	tINS	FF	LCLK_ibuf/O
11.247	0.262	tNET	FF	cnt_RdDelay_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			LCLK
20.000	0.000	tCL	RR	LCLK_ibuf/I
20.844	0.844	tINS	RR	LCLK_ibuf/O
21.029	0.185	tNET	RR	cnt_RdDelay_3_s0/CLK

MPW4

MPW Summary:

Slack:	8.532
Actual Width:	9.782
Required Width:	1.250
Type:	Low Pulse Width
Clock:	LCLK
Objects:	lpc_peri_inst/u_lpc_peri/current_state_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			LCLK
10.000	0.000	tCL	FF	LCLK_ibuf/I
10.984	0.984	tINS	FF	LCLK_ibuf/O
11.247	0.262	tNET	FF	lpc_peri_inst/u_lpc_peri/current_state_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			LCLK
20.000	0.000	tCL	RR	LCLK_ibuf/I
20.844	0.844	tINS	RR	LCLK_ibuf/O
21.029	0.185	tNET	RR	lpc_peri_inst/u_lpc_peri/current_state_1_s0/CLK

MPW5

MPW Summary:

Slack:	8.532
Actual Width:	9.782
Required Width:	1.250
Type:	Low Pulse Width
Clock:	LCLK
Objects:	lpc_peri_inst/u_lpc_peri/lpc_addr_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			LCLK
10.000	0.000	tCL	FF	LCLK_ibuf/I
10.984	0.984	tINS	FF	LCLK_ibuf/O
11.247	0.262	tNET	FF	lpc_peri_inst/u_lpc_peri/lpc_addr_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			LCLK
20.000	0.000	tCL	RR	LCLK_ibuf/I
20.844	0.844	tINS	RR	LCLK_ibuf/O
21.029	0.185	tNET	RR	lpc_peri_inst/u_lpc_peri/lpc_addr_3_s0/CLK

MPW6

MPW Summary:

Slack:	8.532
Actual Width:	9.782
Required Width:	1.250
Type:	Low Pulse Width
Clock:	LCLK
Objects:	lpc_peri_inst/u_lpc_peri/lpc_addr_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			LCLK
10.000	0.000	tCL	FF	LCLK_ibuf/I
10.984	0.984	tINS	FF	LCLK_ibuf/O
11.247	0.262	tNET	FF	lpc_peri_inst/u_lpc_peri/lpc_addr_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			LCLK
20.000	0.000	tCL	RR	LCLK_ibuf/I
20.844	0.844	tINS	RR	LCLK_ibuf/O
21.029	0.185	tNET	RR	lpc_peri_inst/u_lpc_peri/lpc_addr_4_s0/CLK

MPW7

MPW Summary:

Slack:	8.532
Actual Width:	9.782
Required Width:	1.250
Type:	Low Pulse Width
Clock:	LCLK
Objects:	lpc_peri_inst/u_lpc_peri/current_state_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			LCLK
10.000	0.000	tCL	FF	LCLK_ibuf/I
10.984	0.984	tINS	FF	LCLK_ibuf/O
11.247	0.262	tNET	FF	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			LCLK
20.000	0.000	tCL	RR	LCLK_ibuf/I
20.844	0.844	tINS	RR	LCLK_ibuf/O
21.029	0.185	tNET	RR	lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK

MPW8

MPW Summary:

Slack:	8.532
Actual Width:	9.782
Required Width:	1.250
Type:	Low Pulse Width
Clock:	LCLK
Objects:	lpc_peri_inst/u_lpc_peri/lpc_addr_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			LCLK
10.000	0.000	tCL	FF	LCLK_ibuf/I
10.984	0.984	tINS	FF	LCLK_ibuf/O
11.247	0.262	tNET	FF	lpc_peri_inst/u_lpc_peri/lpc_addr_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			LCLK
20.000	0.000	tCL	RR	LCLK_ibuf/I
20.844	0.844	tINS	RR	LCLK_ibuf/O
21.029	0.185	tNET	RR	lpc_peri_inst/u_lpc_peri/lpc_addr_5_s0/CLK

MPW9

MPW Summary:

Slack:	8.532
Actual Width:	9.782
Required Width:	1.250
Type:	Low Pulse Width
Clock:	LCLK
Objects:	lpc_peri_inst/u_lpc_peri/lpc_addr_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			LCLK
10.000	0.000	tCL	FF	LCLK_ibuf/I
10.984	0.984	tINS	FF	LCLK_ibuf/O
11.247	0.262	tNET	FF	lpc_peri_inst/u_lpc_peri/lpc_addr_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			LCLK
20.000	0.000	tCL	RR	LCLK_ibuf/I
20.844	0.844	tINS	RR	LCLK_ibuf/O
21.029	0.185	tNET	RR	lpc_peri_inst/u_lpc_peri/lpc_addr_6_s0/CLK

MPW10

MPW Summary:

Slack:	8.532
Actual Width:	9.782
Required Width:	1.250
Type:	Low Pulse Width
Clock:	LCLK
Objects:	io_rd_sync_zero_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			LCLK
10.000	0.000	tCL	FF	LCLK_ibuf/I
10.984	0.984	tINS	FF	LCLK_ibuf/O
11.247	0.262	tNET	FF	io_rd_sync_zero_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			LCLK
20.000	0.000	tCL	RR	LCLK_ibuf/I
20.844	0.844	tINS	RR	LCLK_ibuf/O
21.029	0.185	tNET	RR	io_rd_sync_zero_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
35	LCLK_d	5.601	0.262
22	current_state[0]	5.601	1.329
22	current_state[1]	6.692	1.361
21	current_state[3]	5.637	1.348
18	current_state[2]	6.278	1.334
16	current_state[4]	5.875	1.639
8	next_state[4]	8.914	1.447
7	cnt_RdDelay[0]	15.793	0.832
6	cnt_RdDelay[1]	15.799	0.426
6	next_state_0_6	8.752	0.830

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R8C7	68.06%
R7C7	65.28%
R7C6	56.94%
R12C5	56.94%
R7C5	51.39%
R12C7	51.39%
R8C6	51.39%
R6C5	50.00%
R12C6	48.61%
R6C6	48.61%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command