Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\vito\Desktop\xcorr_update\Gowin_XCORR_RefDesign\XCORR_17_512_13_case\project\src\top.v
C:\Users\vito\Desktop\xcorr_update\Gowin_XCORR_RefDesign\XCORR_17_512_13_case\project\src\xcorr\xcorr.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\gw_jtag.v
C:\Users\vito\Desktop\xcorr_update\Gowin_XCORR_RefDesign\XCORR_17_512_13_case\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue May 27 16:13:02 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.553s, Peak memory usage = 543.789MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.136s, Peak memory usage = 543.789MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 543.789MB
    Optimizing Phase 2: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.525s, Peak memory usage = 543.789MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 543.789MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 543.789MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 543.789MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 543.789MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 543.789MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.217s, Peak memory usage = 543.789MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 543.789MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 543.789MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 543.789MB
Generate output files:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.136s, Peak memory usage = 543.789MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 543.789MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 90
I/O Buf 90
    IBUF 5
    OBUF 85
Register 971
    DFFRE 73
    DFFPE 37
    DFFCE 861
LUT 882
    LUT2 128
    LUT3 233
    LUT4 521
MUX 1
    MUX16 1
ALU 41
    ALU 41
INV 25
    INV 25
DSP
    MULTALU27X18 1
BSRAM 38
    SDPB 35
    SDPX9B 2
    pROMX9 1
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 956(915 LUT, 41 ALU) / 23040 5%
Register 971 / 23682 5%
  --Register as Latch 0 / 23682 0%
  --Register as FF 971 / 23682 5%
BSRAM 38 / 56 68%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 115.334(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.330
Data Arrival Time 8.982
Data Required Time 10.311
From uut/u_xcorr/cnt_8_s1
To uut/u_xcorr/result_41_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 537 clk_ibuf/O
0.375 0.375 tNET RR 1 uut/u_xcorr/cnt_8_s1/CLK
0.757 0.382 tC2Q RR 12 uut/u_xcorr/cnt_8_s1/Q
1.132 0.375 tNET RR 1 uut/u_xcorr/n218_s2/I0
1.659 0.526 tINS RR 2 uut/u_xcorr/n218_s2/F
2.034 0.375 tNET RR 1 uut/u_xcorr/r_42_s6/I0
2.560 0.526 tINS RR 44 uut/u_xcorr/r_42_s6/F
2.935 0.375 tNET RR 1 uut/u_xcorr/r_5_s3/I0
3.461 0.526 tINS RR 1 uut/u_xcorr/r_5_s3/F
3.836 0.375 tNET RR 86 uut/u_xcorr/m1/n4_s0/C[5]
7.730 3.894 tINS RF 1 uut/u_xcorr/m1/n4_s0/DOUT[41]
8.080 0.350 tNET FF 1 uut/u_xcorr/n871_s2/I0
8.607 0.526 tINS FR 1 uut/u_xcorr/n871_s2/F
8.982 0.375 tNET RR 1 uut/u_xcorr/result_41_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 537 clk_ibuf/O
10.375 0.375 tNET RR 1 uut/u_xcorr/result_41_s0/CLK
10.311 -0.064 tSu 1 uut/u_xcorr/result_41_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.999, 69.704%; route: 2.225, 25.852%; tC2Q: 0.382, 4.444%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 1.331
Data Arrival Time 8.981
Data Required Time 10.311
From uut/u_xcorr/cnt_8_s1
To uut/u_xcorr/result_42_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 537 clk_ibuf/O
0.375 0.375 tNET RR 1 uut/u_xcorr/cnt_8_s1/CLK
0.757 0.382 tC2Q RR 12 uut/u_xcorr/cnt_8_s1/Q
1.132 0.375 tNET RR 1 uut/u_xcorr/n218_s2/I0
1.659 0.526 tINS RR 2 uut/u_xcorr/n218_s2/F
2.034 0.375 tNET RR 1 uut/u_xcorr/r_42_s6/I0
2.560 0.526 tINS RR 44 uut/u_xcorr/r_42_s6/F
2.935 0.375 tNET RR 1 uut/u_xcorr/r_5_s3/I0
3.461 0.526 tINS RR 1 uut/u_xcorr/r_5_s3/F
3.836 0.375 tNET RR 86 uut/u_xcorr/m1/n4_s0/C[5]
7.729 3.893 tINS RF 1 uut/u_xcorr/m1/n4_s0/DOUT[42]
8.079 0.350 tNET FF 1 uut/u_xcorr/n870_s2/I0
8.606 0.526 tINS FR 1 uut/u_xcorr/n870_s2/F
8.981 0.375 tNET RR 1 uut/u_xcorr/result_42_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 537 clk_ibuf/O
10.375 0.375 tNET RR 1 uut/u_xcorr/result_42_s0/CLK
10.311 -0.064 tSu 1 uut/u_xcorr/result_42_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.998, 69.700%; route: 2.225, 25.855%; tC2Q: 0.382, 4.445%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 1.354
Data Arrival Time 8.957
Data Required Time 10.311
From uut/u_xcorr/cnt_8_s1
To uut/u_xcorr/result_36_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 537 clk_ibuf/O
0.375 0.375 tNET RR 1 uut/u_xcorr/cnt_8_s1/CLK
0.757 0.382 tC2Q RR 12 uut/u_xcorr/cnt_8_s1/Q
1.132 0.375 tNET RR 1 uut/u_xcorr/n218_s2/I0
1.659 0.526 tINS RR 2 uut/u_xcorr/n218_s2/F
2.034 0.375 tNET RR 1 uut/u_xcorr/r_42_s6/I0
2.560 0.526 tINS RR 44 uut/u_xcorr/r_42_s6/F
2.935 0.375 tNET RR 1 uut/u_xcorr/r_5_s3/I0
3.461 0.526 tINS RR 1 uut/u_xcorr/r_5_s3/F
3.836 0.375 tNET RR 86 uut/u_xcorr/m1/n4_s0/C[5]
7.706 3.870 tINS RF 1 uut/u_xcorr/m1/n4_s0/DOUT[36]
8.056 0.350 tNET FF 1 uut/u_xcorr/n876_s2/I0
8.582 0.526 tINS FR 1 uut/u_xcorr/n876_s2/F
8.957 0.375 tNET RR 1 uut/u_xcorr/result_36_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 537 clk_ibuf/O
10.375 0.375 tNET RR 1 uut/u_xcorr/result_36_s0/CLK
10.311 -0.064 tSu 1 uut/u_xcorr/result_36_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.975, 69.617%; route: 2.225, 25.926%; tC2Q: 0.382, 4.457%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 1.364
Data Arrival Time 8.947
Data Required Time 10.311
From uut/u_xcorr/cnt_8_s1
To uut/u_xcorr/result_40_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 537 clk_ibuf/O
0.375 0.375 tNET RR 1 uut/u_xcorr/cnt_8_s1/CLK
0.757 0.382 tC2Q RR 12 uut/u_xcorr/cnt_8_s1/Q
1.132 0.375 tNET RR 1 uut/u_xcorr/n218_s2/I0
1.659 0.526 tINS RR 2 uut/u_xcorr/n218_s2/F
2.034 0.375 tNET RR 1 uut/u_xcorr/r_42_s6/I0
2.560 0.526 tINS RR 44 uut/u_xcorr/r_42_s6/F
2.935 0.375 tNET RR 1 uut/u_xcorr/r_5_s3/I0
3.461 0.526 tINS RR 1 uut/u_xcorr/r_5_s3/F
3.836 0.375 tNET RR 86 uut/u_xcorr/m1/n4_s0/C[5]
7.696 3.860 tINS RF 1 uut/u_xcorr/m1/n4_s0/DOUT[40]
8.046 0.350 tNET FF 1 uut/u_xcorr/n872_s2/I0
8.572 0.526 tINS FR 1 uut/u_xcorr/n872_s2/F
8.947 0.375 tNET RR 1 uut/u_xcorr/result_40_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 537 clk_ibuf/O
10.375 0.375 tNET RR 1 uut/u_xcorr/result_40_s0/CLK
10.311 -0.064 tSu 1 uut/u_xcorr/result_40_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.965, 69.582%; route: 2.225, 25.956%; tC2Q: 0.382, 4.462%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 1.393
Data Arrival Time 8.918
Data Required Time 10.311
From uut/u_xcorr/cnt_8_s1
To uut/u_xcorr/result_39_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 537 clk_ibuf/O
0.375 0.375 tNET RR 1 uut/u_xcorr/cnt_8_s1/CLK
0.757 0.382 tC2Q RR 12 uut/u_xcorr/cnt_8_s1/Q
1.132 0.375 tNET RR 1 uut/u_xcorr/n218_s2/I0
1.659 0.526 tINS RR 2 uut/u_xcorr/n218_s2/F
2.034 0.375 tNET RR 1 uut/u_xcorr/r_42_s6/I0
2.560 0.526 tINS RR 44 uut/u_xcorr/r_42_s6/F
2.935 0.375 tNET RR 1 uut/u_xcorr/r_5_s3/I0
3.461 0.526 tINS RR 1 uut/u_xcorr/r_5_s3/F
3.836 0.375 tNET RR 86 uut/u_xcorr/m1/n4_s0/C[5]
7.667 3.831 tINS RF 1 uut/u_xcorr/m1/n4_s0/DOUT[39]
8.017 0.350 tNET FF 1 uut/u_xcorr/n873_s2/I0
8.543 0.526 tINS FR 1 uut/u_xcorr/n873_s2/F
8.918 0.375 tNET RR 1 uut/u_xcorr/result_39_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 537 clk_ibuf/O
10.375 0.375 tNET RR 1 uut/u_xcorr/result_39_s0/CLK
10.311 -0.064 tSu 1 uut/u_xcorr/result_39_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.936, 69.479%; route: 2.225, 26.044%; tC2Q: 0.382, 4.477%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%