Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_XCORR_RefDesign\XCORR_17_512_13_case\project\impl\gwsynthesis\XCORR.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_XCORR_RefDesign\XCORR_17_512_13_case\project\src\XCORR.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_XCORR_RefDesign\XCORR_17_512_13_case\project\src\XCORR.sdc
Tool Version	V1.9.11.02 (64-bit)
Part Number	GW5A-LV25UG324ES
Device	GW5A-25
Device Version	A
Created Time	Tue Jun 10 13:56:03 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C ES
Hold Delay Model	Fast 0.945V 85C ES
Numbers of Paths Analyzed	3143
Numbers of Endpoints Analyzed	4437
Numbers of Falling Endpoints	10
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk	Base	10.000	100.000	0.000	5.000			clk
2	tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	113.943(MHz)	4	TOP
2	tck_pad_i	20.000(MHz)	95.023(MHz)	6	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.224	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_36_s0/D	clk:[R]	clk:[R]	10.000	-0.001	8.713
2	1.332	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_35_s0/D	clk:[R]	clk:[R]	10.000	0.018	8.586
3	1.435	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_41_s0/D	clk:[R]	clk:[R]	10.000	0.000	8.500
4	1.449	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_33_s0/D	clk:[R]	clk:[R]	10.000	0.008	8.479
5	1.534	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_40_s0/D	clk:[R]	clk:[R]	10.000	-0.038	8.441
6	1.550	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_32_s0/D	clk:[R]	clk:[R]	10.000	0.008	8.378
7	1.553	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_37_s0/D	clk:[R]	clk:[R]	10.000	-0.001	8.384
8	1.563	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_34_s0/D	clk:[R]	clk:[R]	10.000	0.018	8.355
9	1.633	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_38_s0/D	clk:[R]	clk:[R]	10.000	-0.001	8.304
10	1.635	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_27_s0/D	clk:[R]	clk:[R]	10.000	0.008	8.293
11	1.644	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_42_s0/D	clk:[R]	clk:[R]	10.000	-0.034	8.326
12	1.670	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_30_s0/D	clk:[R]	clk:[R]	10.000	0.008	8.258
13	1.674	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_24_s0/D	clk:[R]	clk:[R]	10.000	0.008	8.254
14	1.722	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_28_s0/D	clk:[R]	clk:[R]	10.000	-0.001	8.215
15	1.747	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_39_s0/D	clk:[R]	clk:[R]	10.000	-0.007	8.197
16	1.831	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_26_s0/D	clk:[R]	clk:[R]	10.000	0.008	8.097
17	1.836	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_31_s0/D	clk:[R]	clk:[R]	10.000	0.018	8.083
18	1.897	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_29_s0/D	clk:[R]	clk:[R]	10.000	-0.001	8.040
19	1.994	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_25_s0/D	clk:[R]	clk:[R]	10.000	0.018	7.924
20	2.193	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_22_s0/D	clk:[R]	clk:[R]	10.000	-0.001	7.750
21	2.202	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_21_s0/D	clk:[R]	clk:[R]	10.000	-0.053	7.787
22	2.260	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_20_s0/D	clk:[R]	clk:[R]	10.000	-0.053	7.729
23	2.319	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_19_s0/D	clk:[R]	clk:[R]	10.000	-0.053	7.670
24	2.347	gw_gao_inst_0/u_la0_top/internal_reg_start_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D	tck_pad_i:[F]	clk:[R]	5.000	1.422	1.133
25	2.403	uut/u_xcorr/memx_memx_0_0_s/DO[3]	uut/u_xcorr/result_23_s0/D	clk:[R]	clk:[R]	10.000	-0.017	7.550

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.193	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[2]	clk:[R]	clk:[R]	0.000	-0.005	0.235
2	0.230	gw_gao_inst_0/u_la0_top/address_counter_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s/ADB[5]	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.024	0.241
3	0.249	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[1]	clk:[R]	clk:[R]	0.000	0.002	0.284
4	0.249	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1]	clk:[R]	clk:[R]	0.000	0.002	0.284
5	0.249	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[0]	clk:[R]	clk:[R]	0.000	0.002	0.284
6	0.252	ad_1_s0/Q	b_d_0_s2/AD[6]	clk:[R]	clk:[R]	0.000	0.000	0.286
7	0.269	ad_3_s0/Q	b_d_0_s2/AD[8]	clk:[R]	clk:[R]	0.000	0.002	0.302
8	0.271	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/DI[0]	clk:[R]	clk:[R]	0.000	-0.002	0.310
9	0.275	gw_gao_inst_0/u_la0_top/bit_count_5_s1/Q	gw_gao_inst_0/u_la0_top/bit_count_5_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
10	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
11	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
12	0.275	gw_gao_inst_0/u_la0_top/bit_count_6_s1/Q	gw_gao_inst_0/u_la0_top/bit_count_6_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
13	0.278	gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_4_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.303
14	0.278	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.303
15	0.278	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.303
16	0.278	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.303
17	0.278	start_s0/Q	start_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.303
18	0.278	gw_gao_inst_0/u_la0_top/word_count_0_s0/Q	gw_gao_inst_0/u_la0_top/word_count_0_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.303
19	0.278	gw_gao_inst_0/u_la0_top/word_count_4_s0/Q	gw_gao_inst_0/u_la0_top/word_count_4_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.303
20	0.278	gw_gao_inst_0/u_la0_top/address_counter_0_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_0_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.303
21	0.281	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.306
22	0.281	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.306
23	0.281	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.306
24	0.288	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_66_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_16_s/DI[2]	clk:[R]	clk:[R]	0.000	0.002	0.323
25	0.290	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_62_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/DI[2]	clk:[R]	clk:[R]	0.000	0.000	0.326

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	3.037	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.028	1.644
2	3.302	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.005	1.355
3	3.415	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.043	1.281
4	3.415	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.043	1.281
5	3.415	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.043	1.281
6	3.415	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.043	1.281
7	3.415	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.043	1.281
8	3.415	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.043	1.281
9	3.415	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.043	1.281
10	3.442	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.009	1.220
11	3.451	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.019	1.220
12	3.451	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.019	1.220
13	3.493	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.003	1.162
14	3.493	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.003	1.162
15	3.503	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	5.000	-0.013	1.162
16	3.503	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.013	1.162
17	3.503	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.013	1.162
18	3.504	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.014	1.162
19	3.504	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.014	1.162
20	3.504	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.014	1.162
21	3.504	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.014	1.162
22	3.513	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.023	1.162
23	3.513	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.023	1.162
24	3.513	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.023	1.162
25	3.513	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.023	1.162

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.365	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	-0.004	0.316
2	5.365	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	-0.004	0.316
3	5.365	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.004	0.316
4	5.365	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.004	0.316
5	5.412	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.007	0.366
6	5.412	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.007	0.366
7	5.418	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.003	0.368
8	5.418	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.003	0.368
9	5.418	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	-5.000	-0.003	0.368
10	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.004	0.422
11	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.004	0.422
12	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.004	0.422
13	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.004	0.422
14	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.004	0.422
15	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.004	0.422
16	5.475	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.000	0.422
17	5.475	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.000	0.422
18	5.475	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.000	0.422
19	5.475	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.000	0.422
20	5.518	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.003	0.468
21	5.518	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.003	0.468
22	5.548	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.010	0.505
23	5.548	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.010	0.505
24	5.552	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.006	0.505
25	5.552	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.006	0.505

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.747	3.747	1.000	Low Pulse Width	clk	b_d_0_s2
2	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
3	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
4	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s
5	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s
6	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_27_s
7	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_28_s
8	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s
9	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s
10	2.751	3.751	1.000	Low Pulse Width	clk	uut/u_xcorr/memy_memy_0_0_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.224
Data Arrival Time	11.318
Data Required Time	12.542
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_36_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
10.236	3.673	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[36]
10.792	0.556	tNET	FF	1	R13C53[2][B]	uut/u_xcorr/n876_s2/I0
11.318	0.526	tINS	FR	1	R13C53[2][B]	uut/u_xcorr/n876_s2/F
11.318	0.000	tNET	RR	1	R13C53[2][B]	uut/u_xcorr/result_36_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C53[2][B]	uut/u_xcorr/result_36_s0/CLK
12.542	-0.064	tSu		1	R13C53[2][B]	uut/u_xcorr/result_36_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.716, 54.123%; route: 1.987, 22.809%; tC2Q: 2.010, 23.068%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path2

Path Summary:

Slack	1.332
Data Arrival Time	11.191
Data Required Time	12.523
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_35_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
10.108	3.546	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[35]
10.664	0.556	tNET	FF	1	R13C55[1][A]	uut/u_xcorr/n877_s2/I0
11.191	0.526	tINS	FR	1	R13C55[1][A]	uut/u_xcorr/n877_s2/F
11.191	0.000	tNET	RR	1	R13C55[1][A]	uut/u_xcorr/result_35_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.587	1.904	tNET	RR	1	R13C55[1][A]	uut/u_xcorr/result_35_s0/CLK
12.523	-0.064	tSu		1	R13C55[1][A]	uut/u_xcorr/result_35_s0

Path Statistics:

Clock Skew	-0.018
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.589, 53.442%; route: 1.987, 23.148%; tC2Q: 2.010, 23.410%
Required Clock Path Delay	cell: 0.683, 26.383%; route: 1.904, 73.617%

Path3

Path Summary:

Slack	1.435
Data Arrival Time	11.105
Data Required Time	12.541
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_41_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
10.258	3.695	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[41]
10.584	0.326	tNET	FF	1	R18C55[3][A]	uut/u_xcorr/n871_s2/I0
11.105	0.521	tINS	FR	1	R18C55[3][A]	uut/u_xcorr/n871_s2/F
11.105	0.000	tNET	RR	1	R18C55[3][A]	uut/u_xcorr/result_41_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.604	1.922	tNET	RR	1	R18C55[3][A]	uut/u_xcorr/result_41_s0/CLK
12.541	-0.064	tSu		1	R18C55[3][A]	uut/u_xcorr/result_41_s0

Path Statistics:

Clock Skew	-0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.733, 55.679%; route: 1.757, 20.675%; tC2Q: 2.010, 23.646%
Required Clock Path Delay	cell: 0.683, 26.206%; route: 1.922, 73.794%

Path4

Path Summary:

Slack	1.449
Data Arrival Time	11.083
Data Required Time	12.533
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_33_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
10.001	3.439	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[33]
10.557	0.556	tNET	FF	1	R13C54[1][B]	uut/u_xcorr/n879_s2/I0
11.083	0.526	tINS	FR	1	R13C54[1][B]	uut/u_xcorr/n879_s2/F
11.083	0.000	tNET	RR	1	R13C54[1][B]	uut/u_xcorr/result_33_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.596	1.914	tNET	RR	1	R13C54[1][B]	uut/u_xcorr/result_33_s0/CLK
12.533	-0.064	tSu		1	R13C54[1][B]	uut/u_xcorr/result_33_s0

Path Statistics:

Clock Skew	-0.008
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.481, 52.851%; route: 1.987, 23.442%; tC2Q: 2.010, 23.707%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path5

Path Summary:

Slack	1.534
Data Arrival Time	11.046
Data Required Time	12.579
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_40_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
10.171	3.608	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[40]
10.529	0.359	tNET	RR	1	R22C54[0][B]	uut/u_xcorr/n872_s2/I0
11.046	0.516	tINS	RR	1	R22C54[0][B]	uut/u_xcorr/n872_s2/F
11.046	0.000	tNET	RR	1	R22C54[0][B]	uut/u_xcorr/result_40_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.643	1.961	tNET	RR	1	R22C54[0][B]	uut/u_xcorr/result_40_s0/CLK
12.579	-0.064	tSu		1	R22C54[0][B]	uut/u_xcorr/result_40_s0

Path Statistics:

Clock Skew	0.038
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.641, 54.981%; route: 1.790, 21.206%; tC2Q: 2.010, 23.813%
Required Clock Path Delay	cell: 0.683, 25.822%; route: 1.961, 74.178%

Path6

Path Summary:

Slack	1.550
Data Arrival Time	10.982
Data Required Time	12.533
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_32_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.990	3.428	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[32]
10.456	0.466	tNET	FF	1	R13C54[1][A]	uut/u_xcorr/n880_s2/I0
10.982	0.526	tINS	FR	1	R13C54[1][A]	uut/u_xcorr/n880_s2/F
10.982	0.000	tNET	RR	1	R13C54[1][A]	uut/u_xcorr/result_32_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.596	1.914	tNET	RR	1	R13C54[1][A]	uut/u_xcorr/result_32_s0/CLK
12.533	-0.064	tSu		1	R13C54[1][A]	uut/u_xcorr/result_32_s0

Path Statistics:

Clock Skew	-0.008
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.470, 53.359%; route: 1.897, 22.649%; tC2Q: 2.010, 23.992%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path7

Path Summary:

Slack	1.553
Data Arrival Time	10.989
Data Required Time	12.542
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_37_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
10.123	3.560	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[37]
10.726	0.604	tNET	FF	1	R13C53[1][B]	uut/u_xcorr/n875_s2/I0
10.989	0.262	tINS	FR	1	R13C53[1][B]	uut/u_xcorr/n875_s2/F
10.989	0.000	tNET	RR	1	R13C53[1][B]	uut/u_xcorr/result_37_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C53[1][B]	uut/u_xcorr/result_37_s0/CLK
12.542	-0.064	tSu		1	R13C53[1][B]	uut/u_xcorr/result_37_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.339, 51.755%; route: 2.035, 24.272%; tC2Q: 2.010, 23.974%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path8

Path Summary:

Slack	1.563
Data Arrival Time	10.960
Data Required Time	12.523
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_34_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
10.032	3.470	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[34]
10.499	0.466	tNET	FF	1	R13C55[0][B]	uut/u_xcorr/n878_s2/I0
10.960	0.461	tINS	FR	1	R13C55[0][B]	uut/u_xcorr/n878_s2/F
10.960	0.000	tNET	RR	1	R13C55[0][B]	uut/u_xcorr/result_34_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.587	1.904	tNET	RR	1	R13C55[0][B]	uut/u_xcorr/result_34_s0/CLK
12.523	-0.064	tSu		1	R13C55[0][B]	uut/u_xcorr/result_34_s0

Path Statistics:

Clock Skew	-0.018
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.448, 53.232%; route: 1.897, 22.711%; tC2Q: 2.010, 24.057%
Required Clock Path Delay	cell: 0.683, 26.383%; route: 1.904, 73.617%

Path9

Path Summary:

Slack	1.633
Data Arrival Time	10.909
Data Required Time	12.542
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_38_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
10.180	3.618	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[38]
10.646	0.466	tNET	FF	1	R13C53[2][A]	uut/u_xcorr/n874_s2/I0
10.909	0.262	tINS	FR	1	R13C53[2][A]	uut/u_xcorr/n874_s2/F
10.909	0.000	tNET	RR	1	R13C53[2][A]	uut/u_xcorr/result_38_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C53[2][A]	uut/u_xcorr/result_38_s0/CLK
12.542	-0.064	tSu		1	R13C53[2][A]	uut/u_xcorr/result_38_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.397, 52.946%; route: 1.897, 22.850%; tC2Q: 2.010, 24.204%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path10

Path Summary:

Slack	1.635
Data Arrival Time	10.898
Data Required Time	12.533
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_27_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.833	3.270	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[27]
10.436	0.604	tNET	FF	1	R13C54[0][A]	uut/u_xcorr/n885_s2/I0
10.898	0.461	tINS	FR	1	R13C54[0][A]	uut/u_xcorr/n885_s2/F
10.898	0.000	tNET	RR	1	R13C54[0][A]	uut/u_xcorr/result_27_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.596	1.914	tNET	RR	1	R13C54[0][A]	uut/u_xcorr/result_27_s0/CLK
12.533	-0.064	tSu		1	R13C54[0][A]	uut/u_xcorr/result_27_s0

Path Statistics:

Clock Skew	-0.008
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.248, 51.224%; route: 2.035, 24.539%; tC2Q: 2.010, 24.237%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path11

Path Summary:

Slack	1.644
Data Arrival Time	10.931
Data Required Time	12.575
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_42_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
10.232	3.670	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[42]
10.469	0.237	tNET	RR	1	R20C55[1][B]	uut/u_xcorr/n870_s2/I0
10.931	0.461	tINS	RR	1	R20C55[1][B]	uut/u_xcorr/n870_s2/F
10.931	0.000	tNET	RR	1	R20C55[1][B]	uut/u_xcorr/result_42_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.639	1.956	tNET	RR	1	R20C55[1][B]	uut/u_xcorr/result_42_s0/CLK
12.575	-0.064	tSu		1	R20C55[1][B]	uut/u_xcorr/result_42_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.647, 55.816%; route: 1.669, 20.043%; tC2Q: 2.010, 24.141%
Required Clock Path Delay	cell: 0.683, 25.865%; route: 1.956, 74.135%

Path12

Path Summary:

Slack	1.670
Data Arrival Time	10.862
Data Required Time	12.533
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_30_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.921	3.359	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[30]
10.336	0.415	tNET	RR	1	R13C54[2][B]	uut/u_xcorr/n882_s2/I0
10.862	0.526	tINS	RR	1	R13C54[2][B]	uut/u_xcorr/n882_s2/F
10.862	0.000	tNET	RR	1	R13C54[2][B]	uut/u_xcorr/result_30_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.596	1.914	tNET	RR	1	R13C54[2][B]	uut/u_xcorr/result_30_s0/CLK
12.533	-0.064	tSu		1	R13C54[2][B]	uut/u_xcorr/result_30_s0

Path Statistics:

Clock Skew	-0.008
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.401, 53.301%; route: 1.846, 22.358%; tC2Q: 2.010, 24.341%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path13

Path Summary:

Slack	1.674
Data Arrival Time	10.858
Data Required Time	12.533
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_24_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.917	3.355	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[24]
10.332	0.415	tNET	RR	1	R13C54[2][A]	uut/u_xcorr/n888_s2/I0
10.858	0.526	tINS	RR	1	R13C54[2][A]	uut/u_xcorr/n888_s2/F
10.858	0.000	tNET	RR	1	R13C54[2][A]	uut/u_xcorr/result_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.596	1.914	tNET	RR	1	R13C54[2][A]	uut/u_xcorr/result_24_s0/CLK
12.533	-0.064	tSu		1	R13C54[2][A]	uut/u_xcorr/result_24_s0

Path Statistics:

Clock Skew	-0.008
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.397, 53.279%; route: 1.846, 22.369%; tC2Q: 2.010, 24.353%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path14

Path Summary:

Slack	1.722
Data Arrival Time	10.820
Data Required Time	12.542
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_28_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.902	3.340	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[28]
10.557	0.655	tNET	RR	1	R13C53[0][B]	uut/u_xcorr/n884_s2/I0
10.820	0.262	tINS	RR	1	R13C53[0][B]	uut/u_xcorr/n884_s2/F
10.820	0.000	tNET	RR	1	R13C53[0][B]	uut/u_xcorr/result_28_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C53[0][B]	uut/u_xcorr/result_28_s0/CLK
12.542	-0.064	tSu		1	R13C53[0][B]	uut/u_xcorr/result_28_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.119, 50.139%; route: 2.086, 25.395%; tC2Q: 2.010, 24.467%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path15

Path Summary:

Slack	1.747
Data Arrival Time	10.802
Data Required Time	12.548
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_39_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
10.198	3.636	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[39]
10.387	0.189	tNET	FF	1	R17C54[3][A]	uut/u_xcorr/n873_s2/I0
10.802	0.415	tINS	FR	1	R17C54[3][A]	uut/u_xcorr/n873_s2/F
10.802	0.000	tNET	RR	1	R17C54[3][A]	uut/u_xcorr/result_39_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.612	1.929	tNET	RR	1	R17C54[3][A]	uut/u_xcorr/result_39_s0/CLK
12.548	-0.064	tSu		1	R17C54[3][A]	uut/u_xcorr/result_39_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.567, 55.715%; route: 1.620, 19.764%; tC2Q: 2.010, 24.522%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path16

Path Summary:

Slack	1.831
Data Arrival Time	10.701
Data Required Time	12.533
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_26_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.819	3.257	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[26]
10.240	0.421	tNET	FF	1	R13C54[0][B]	uut/u_xcorr/n886_s2/I0
10.701	0.461	tINS	FR	1	R13C54[0][B]	uut/u_xcorr/n886_s2/F
10.701	0.000	tNET	RR	1	R13C54[0][B]	uut/u_xcorr/result_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.596	1.914	tNET	RR	1	R13C54[0][B]	uut/u_xcorr/result_26_s0/CLK
12.533	-0.064	tSu		1	R13C54[0][B]	uut/u_xcorr/result_26_s0

Path Statistics:

Clock Skew	-0.008
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.234, 52.295%; route: 1.852, 22.880%; tC2Q: 2.010, 24.825%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path17

Path Summary:

Slack	1.836
Data Arrival Time	10.687
Data Required Time	12.523
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_31_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.959	3.396	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[31]
10.425	0.466	tNET	FF	1	R13C55[0][A]	uut/u_xcorr/n881_s2/I0
10.687	0.262	tINS	FR	1	R13C55[0][A]	uut/u_xcorr/n881_s2/F
10.687	0.000	tNET	RR	1	R13C55[0][A]	uut/u_xcorr/result_31_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.587	1.904	tNET	RR	1	R13C55[0][A]	uut/u_xcorr/result_31_s0/CLK
12.523	-0.064	tSu		1	R13C55[0][A]	uut/u_xcorr/result_31_s0

Path Statistics:

Clock Skew	-0.018
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.175, 51.656%; route: 1.897, 23.476%; tC2Q: 2.010, 24.868%
Required Clock Path Delay	cell: 0.683, 26.383%; route: 1.904, 73.617%

Path18

Path Summary:

Slack	1.897
Data Arrival Time	10.644
Data Required Time	12.542
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_29_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.961	3.399	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[29]
10.382	0.421	tNET	FF	1	R13C53[1][A]	uut/u_xcorr/n883_s2/I0
10.644	0.262	tINS	FR	1	R13C53[1][A]	uut/u_xcorr/n883_s2/F
10.644	0.000	tNET	RR	1	R13C53[1][A]	uut/u_xcorr/result_29_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C53[1][A]	uut/u_xcorr/result_29_s0/CLK
12.542	-0.064	tSu		1	R13C53[1][A]	uut/u_xcorr/result_29_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.177, 51.958%; route: 1.852, 23.042%; tC2Q: 2.010, 25.001%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path19

Path Summary:

Slack	1.994
Data Arrival Time	10.529
Data Required Time	12.523
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_25_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.800	3.238	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[25]
10.267	0.466	tNET	FF	1	R13C55[1][B]	uut/u_xcorr/n887_s2/I0
10.529	0.262	tINS	FR	1	R13C55[1][B]	uut/u_xcorr/n887_s2/F
10.529	0.000	tNET	RR	1	R13C55[1][B]	uut/u_xcorr/result_25_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.587	1.904	tNET	RR	1	R13C55[1][B]	uut/u_xcorr/result_25_s0/CLK
12.523	-0.064	tSu		1	R13C55[1][B]	uut/u_xcorr/result_25_s0

Path Statistics:

Clock Skew	-0.018
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.017, 50.690%; route: 1.897, 23.945%; tC2Q: 2.010, 25.365%
Required Clock Path Delay	cell: 0.683, 26.383%; route: 1.904, 73.617%

Path20

Path Summary:

Slack	2.193
Data Arrival Time	10.355
Data Required Time	12.548
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.600	3.038	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[22]
10.065	0.465	tNET	RR	1	R13C53[3][A]	uut/u_xcorr/n890_s2/I0
10.355	0.290	tINS	RF	1	R13C53[3][A]	uut/u_xcorr/n890_s2/F
10.355	0.000	tNET	FF	1	R13C53[3][A]	uut/u_xcorr/result_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C53[3][A]	uut/u_xcorr/result_22_s0/CLK
12.548	-0.058	tSu		1	R13C53[3][A]	uut/u_xcorr/result_22_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 3.844, 49.597%; route: 1.896, 24.468%; tC2Q: 2.010, 25.935%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path21

Path Summary:

Slack	2.202
Data Arrival Time	10.392
Data Required Time	12.594
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.628	3.066	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[21]
9.866	0.237	tNET	RR	1	R20C53[2][A]	uut/u_xcorr/n891_s2/I0
10.392	0.526	tINS	RR	1	R20C53[2][A]	uut/u_xcorr/n891_s2/F
10.392	0.000	tNET	RR	1	R20C53[2][A]	uut/u_xcorr/result_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.658	1.975	tNET	RR	1	R20C53[2][A]	uut/u_xcorr/result_21_s0/CLK
12.594	-0.064	tSu		1	R20C53[2][A]	uut/u_xcorr/result_21_s0

Path Statistics:

Clock Skew	0.053
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.109, 52.760%; route: 1.669, 21.429%; tC2Q: 2.010, 25.811%
Required Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%

Path22

Path Summary:

Slack	2.260
Data Arrival Time	10.334
Data Required Time	12.594
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.570	3.008	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[20]
9.808	0.237	tNET	RR	1	R20C53[1][B]	uut/u_xcorr/n892_s2/I0
10.334	0.526	tINS	RR	1	R20C53[1][B]	uut/u_xcorr/n892_s2/F
10.334	0.000	tNET	RR	1	R20C53[1][B]	uut/u_xcorr/result_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.658	1.975	tNET	RR	1	R20C53[1][B]	uut/u_xcorr/result_20_s0/CLK
12.594	-0.064	tSu		1	R20C53[1][B]	uut/u_xcorr/result_20_s0

Path Statistics:

Clock Skew	0.053
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 4.050, 52.404%; route: 1.669, 21.590%; tC2Q: 2.010, 26.006%
Required Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%

Path23

Path Summary:

Slack	2.319
Data Arrival Time	10.275
Data Required Time	12.594
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.521	2.959	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[19]
9.759	0.237	tNET	RR	1	R20C53[1][A]	uut/u_xcorr/n893_s2/I0
10.275	0.516	tINS	RR	1	R20C53[1][A]	uut/u_xcorr/n893_s2/F
10.275	0.000	tNET	RR	1	R20C53[1][A]	uut/u_xcorr/result_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.658	1.975	tNET	RR	1	R20C53[1][A]	uut/u_xcorr/result_19_s0/CLK
12.594	-0.064	tSu		1	R20C53[1][A]	uut/u_xcorr/result_19_s0

Path Statistics:

Clock Skew	0.053
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 3.991, 52.038%; route: 1.669, 21.756%; tC2Q: 2.010, 26.205%
Required Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%

Path24

Path Summary:

Slack	2.347
Data Arrival Time	30.161
Data Required Time	32.508
From	gw_gao_inst_0/u_la0_top/internal_reg_start_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
25.688	0.688	tINS	FF	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
25.688	0.000	tNET	FF	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375	0.688	tINS	FF	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
29.029	2.654	tNET	FF	1	R11C50[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CLK
29.462	0.434	tC2Q	FR	2	R11C50[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s1/Q
30.161	0.699	tNET	RR	1	R11C40[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					clk
30.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
30.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
32.607	1.924	tNET	RR	1	R11C40[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
32.572	-0.035	tUnc				gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
32.508	-0.064	tSu		1	R11C40[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-1.422
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.375, 34.130%; route: 2.654, 65.870%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.699, 61.700%; tC2Q: 0.434, 38.300%
Required Clock Path Delay	cell: 0.683, 26.181%; route: 1.924, 73.819%

Path25

Path Summary:

Slack	2.403
Data Arrival Time	10.155
Data Required Time	12.557
From	uut/u_xcorr/memx_memx_0_0_s
To	uut/u_xcorr/result_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
2.605	1.922	tNET	RR	18	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/CLKB
4.615	2.010	tC2Q	RR	1	BSRAM_R28[15]	uut/u_xcorr/memx_memx_0_0_s/DO[3]
5.342	0.728	tNET	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/I0
5.858	0.516	tINS	RR	1	R25C53[1][A]	uut/u_xcorr/x_1_3_s8/F
6.562	0.704	tNET	RR	94	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/A[3]
9.703	3.141	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[23]
9.892	0.189	tNET	FF	1	R17C53[2][A]	uut/u_xcorr/n889_s2/I0
10.155	0.262	tINS	FR	1	R17C53[2][A]	uut/u_xcorr/n889_s2/F
10.155	0.000	tNET	RR	1	R17C53[2][A]	uut/u_xcorr/result_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.621	1.939	tNET	RR	1	R17C53[2][A]	uut/u_xcorr/result_23_s0/CLK
12.557	-0.064	tSu		1	R17C53[2][A]	uut/u_xcorr/result_23_s0

Path Statistics:

Clock Skew	0.017
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.203%; route: 1.922, 73.797%
Arrival Data Path Delay	cell: 3.920, 51.919%; route: 1.620, 21.457%; tC2Q: 2.010, 26.623%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.193
Data Arrival Time	1.609
Data Required Time	1.415
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/CLK
1.515	0.141	tC2Q	RF	1	R11C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q
1.609	0.094	tNET	FF	1	BSRAM_R10[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R10[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
1.415	0.037	tHld		1	BSRAM_R10[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path2

Path Summary:

Slack	0.230
Data Arrival Time	2.682
Data Required Time	2.452
From	gw_gao_inst_0/u_la0_top/address_counter_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.441	1.090	tNET	RR	1	R20C48[2][A]	gw_gao_inst_0/u_la0_top/address_counter_3_s0/CLK
2.582	0.141	tC2Q	RF	37	R20C48[2][A]	gw_gao_inst_0/u_la0_top/address_counter_3_s0/Q
2.682	0.100	tNET	FF	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s/ADB[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.417	1.066	tNET	RR	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s/CLKB
2.452	0.035	tHld		1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s

Path Statistics:

Clock Skew	-0.024
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 55.352%; route: 1.090, 44.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.100, 41.494%; tC2Q: 0.141, 58.506%
Required Clock Path Delay	cell: 1.351, 55.896%; route: 1.066, 44.104%

Path3

Path Summary:

Slack	0.249
Data Arrival Time	1.660
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.376	0.701	tNET	RR	1	R18C26[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/CLK
1.520	0.144	tC2Q	RR	1	R18C26[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/Q
1.660	0.140	tNET	RR	1	BSRAM_R28[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA
1.411	0.037	tHld		1	BSRAM_R28[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.083%; route: 0.701, 50.917%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.140, 49.296%; tC2Q: 0.144, 50.704%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path4

Path Summary:

Slack	0.249
Data Arrival Time	1.656
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R18C23[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/CLK
1.516	0.144	tC2Q	RR	1	R18C23[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q
1.656	0.140	tNET	RR	1	BSRAM_R28[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.408	0.037	tHld		1	BSRAM_R28[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.226%; route: 0.697, 50.774%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.140, 49.296%; tC2Q: 0.144, 50.704%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path5

Path Summary:

Slack	0.249
Data Arrival Time	1.656
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R18C23[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/CLK
1.516	0.144	tC2Q	RR	1	R18C23[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q
1.656	0.140	tNET	RR	1	BSRAM_R28[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.408	0.037	tHld		1	BSRAM_R28[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.226%; route: 0.697, 50.774%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.140, 49.296%; tC2Q: 0.144, 50.704%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path6

Path Summary:

Slack	0.252
Data Arrival Time	1.661
Data Required Time	1.410
From	ad_1_s0
To	b_d_0_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R17C56[0][B]	ad_1_s0/CLK
1.519	0.144	tC2Q	RR	7	R17C56[0][B]	ad_1_s0/Q
1.661	0.142	tNET	RR	1	BSRAM_R10[17]	b_d_0_s2/AD[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R10[17]	b_d_0_s2/CLK
1.410	0.035	tHld		1	BSRAM_R10[17]	b_d_0_s2

Path Statistics:

Clock Skew	-0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.127%; route: 0.700, 50.873%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.142, 49.650%; tC2Q: 0.144, 50.350%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path7

Path Summary:

Slack	0.269
Data Arrival Time	1.678
Data Required Time	1.410
From	ad_3_s0
To	b_d_0_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.376	0.701	tNET	RR	1	R18C56[2][B]	ad_3_s0/CLK
1.517	0.141	tC2Q	RF	5	R18C56[2][B]	ad_3_s0/Q
1.678	0.161	tNET	FF	1	BSRAM_R10[17]	b_d_0_s2/AD[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R10[17]	b_d_0_s2/CLK
1.410	0.035	tHld		1	BSRAM_R10[17]	b_d_0_s2

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.083%; route: 0.701, 50.917%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.161, 53.311%; tC2Q: 0.141, 46.689%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path8

Path Summary:

Slack	0.271
Data Arrival Time	1.683
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0/CLK
1.513	0.141	tC2Q	RF	1	R14C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0/Q
1.683	0.169	tNET	FF	1	BSRAM_R10[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R10[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/CLKA
1.411	0.037	tHld		1	BSRAM_R10[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.169, 54.516%; tC2Q: 0.141, 45.484%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path9

Path Summary:

Slack	0.275
Data Arrival Time	2.726
Data Required Time	2.451
From	gw_gao_inst_0/u_la0_top/bit_count_5_s1
To	gw_gao_inst_0/u_la0_top/bit_count_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.426	1.075	tNET	RR	1	R24C38[0][A]	gw_gao_inst_0/u_la0_top/bit_count_5_s1/CLK
2.567	0.141	tC2Q	RF	3	R24C38[0][A]	gw_gao_inst_0/u_la0_top/bit_count_5_s1/Q
2.573	0.006	tNET	FF	1	R24C38[0][A]	gw_gao_inst_0/u_la0_top/n990_s4/I0
2.726	0.153	tINS	FF	1	R24C38[0][A]	gw_gao_inst_0/u_la0_top/n990_s4/F
2.726	0.000	tNET	FF	1	R24C38[0][A]	gw_gao_inst_0/u_la0_top/bit_count_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.426	1.075	tNET	RR	1	R24C38[0][A]	gw_gao_inst_0/u_la0_top/bit_count_5_s1/CLK
2.451	0.025	tHld		1	R24C38[0][A]	gw_gao_inst_0/u_la0_top/bit_count_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.694%; route: 1.075, 44.306%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 55.694%; route: 1.075, 44.306%

Path10

Path Summary:

Slack	0.275
Data Arrival Time	1.673
Data Required Time	1.397
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.513	0.141	tC2Q	RF	40	R14C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
1.520	0.006	tNET	FF	1	R14C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n933_s1/I1
1.673	0.153	tINS	FF	1	R14C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n933_s1/F
1.673	0.000	tNET	FF	1	R14C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.397	0.025	tHld		1	R14C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path11

Path Summary:

Slack	0.275
Data Arrival Time	1.665
Data Required Time	1.390
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C48[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
1.506	0.141	tC2Q	RF	5	R13C48[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/Q
1.512	0.006	tNET	FF	1	R13C48[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n817_s0/I1
1.665	0.153	tINS	FF	1	R13C48[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n817_s0/F
1.665	0.000	tNET	FF	1	R13C48[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C48[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
1.390	0.025	tHld		1	R13C48[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path12

Path Summary:

Slack	0.275
Data Arrival Time	2.728
Data Required Time	2.453
From	gw_gao_inst_0/u_la0_top/bit_count_6_s1
To	gw_gao_inst_0/u_la0_top/bit_count_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.428	1.077	tNET	RR	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/bit_count_6_s1/CLK
2.569	0.141	tC2Q	RF	4	R25C37[0][A]	gw_gao_inst_0/u_la0_top/bit_count_6_s1/Q
2.575	0.006	tNET	FF	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/n989_s2/I0
2.728	0.153	tINS	FF	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/n989_s2/F
2.728	0.000	tNET	FF	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/bit_count_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.428	1.077	tNET	RR	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/bit_count_6_s1/CLK
2.453	0.025	tHld		1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/bit_count_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.643%; route: 1.077, 44.357%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 55.643%; route: 1.077, 44.357%

Path13

Path Summary:

Slack	0.278
Data Arrival Time	2.720
Data Required Time	2.443
From	gw_gao_inst_0/u_la0_top/address_counter_4_s0
To	gw_gao_inst_0/u_la0_top/address_counter_4_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.418	1.067	tNET	RR	1	R17C48[1][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK
2.559	0.141	tC2Q	RF	39	R17C48[1][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q
2.568	0.009	tNET	FF	1	R17C48[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_4_s0/I1
2.720	0.153	tINS	FF	1	R17C48[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_4_s0/F
2.720	0.000	tNET	FF	1	R17C48[1][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.418	1.067	tNET	RR	1	R17C48[1][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK
2.443	0.025	tHld		1	R17C48[1][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.884%; route: 1.067, 44.116%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.884%; route: 1.067, 44.116%

Path14

Path Summary:

Slack	0.278
Data Arrival Time	1.675
Data Required Time	1.397
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R13C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.513	0.141	tC2Q	RF	39	R13C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
1.522	0.009	tNET	FF	1	R13C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n929_s1/I1
1.675	0.153	tINS	FF	1	R13C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n929_s1/F
1.675	0.000	tNET	FF	1	R13C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R13C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.397	0.025	tHld		1	R13C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.235%; route: 0.697, 50.765%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 49.235%; route: 0.697, 50.765%

Path15

Path Summary:

Slack	0.278
Data Arrival Time	1.675
Data Required Time	1.397
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
1.513	0.141	tC2Q	RF	38	R14C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/Q
1.522	0.009	tNET	FF	1	R14C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n924_s1/I1
1.675	0.153	tINS	FF	1	R14C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n924_s1/F
1.675	0.000	tNET	FF	1	R14C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
1.397	0.025	tHld		1	R14C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path16

Path Summary:

Slack	0.278
Data Arrival Time	1.668
Data Required Time	1.390
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C48[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
1.506	0.141	tC2Q	RF	4	R13C48[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q
1.515	0.009	tNET	FF	1	R13C48[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n819_s0/I1
1.668	0.153	tINS	FF	1	R13C48[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n819_s0/F
1.668	0.000	tNET	FF	1	R13C48[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C48[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
1.390	0.025	tHld		1	R13C48[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path17

Path Summary:

Slack	0.278
Data Arrival Time	1.664
Data Required Time	1.386
From	start_s0
To	start_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.361	0.685	tNET	RR	1	R12C56[0][A]	start_s0/CLK
1.502	0.141	tC2Q	RF	15	R12C56[0][A]	start_s0/Q
1.511	0.009	tNET	FF	1	R12C56[0][A]	n58_s1/I0
1.664	0.153	tINS	FF	1	R12C56[0][A]	n58_s1/F
1.664	0.000	tNET	FF	1	R12C56[0][A]	start_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.361	0.685	tNET	RR	1	R12C56[0][A]	start_s0/CLK
1.386	0.025	tHld		1	R12C56[0][A]	start_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%

Path18

Path Summary:

Slack	0.278
Data Arrival Time	2.721
Data Required Time	2.443
From	gw_gao_inst_0/u_la0_top/word_count_0_s0
To	gw_gao_inst_0/u_la0_top/word_count_0_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.418	1.067	tNET	RR	1	R27C39[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.559	0.141	tC2Q	RF	5	R27C39[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/Q
2.568	0.009	tNET	FF	1	R27C39[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/I1
2.721	0.153	tINS	FF	1	R27C39[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/F
2.721	0.000	tNET	FF	1	R27C39[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.418	1.067	tNET	RR	1	R27C39[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.443	0.025	tHld		1	R27C39[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.873%; route: 1.067, 44.127%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.873%; route: 1.067, 44.127%

Path19

Path Summary:

Slack	0.278
Data Arrival Time	2.727
Data Required Time	2.449
From	gw_gao_inst_0/u_la0_top/word_count_4_s0
To	gw_gao_inst_0/u_la0_top/word_count_4_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.424	1.073	tNET	RR	1	R25C38[1][A]	gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
2.565	0.141	tC2Q	RF	4	R25C38[1][A]	gw_gao_inst_0/u_la0_top/word_count_4_s0/Q
2.574	0.009	tNET	FF	1	R25C38[1][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/I1
2.727	0.153	tINS	FF	1	R25C38[1][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/F
2.727	0.000	tNET	FF	1	R25C38[1][A]	gw_gao_inst_0/u_la0_top/word_count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.424	1.073	tNET	RR	1	R25C38[1][A]	gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
2.449	0.025	tHld		1	R25C38[1][A]	gw_gao_inst_0/u_la0_top/word_count_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.734%; route: 1.073, 44.266%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.734%; route: 1.073, 44.266%

Path20

Path Summary:

Slack	0.278
Data Arrival Time	2.722
Data Required Time	2.444
From	gw_gao_inst_0/u_la0_top/address_counter_0_s0
To	gw_gao_inst_0/u_la0_top/address_counter_0_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.419	1.068	tNET	RR	1	R18C48[1][A]	gw_gao_inst_0/u_la0_top/address_counter_0_s0/CLK
2.560	0.141	tC2Q	RF	40	R18C48[1][A]	gw_gao_inst_0/u_la0_top/address_counter_0_s0/Q
2.569	0.009	tNET	FF	1	R18C48[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_0_s0/I0
2.722	0.153	tINS	FF	1	R18C48[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_0_s0/F
2.722	0.000	tNET	FF	1	R18C48[1][A]	gw_gao_inst_0/u_la0_top/address_counter_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	509	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.419	1.068	tNET	RR	1	R18C48[1][A]	gw_gao_inst_0/u_la0_top/address_counter_0_s0/CLK
2.444	0.025	tHld		1	R18C48[1][A]	gw_gao_inst_0/u_la0_top/address_counter_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.855%; route: 1.068, 44.145%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.855%; route: 1.068, 44.145%

Path21

Path Summary:

Slack	0.281
Data Arrival Time	1.674
Data Required Time	1.393
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.510	0.141	tC2Q	RF	41	R14C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
1.521	0.012	tNET	FF	1	R14C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n934_s2/I0
1.674	0.153	tINS	FF	1	R14C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n934_s2/F
1.674	0.000	tNET	FF	1	R14C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.393	0.025	tHld		1	R14C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay	cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path22

Path Summary:

Slack	0.281
Data Arrival Time	1.674
Data Required Time	1.393
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.510	0.141	tC2Q	RF	39	R14C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
1.521	0.012	tNET	FF	1	R14C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n926_s1/I1
1.674	0.153	tINS	FF	1	R14C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n926_s1/F
1.674	0.000	tNET	FF	1	R14C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.393	0.025	tHld		1	R14C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay	cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path23

Path Summary:

Slack	0.281
Data Arrival Time	1.675
Data Required Time	1.394
From	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C40[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.510	0.141	tC2Q	RF	9	R11C40[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/Q
1.522	0.012	tNET	FF	1	R11C40[0][A]	gw_gao_inst_0/u_la0_top/n4874_s1/I2
1.675	0.153	tINS	FF	1	R11C40[0][A]	gw_gao_inst_0/u_la0_top/n4874_s1/F
1.675	0.000	tNET	FF	1	R11C40[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C40[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.394	0.025	tHld		1	R11C40[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path24

Path Summary:

Slack	0.288
Data Arrival Time	1.699
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_66_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_16_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.376	0.701	tNET	RR	1	R18C42[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_66_s0/CLK
1.520	0.144	tC2Q	RR	1	R18C42[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_66_s0/Q
1.699	0.179	tNET	RR	1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_16_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_16_s/CLKA
1.411	0.037	tHld		1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_16_s

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.083%; route: 0.701, 50.917%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.179, 55.418%; tC2Q: 0.144, 44.582%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path25

Path Summary:

Slack	0.290
Data Arrival Time	1.705
Data Required Time	1.415
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_62_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R17C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_62_s0/CLK
1.523	0.144	tC2Q	RR	1	R17C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_62_s0/Q
1.705	0.182	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/CLKA
1.415	0.037	tHld		1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s

Path Statistics:

Clock Skew	-0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.985%; route: 0.704, 51.015%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.182, 55.828%; tC2Q: 0.144, 44.172%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	3.037
Data Arrival Time	9.237
Data Required Time	12.274
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.237	1.201	tNET	FF	1	R17C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.621	1.939	tNET	RR	1	R17C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLK
12.274	-0.347	tSu		1	R17C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0

Path Statistics:

Clock Skew	0.028
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.201, 73.080%; tC2Q: 0.442, 26.920%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path2

Path Summary:

Slack	3.302
Data Arrival Time	8.948
Data Required Time	12.250
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.948	0.912	tNET	FF	1	R11C43[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.597	1.915	tNET	RR	1	R11C43[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
12.250	-0.347	tSu		1	R11C43[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.912, 67.343%; tC2Q: 0.442, 32.657%
Required Clock Path Delay	cell: 0.683, 26.275%; route: 1.915, 73.725%

Path3

Path Summary:

Slack	3.415
Data Arrival Time	8.874
Data Required Time	12.289
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.874	0.839	tNET	FF	1	R21C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.636	1.954	tNET	RR	1	R21C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
12.289	-0.347	tSu		1	R21C47[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.839, 65.463%; tC2Q: 0.442, 34.537%
Required Clock Path Delay	cell: 0.683, 25.889%; route: 1.954, 74.111%

Path4

Path Summary:

Slack	3.415
Data Arrival Time	8.874
Data Required Time	12.289
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.874	0.839	tNET	FF	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.636	1.954	tNET	RR	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
12.289	-0.347	tSu		1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.839, 65.463%; tC2Q: 0.442, 34.537%
Required Clock Path Delay	cell: 0.683, 25.889%; route: 1.954, 74.111%

Path5

Path Summary:

Slack	3.415
Data Arrival Time	8.874
Data Required Time	12.289
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.874	0.839	tNET	FF	1	R21C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.636	1.954	tNET	RR	1	R21C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLK
12.289	-0.347	tSu		1	R21C47[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.839, 65.463%; tC2Q: 0.442, 34.537%
Required Clock Path Delay	cell: 0.683, 25.889%; route: 1.954, 74.111%

Path6

Path Summary:

Slack	3.415
Data Arrival Time	8.874
Data Required Time	12.289
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.874	0.839	tNET	FF	1	R21C47[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.636	1.954	tNET	RR	1	R21C47[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLK
12.289	-0.347	tSu		1	R21C47[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.839, 65.463%; tC2Q: 0.442, 34.537%
Required Clock Path Delay	cell: 0.683, 25.889%; route: 1.954, 74.111%

Path7

Path Summary:

Slack	3.415
Data Arrival Time	8.874
Data Required Time	12.289
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.874	0.839	tNET	FF	1	R21C47[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.636	1.954	tNET	RR	1	R21C47[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLK
12.289	-0.347	tSu		1	R21C47[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.839, 65.463%; tC2Q: 0.442, 34.537%
Required Clock Path Delay	cell: 0.683, 25.889%; route: 1.954, 74.111%

Path8

Path Summary:

Slack	3.415
Data Arrival Time	8.874
Data Required Time	12.289
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.874	0.839	tNET	FF	1	R21C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.636	1.954	tNET	RR	1	R21C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLK
12.289	-0.347	tSu		1	R21C47[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.839, 65.463%; tC2Q: 0.442, 34.537%
Required Clock Path Delay	cell: 0.683, 25.889%; route: 1.954, 74.111%

Path9

Path Summary:

Slack	3.415
Data Arrival Time	8.874
Data Required Time	12.289
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.874	0.839	tNET	FF	1	R21C47[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.636	1.954	tNET	RR	1	R21C47[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLK
12.289	-0.347	tSu		1	R21C47[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.839, 65.463%; tC2Q: 0.442, 34.537%
Required Clock Path Delay	cell: 0.683, 25.889%; route: 1.954, 74.111%

Path10

Path Summary:

Slack	3.442
Data Arrival Time	8.813
Data Required Time	12.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.813	0.778	tNET	FF	1	R14C42[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.602	1.920	tNET	RR	1	R14C42[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
12.255	-0.347	tSu		1	R14C42[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	0.009
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.778, 63.730%; tC2Q: 0.442, 36.270%
Required Clock Path Delay	cell: 0.683, 26.228%; route: 1.920, 73.772%

Path11

Path Summary:

Slack	3.451
Data Arrival Time	8.813
Data Required Time	12.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.813	0.778	tNET	FF	1	R14C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.612	1.929	tNET	RR	1	R14C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
12.264	-0.347	tSu		1	R14C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew	0.019
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.778, 63.730%; tC2Q: 0.442, 36.270%
Required Clock Path Delay	cell: 0.683, 26.134%; route: 1.929, 73.866%

Path12

Path Summary:

Slack	3.451
Data Arrival Time	8.813
Data Required Time	12.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.813	0.778	tNET	FF	1	R14C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.612	1.929	tNET	RR	1	R14C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK
12.264	-0.347	tSu		1	R14C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1

Path Statistics:

Clock Skew	0.019
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.778, 63.730%; tC2Q: 0.442, 36.270%
Required Clock Path Delay	cell: 0.683, 26.134%; route: 1.929, 73.866%

Path13

Path Summary:

Slack	3.493
Data Arrival Time	8.755
Data Required Time	12.249
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.755	0.720	tNET	FF	1	R13C44[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.596	1.914	tNET	RR	1	R13C44[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
12.249	-0.347	tSu		1	R13C44[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.720, 61.935%; tC2Q: 0.442, 38.065%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path14

Path Summary:

Slack	3.493
Data Arrival Time	8.755
Data Required Time	12.249
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.755	0.720	tNET	FF	1	R13C44[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.596	1.914	tNET	RR	1	R13C44[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
12.249	-0.347	tSu		1	R13C44[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.720, 61.935%; tC2Q: 0.442, 38.065%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path15

Path Summary:

Slack	3.503
Data Arrival Time	8.755
Data Required Time	12.258
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.755	0.720	tNET	FF	1	R13C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
12.258	-0.347	tSu		1	R13C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	0.013
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.720, 61.935%; tC2Q: 0.442, 38.065%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path16

Path Summary:

Slack	3.503
Data Arrival Time	8.755
Data Required Time	12.258
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.755	0.720	tNET	FF	1	R13C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
12.258	-0.347	tSu		1	R13C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.013
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.720, 61.935%; tC2Q: 0.442, 38.065%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path17

Path Summary:

Slack	3.503
Data Arrival Time	8.755
Data Required Time	12.258
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.755	0.720	tNET	FF	1	R13C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
12.258	-0.347	tSu		1	R13C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.013
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.720, 61.935%; tC2Q: 0.442, 38.065%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path18

Path Summary:

Slack	3.504
Data Arrival Time	8.755
Data Required Time	12.259
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.755	0.720	tNET	FF	1	R11C42[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.607	1.924	tNET	RR	1	R11C42[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
12.259	-0.347	tSu		1	R11C42[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	0.014
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.720, 61.935%; tC2Q: 0.442, 38.065%
Required Clock Path Delay	cell: 0.683, 26.181%; route: 1.924, 73.819%

Path19

Path Summary:

Slack	3.504
Data Arrival Time	8.755
Data Required Time	12.259
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.755	0.720	tNET	FF	1	R11C42[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.607	1.924	tNET	RR	1	R11C42[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
12.259	-0.347	tSu		1	R11C42[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	0.014
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.720, 61.935%; tC2Q: 0.442, 38.065%
Required Clock Path Delay	cell: 0.683, 26.181%; route: 1.924, 73.819%

Path20

Path Summary:

Slack	3.504
Data Arrival Time	8.755
Data Required Time	12.259
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.755	0.720	tNET	FF	1	R11C42[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.607	1.924	tNET	RR	1	R11C42[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
12.259	-0.347	tSu		1	R11C42[0][A]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	0.014
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.720, 61.935%; tC2Q: 0.442, 38.065%
Required Clock Path Delay	cell: 0.683, 26.181%; route: 1.924, 73.819%

Path21

Path Summary:

Slack	3.504
Data Arrival Time	8.755
Data Required Time	12.259
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.755	0.720	tNET	FF	1	R11C42[0][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.607	1.924	tNET	RR	1	R11C42[0][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
12.259	-0.347	tSu		1	R11C42[0][B]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	0.014
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.720, 61.935%; tC2Q: 0.442, 38.065%
Required Clock Path Delay	cell: 0.683, 26.181%; route: 1.924, 73.819%

Path22

Path Summary:

Slack	3.513
Data Arrival Time	8.755
Data Required Time	12.269
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.755	0.720	tNET	FF	1	R11C41[3][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.616	1.934	tNET	RR	1	R11C41[3][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
12.269	-0.347	tSu		1	R11C41[3][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.720, 61.935%; tC2Q: 0.442, 38.065%
Required Clock Path Delay	cell: 0.683, 26.087%; route: 1.934, 73.913%

Path23

Path Summary:

Slack	3.513
Data Arrival Time	8.755
Data Required Time	12.269
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.755	0.720	tNET	FF	1	R11C41[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.616	1.934	tNET	RR	1	R11C41[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
12.269	-0.347	tSu		1	R11C41[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.720, 61.935%; tC2Q: 0.442, 38.065%
Required Clock Path Delay	cell: 0.683, 26.087%; route: 1.934, 73.913%

Path24

Path Summary:

Slack	3.513
Data Arrival Time	8.755
Data Required Time	12.269
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.755	0.720	tNET	FF	1	R11C41[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.616	1.934	tNET	RR	1	R11C41[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
12.269	-0.347	tSu		1	R11C41[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew	0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.720, 61.935%; tC2Q: 0.442, 38.065%
Required Clock Path Delay	cell: 0.683, 26.087%; route: 1.934, 73.913%

Path25

Path Summary:

Slack	3.513
Data Arrival Time	8.755
Data Required Time	12.269
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	537	IOB29[A]	clk_ibuf/O
7.593	1.905	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.035	0.442	tC2Q	FF	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.755	0.720	tNET	FF	1	R11C41[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	537	IOB29[A]	clk_ibuf/O
12.616	1.934	tNET	RR	1	R11C41[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
12.269	-0.347	tSu		1	R11C41[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew	0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.516%; route: 1.905, 73.484%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.720, 61.935%; tC2Q: 0.442, 38.065%
Required Clock Path Delay	cell: 0.683, 26.087%; route: 1.934, 73.913%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.365
Data Arrival Time	6.681
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681	0.158	tNET	RR	1	R11C38[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C38[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
1.316	-0.053	tHld		1	R11C38[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	0.004
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.158, 50.000%; tC2Q: 0.158, 50.000%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path2

Path Summary:

Slack	5.365
Data Arrival Time	6.681
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681	0.158	tNET	RR	1	R11C38[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C38[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
1.316	-0.053	tHld		1	R11C38[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	0.004
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.158, 50.000%; tC2Q: 0.158, 50.000%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path3

Path Summary:

Slack	5.365
Data Arrival Time	6.681
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681	0.158	tNET	RR	1	R11C38[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C38[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
1.316	-0.053	tHld		1	R11C38[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.158, 50.000%; tC2Q: 0.158, 50.000%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path4

Path Summary:

Slack	5.365
Data Arrival Time	6.681
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681	0.158	tNET	RR	1	R11C38[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C38[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
1.316	-0.053	tHld		1	R11C38[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.158, 50.000%; tC2Q: 0.158, 50.000%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path5

Path Summary:

Slack	5.412
Data Arrival Time	6.732
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.732	0.208	tNET	RR	1	R14C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.319	-0.053	tHld		1	R14C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.007
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path6

Path Summary:

Slack	5.412
Data Arrival Time	6.732
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.732	0.208	tNET	RR	1	R14C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
1.319	-0.053	tHld		1	R14C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	0.007
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path7

Path Summary:

Slack	5.418
Data Arrival Time	6.734
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.734	0.210	tNET	RR	1	R14C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.316	-0.053	tHld		1	R14C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.210, 57.065%; tC2Q: 0.158, 42.935%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path8

Path Summary:

Slack	5.418
Data Arrival Time	6.734
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.734	0.210	tNET	RR	1	R14C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
1.316	-0.053	tHld		1	R14C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.210, 57.065%; tC2Q: 0.158, 42.935%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path9

Path Summary:

Slack	5.418
Data Arrival Time	6.734
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.734	0.210	tNET	RR	1	R14C38[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C38[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
1.316	-0.053	tHld		1	R14C38[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.210, 57.065%; tC2Q: 0.158, 42.935%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path10

Path Summary:

Slack	5.471
Data Arrival Time	6.787
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.787	0.264	tNET	RR	1	R11C40[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C40[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.316	-0.053	tHld		1	R11C40[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 62.559%; tC2Q: 0.158, 37.441%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path11

Path Summary:

Slack	5.471
Data Arrival Time	6.787
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.787	0.264	tNET	RR	1	R11C40[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C40[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.316	-0.053	tHld		1	R11C40[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 62.559%; tC2Q: 0.158, 37.441%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path12

Path Summary:

Slack	5.471
Data Arrival Time	6.787
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.787	0.264	tNET	RR	1	R11C40[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C40[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
1.316	-0.053	tHld		1	R11C40[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 62.559%; tC2Q: 0.158, 37.441%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path13

Path Summary:

Slack	5.471
Data Arrival Time	6.787
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.787	0.264	tNET	RR	1	R11C40[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C40[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
1.316	-0.053	tHld		1	R11C40[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 62.559%; tC2Q: 0.158, 37.441%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path14

Path Summary:

Slack	5.471
Data Arrival Time	6.787
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.787	0.264	tNET	RR	1	R11C40[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C40[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
1.316	-0.053	tHld		1	R11C40[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 62.559%; tC2Q: 0.158, 37.441%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path15

Path Summary:

Slack	5.471
Data Arrival Time	6.787
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.787	0.264	tNET	RR	1	R11C40[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C40[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
1.316	-0.053	tHld		1	R11C40[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 62.559%; tC2Q: 0.158, 37.441%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path16

Path Summary:

Slack	5.475
Data Arrival Time	6.787
Data Required Time	1.313
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.787	0.264	tNET	RR	1	R11C39[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.365	0.690	tNET	RR	1	R11C39[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.313	-0.053	tHld		1	R11C39[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 62.559%; tC2Q: 0.158, 37.441%
Required Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%

Path17

Path Summary:

Slack	5.475
Data Arrival Time	6.787
Data Required Time	1.313
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.787	0.264	tNET	RR	1	R11C39[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.365	0.690	tNET	RR	1	R11C39[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
1.313	-0.053	tHld		1	R11C39[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 62.559%; tC2Q: 0.158, 37.441%
Required Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%

Path18

Path Summary:

Slack	5.475
Data Arrival Time	6.787
Data Required Time	1.313
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.787	0.264	tNET	RR	1	R11C39[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.365	0.690	tNET	RR	1	R11C39[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
1.313	-0.053	tHld		1	R11C39[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 62.559%; tC2Q: 0.158, 37.441%
Required Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%

Path19

Path Summary:

Slack	5.475
Data Arrival Time	6.787
Data Required Time	1.313
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.787	0.264	tNET	RR	1	R11C39[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.365	0.690	tNET	RR	1	R11C39[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
1.313	-0.053	tHld		1	R11C39[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 62.559%; tC2Q: 0.158, 37.441%
Required Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%

Path20

Path Summary:

Slack	5.518
Data Arrival Time	6.833
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.833	0.310	tNET	RR	1	R14C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.316	-0.053	tHld		1	R14C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.310, 66.239%; tC2Q: 0.158, 33.761%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path21

Path Summary:

Slack	5.518
Data Arrival Time	6.833
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.833	0.310	tNET	RR	1	R14C40[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C40[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.316	-0.053	tHld		1	R14C40[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.310, 66.239%; tC2Q: 0.158, 33.761%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path22

Path Summary:

Slack	5.548
Data Arrival Time	6.871
Data Required Time	1.323
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.871	0.347	tNET	RR	1	R14C46[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.376	0.701	tNET	RR	1	R14C46[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
1.323	-0.053	tHld		1	R14C46[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	0.010
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.347, 68.713%; tC2Q: 0.158, 31.287%
Required Clock Path Delay	cell: 0.675, 49.092%; route: 0.701, 50.908%

Path23

Path Summary:

Slack	5.548
Data Arrival Time	6.871
Data Required Time	1.323
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.871	0.347	tNET	RR	1	R14C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.376	0.701	tNET	RR	1	R14C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLK
1.323	-0.053	tHld		1	R14C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1

Path Statistics:

Clock Skew	0.010
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.347, 68.713%; tC2Q: 0.158, 31.287%
Required Clock Path Delay	cell: 0.675, 49.092%; route: 0.701, 50.908%

Path24

Path Summary:

Slack	5.552
Data Arrival Time	6.871
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.871	0.347	tNET	RR	1	R13C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R13C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.319	-0.053	tHld		1	R13C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	0.006
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.347, 68.713%; tC2Q: 0.158, 31.287%
Required Clock Path Delay	cell: 0.675, 49.235%; route: 0.697, 50.765%

Path25

Path Summary:

Slack	5.552
Data Arrival Time	6.871
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	537	IOB29[A]	clk_ibuf/O
6.365	0.688	tNET	FF	1	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.523	0.158	tC2Q	FR	75	R12C38[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.871	0.347	tNET	RR	1	R13C46[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	537	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R13C46[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
1.319	-0.053	tHld		1	R13C46[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	0.006
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.616%; route: 0.688, 50.384%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.347, 68.713%; tC2Q: 0.158, 31.287%
Required Clock Path Delay	cell: 0.675, 49.235%; route: 0.697, 50.765%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.747
Actual Width:	3.747
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	b_d_0_s2

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	b_d_0_s2/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.375	0.699	tNET	RR	b_d_0_s2/CLK

MPW2

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW3

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA

MPW4

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA

MPW5

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s/CLKA

MPW6

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_27_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_27_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_27_s/CLKA

MPW7

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_28_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_28_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_28_s/CLKA

MPW8

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/CLKA

MPW9

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/CLKA

MPW10

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	uut/u_xcorr/memy_memy_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	uut/u_xcorr/memy_memy_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	uut/u_xcorr/memy_memy_0_0_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
537	clk_d	1.224	1.975
509	gw_gao_inst_0/control0[0]	3.382	2.754
160	gw_gao_inst_0/u_la0_top/n20_3	45.497	2.101
140	gw_gao_inst_0/u_la0_top/data_out_shift_reg_137_7	43.903	2.111
131	gw_gao_inst_0/u_la0_top/n1227_5	43.663	1.599
123	gw_gao_inst_0/u_la0_top/n1227_4	44.001	1.633
75	gw_gao_inst_0/u_la0_top/rst_ao	3.037	1.226
50	gw_gao_inst_0/u_la0_top/data_to_word_counter_15_11	44.715	1.487
46	complete_d	6.632	2.240
44	uut/u_xcorr/r_42_12	1.386	1.214

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C4	100.00%
R2C19	100.00%
R2C20	100.00%
R2C52	100.00%
R3C26	100.00%
R4C63	100.00%
R7C47	100.00%
R13C36	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]