#Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep 3 2018 #install: D:\Gowin\1.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-042 # Fri Sep 28 13:58:22 2018 #Implementation: rev_1 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\Complex_Multiplier\Complex_Multiplier.v" (library work) @I::"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\top.v" (library work) @I:"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\top.v":"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\Wreal1.txt" (library work) @I:"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\top.v":"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\Wreal2.txt" (library work) @I:"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\top.v":"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\Wimag1.txt" (library work) @I:"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\top.v":"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\Wimag2.txt" (library work) @I:"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\top.v":"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\Wrealo.txt" (library work) @I:"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\top.v":"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\Wimago.txt" (library work) Verilog syntax check successful! Options changed - recompiling Selecting top level module top @N:CG364 : gw2a.v(1597) | Synthesizing module GSR in library work. Running optimization stage 1 on GSR ....... Running optimization stage 1 on ALU54D ....... Running optimization stage 1 on MULT9X9 ....... Running optimization stage 1 on GND ....... Running optimization stage 1 on VCC ....... Running optimization stage 1 on \(cmp_core)/(complex_multiplier)_9s_1_SYNC_0_0_0_9s ....... @N:CG364 : Complex_Multiplier.v(221) | Synthesizing module complex_multiplier in library work. Running optimization stage 1 on complex_multiplier ....... @W:CL168 : Complex_Multiplier.v(274) | Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : top.v(1) | Synthesizing module top in library work. @N:CG179 : top.v(29) | Removing redundant assignment. @N:CG179 : top.v(57) | Removing redundant assignment. Running optimization stage 1 on top ....... @N:CL189 : top.v(34) | Register bit mimago[6] is always 0. @N:CL189 : top.v(34) | Register bit mimago[5] is always 0. @N:CL189 : top.v(34) | Register bit mimago[4] is always 0. @N:CL189 : top.v(34) | Register bit mimago[3] is always 0. @N:CL189 : top.v(34) | Register bit mimago[2] is always 0. @W:CL279 : top.v(34) | Pruning register bits 6 to 2 of mimago[18:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Running optimization stage 2 on top ....... Running optimization stage 2 on complex_multiplier ....... Running optimization stage 2 on \(cmp_core)/(complex_multiplier)_9s_1_SYNC_0_0_0_9s ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on MULT9X9 ....... Running optimization stage 2 on ALU54D ....... Running optimization stage 2 on GSR ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Sep 28 13:58:23 2018 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode File E:\ide\IP_TEST_GOLDEN\gwip_ref_design\reference design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\impl\synthesize\rev_1\synwork\layer0.srs changed - recompiling @N:NF107 : top.v(1) | Selected library: work cell: top view verilog as top level @N:NF107 : top.v(1) | Selected library: work cell: top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Sep 28 13:58:23 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Sep 28 13:58:23 2018 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Database state : E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\impl\synthesize\rev_1\synwork\|rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode File E:\ide\IP_TEST_GOLDEN\gwip_ref_design\reference design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\impl\synthesize\rev_1\synwork\cmult_9_comp.srs changed - recompiling @N:NF107 : top.v(1) | Selected library: work cell: top view verilog as top level @N:NF107 : top.v(1) | Selected library: work cell: top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Sep 28 13:58:24 2018 ###########################################################] Premap Report # Fri Sep 28 13:58:25 2018 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1167R, Built Sep 4 2018 10:03:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @A:MF827 : | No constraint file specified. @N:MF284 : | Setting synthesis effort to medium for the design Linked File: cmult_9_scck.rpt Printing clock summary report in "E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\impl\synthesize\rev_1\cmult_9_scck.rpt" file @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MH105 : | UMR3 is only supported for HAPS-80. @N:MH105 : | UMR3 is only supported for HAPS-80. Beginning opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB) Finished opaque latch marking step (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB) Rerun analysis in 0 latches Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB) @N:MF974 : | Total number of latches (multibit) processed = 0 @N:MF975 : | Total number of latches (bit blasted) processed = 0 @N:MF976 : | Total number of (multibit) opaque latches found = 0 @N:MF977 : | Total number of (bit blasted) opaque latches found = 0 Finished opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB) Detailed report for transparent and observable latches in design: Linked File: cmult_9_prem_latch_transparency_report.log Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB) Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB) syn_allowed_resources : blockrams=140 set on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------- 0 - top|clk 323.5 MHz 3.091 inferred Autoconstr_clkgroup_0 90 ============================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ------------------------------------------------------------------------------------ top|clk 90 clk(port) imag1[8:0].C - - ==================================================================================== ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 90 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId_0_0 clk Unconstrained_port 90 ad[8:0] ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\impl\synthesize\rev_1\cmult_9.sap. Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB) None None Finished constraint checker (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 105MB peak: 192MB) Process took 0h:00m:04s realtime, 0h:00m:03s cputime # Fri Sep 28 13:58:29 2018 ###########################################################] Map & Optimize Report # Fri Sep 28 13:58:29 2018 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw, Build 1167R, Built Sep 4 2018 10:03:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) @N:MF284 : | Setting synthesis effort to medium for the design Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB) @N:MO231 : top.v(52) | Found counter in view:work.top(verilog) instance ad[8:0] @N:MF179 : top.v(65) | Found 19 by 19 bit equality operator ('==') un1_realo (in view: work.top(verilog)) @N:MF179 : top.v(74) | Found 19 by 19 bit equality operator ('==') un1_imago (in view: work.top(verilog)) Starting factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 190MB peak: 192MB) Finished factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 191MB peak: 192MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 192MB peak: 193MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 193MB peak: 193MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 193MB peak: 193MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 192MB peak: 193MB) @A:BN291 : top.v(34) | Boundary register mimago_1[0] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mimago_1[1] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mimago_1[2] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mimago_1[3] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mimago_1[4] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mimago_1[5] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mimago_1[6] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mimago_1[7] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mimago_1[8] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mimago_1[9] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mimago_1[10] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mimago_1[11] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mimago_1[12] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mimago_1[13] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[0] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[1] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[2] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[3] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[4] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[5] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[6] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[7] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[8] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[9] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[10] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[11] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[12] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[13] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[14] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[15] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[16] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[17] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : top.v(34) | Boundary register mrealo[18] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_00 = 0001FF000000FF0000000100000201000401FF000400FF000400010000000000. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_01 = 03FDFF0003FCFF0003FC010003FE010001FDFF0001FCFF0001FC010001FE0100. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_02 = 0001FE000000FE0000000000000200000401FE000400FE000400000004020000. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_03 = 03FDFE0003FCFE0003FC000003FE000001FDFE0001FCFE0001FC000001FE0000. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_04 = 0001FE7F0000FE7F0000007F0002007F0401FE7F0400FE7F0400007F0402007F. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_05 = 03FDFE7F03FCFE7F03FC007F03FE007F01FDFE7F01FCFE7F01FC007F01FE007F. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_06 = 0001FEFF0000FEFF000000FF000200FF0401FEFF0400FEFF040000FF040200FF. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_07 = 03FDFEFF03FCFEFF03FC00FF03FE00FF01FDFEFF01FCFEFF01FC00FF01FE00FF. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_08 = 0001FF000000FF0000000100000201000401FF000400FF000400010004020100. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_09 = 03FDFF0003FCFF0003FC010003FE010001FDFF0001FCFF0001FC010001FE0100. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_0A = 0001FE000000FE0000000000000200000401FE000400FE000400000004020000. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_0B = 03FDFE0003FCFE0003FC000003FE000001FDFE0001FCFE0001FC000001FE0000. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_0C = 0001FE7F0000FE7F0000007F0002007F0401FE7F0400FE7F0400007F0402007F. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_0D = 03FDFE7F03FCFE7F03FC007F03FE007F01FDFE7F01FCFE7F01FC007F01FE007F. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_0E = 0001FEFF0000FEFF000000FF000200FF0401FEFF0400FEFF040000FF040200FF. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_0F = 03FDFEFF03FCFEFF03FC00FF03FE00FF01FDFEFF01FCFEFF01FC00FF01FE00FF. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_10 = F801FF00F800FF00F8000100F8020100FC01FF00FC00FF00FC000100FC020100. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_11 = FBFDFF00FBFCFF00FBFC0100FBFE0100F9FDFF00F9FCFF00F9FC0100F9FE0100. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_12 = F801FE00F800FE00F8000000F8020000FC01FE00FC00FE00FC000000FC020000. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_13 = FBFDFE00FBFCFE00FBFC0000FBFE0000F9FDFE00F9FCFE00F9FC0000F9FE0000. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_14 = F801FE7FF800FE7FF800007FF802007FFC01FE7FFC00FE7FFC00007FFC02007F. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_15 = FBFDFE7FFBFCFE7FFBFC007FFBFE007FF9FDFE7FF9FCFE7FF9FC007FF9FE007F. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_16 = F801FEFFF800FEFFF80000FFF80200FFFC01FEFFFC00FEFFFC0000FFFC0200FF. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_17 = FBFDFEFFFBFCFEFFFBFC00FFFBFE00FFF9FDFEFFF9FCFEFFF9FC00FFF9FE00FF. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_18 = F801FF00F800FF00F8000100F8020100FC01FF00FC00FF00FC000100FC020100. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_19 = FBFDFF00FBFCFF00FBFC0100FBFE0100F9FDFF00F9FCFF00F9FC0100F9FE0100. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_1A = F801FE00F800FE00F8000000F8020000FC01FE00FC00FE00FC000000FC020000. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_1B = FBFDFE00FBFCFE00FBFC0000FBFE0000F9FDFE00F9FCFE00F9FC0000F9FE0000. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_1C = F801FE7FF800FE7FF800007FF802007FFC01FE7FFC00FE7FFC00007FFC02007F. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_1D = FBFDFE7FFBFCFE7FFBFC007FFBFE007FF9FDFE7FF9FCFE7FF9FC007FF9FE007F. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_1E = F801FEFFF800FEFFF80000FFF80200FFFC01FEFFFC00FEFFFC0000FFFC0200FF. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_1F = FBFDFEFFFBFCFEFFFBFC00FFFBFE00FFF9FDFEFFF9FCFEFFF9FC00FFF9FE00FF. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_20 = 0001FF000000FF0000000100000201000401FF000400FF000400010004020100. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_21 = 03FDFF0003FCFF0003FC010003FE010001FDFF0001FCFF0001FC010001FE0100. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_22 = 0001FE000000FE0000000000000200000401FE000400FE000400000004020000. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_23 = 03FDFE0003FCFE0003FC000003FE000001FDFE0001FCFE0001FC000001FE0000. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_24 = 0001FE7F0000FE7F0000007F0002007F0401FE7F0400FE7F0400007F0402007F. @N:FX276 : top.v(49) | Initial value mimago_2_0_0.INIT_RAM_25 = 0000000000000000000000000000000001FDFE7F01FCFE7F01FC007F01FE007F. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_00 = 0470100804781008000000080010000804601008046810080070000800000000. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_01 = 0800000808080008040FF008041FF00808780008080000080407F0080417F008. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_02 = 0400000804000008000000080000000804700008047000080070000800700008. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_03 = 040FF008040FF008000FF008000FF0080407F0080407F0080007F0080007F008. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_04 = 0407E8180403F01800000008007810080877E8180873F0180470000804681008. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_05 = FE97D818FE93E018FA8FF008FA880008008FD818008BE018FC87F008FC800008. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_06 = 040FE0180407E8180000000800701008087FE0180877E8180470000804601008. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_07 = FC9FD018FC97D818F88FF008F8800008FE97D018FE8FD818FA87F008FAF80008. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_08 = 0070100000781000000000000010000000701000007810000000000000100000. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_09 = 0470100004781000040000000410000004701000047810000400000004100000. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_0A = 0000000000000000000000000000000000000000000000000000000000000000. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_0B = 0000000000000000000000000000000000000000000000000000000000000000. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_0C = 0007E8100003F01000000000007810000407E8100403F0100400000004781000. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_0D = FA87E810FA83F010FA800000FAF81000FC87E810FC83F010FC800000FCF81000. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_0E = 000FE0100007E8100000000000701000040FE0100407E8100400000004701000. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_0F = F88FE010F887E810F8800000F8F01000FA8FE010FA87E810FA800000FAF01000. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_10 = FAF01003FCF810030000000304100003FAF80003FC8000030007F0030417F003. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_11 = FEE827F300F027F3047817F3080817F3FEEC1FF300F41FF3047C0FF3080C0FF3. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_12 = FA800003FC8000030000000304000003FA87F003FC87F0030007F0030407F003. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_13 = FAF817F3FCF817F3007817F3047817F3FAFC0FF3FCFC0FF3007C0FF3047C0FF3. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_14 = FA87E813FC83F0130000000304781003FE8FD813008BE0130407F00308000003. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_15 = F5000003F77C0803FAF817F3FEF027F3F703F803F9000003FCFC0FF300F41FF3. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_16 = FA8FE013FC87E8130000000304701003FE97D013008FD8130407F00308780003. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_17 = F307F803F5000003F8F817F3FCE827F3F50BF003F703F803FAFC0FF3FEEC1FF3. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_18 = F8F01007FAF810070000000704100007F8800007FA880007000FF007041FF007. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_19 = FCE02FF7FEE82FF704701FF708001FF7FCE827F7FEF027F7047817F7080817F7. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_1A = F8800007FA8000070000000704000007F88FF007FA8FF007000FF007040FF007. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_1B = F8F01FF7FAF01FF700701FF704701FF7F8F817F7FAF817F7007817F7047817F7. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_1C = F887E817FA83F0170000000704781007FC97D817FE93E017040FF00708080007. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_1D = F3780807F5741007FAF01FF7FEE82FF7F5000007F77C0807FCF817F700F027F7. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_1E = F88FE017FA87E8170000000704701007FC9FD017FE97D817040FF00708000007. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_1F = F1000007F3780807F8F01FF7FCE02FF7F307F807F5000007FAF817F7FEE827F7. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_20 = 0470100804781008000000080010000804601008046810080070000800000008. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_21 = 0800000808080008040FF008041FF00808780008080000080407F0080417F008. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_22 = 0400000804000008000000080000000804700008047000080070000800700008. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_23 = 040FF008040FF008000FF008000FF0080407F0080407F0080007F0080007F008. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_24 = 0407E8180403F01800000008007810080877E8180873F0180470000804681008. @N:FX276 : top.v(49) | Initial value mimago_2_0_1.INIT_RAM_25 = 00000000000000000000000000000000008FD818008BE018FC87F008FC800008. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_00 = 0000001C0000001E000000000000000400000000000000020000000400000000. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_01 = 000000180000001A0000001C000000000000001A0000001C0000001E00000002. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_02 = 0000001C0000001E00000000000000040000001C0000001E0000000000000004. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_03 = 0000001C0000001E00000000000000040000001C0000001E0000000000000004. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_04 = 0000001C0000001E00000000000000040000001A0000001C0000001E00000002. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_05 = 0000001D0000001F00000001000000050000001D0000001F0000000000000004. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_06 = 0000001C0000001E0000000000000004000000180000001A0000001C00000000. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_07 = 0000001F0000000100000003000000070000001D0000001F0000000100000005. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_08 = 0000000000000000000000000000000000000004000000040000000400000004. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_09 = 0000001C0000001C0000001C0000001C0000001E0000001E0000001E0000001E. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_0A = 0000000000000000000000000000000000000000000000000000000000000000. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_0B = 0000000000000000000000000000000000000000000000000000000000000000. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_0C = 000000000000000000000000000000000000001E0000001E0000001E0000001E. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_0D = 0000000100000001000000010000000100000000000000000000000000000000. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_0E = 000000000000000000000000000000000000001C0000001C0000001C0000001C. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_0F = 0000000300000003000000030000000300000001000000010000000100000001. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_10 = 0000000100000000000000000000001E00000005000000040000000400000002. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_11 = 0000001D0000001D0000001C0000001A0000001F0000001F0000001E0000001C. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_12 = 0000000100000000000000000000001E0000000100000000000000000000001E. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_13 = 0000000100000000000000000000001E0000000100000000000000000000001E. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_14 = 0000000100000000000000000000001E0000001F0000001F0000001E0000001C. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_15 = 0000000300000002000000010000001F0000000200000001000000000000001F. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_16 = 0000000100000000000000000000001E0000001D0000001D0000001C0000001A. @N:FX276 : top.v(49) | Initial value mimago_2_0_2.INIT_RAM_17 = 000000050000000400000003000000010000000300000002000000010000001F. Only the first 100 messages of id 'FX276' are reported. To see all messages use 'report_messages -log E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\impl\synthesize\rev_1\synlog\cmult_9_fpga_mapper.srr -id FX276' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {FX276} -count unlimited' in the Tcl shell. @N:FX211 : | Packed ROM mimago_2_0[68:0] (9 input, 69 output) to Block SelectRAM Finished preparing to map (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 193MB peak: 193MB) Finished technology mapping (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 192MB peak: 193MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:14s -2.70ns 35 / 15 2 0h:00m:14s -2.70ns 35 / 15 3 0h:00m:15s -2.70ns 35 / 15 4 0h:00m:15s -2.70ns 35 / 15 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:16s; Memory used current: 192MB peak: 193MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. @W:BN114 : top.v(49) | Removing instance mimago_2_0_0 (in view: work.top(verilog)) of black box view:VIRTEX.RAMB16(PRIM) because it does not drive other instances. @W:BN114 : top.v(49) | Removing instance mimago_2_0_1 (in view: work.top(verilog)) of black box view:VIRTEX.RAMB16(PRIM) because it does not drive other instances. @W:BN114 : top.v(49) | Removing instance mimago_2_0_2 (in view: work.top(verilog)) of black box view:VIRTEX.RAMB16(PRIM) because it does not drive other instances. Finished restoring hierarchy (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:19s; Memory used current: 192MB peak: 193MB) Start Writing Netlists (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:20s; Memory used current: 121MB peak: 193MB) Writing Analyst data base E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\impl\synthesize\rev_1\synwork\cmult_9_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:22s; CPU Time elapsed 0h:00m:21s; Memory used current: 191MB peak: 194MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:24s; CPU Time elapsed 0h:00m:23s; Memory used current: 193MB peak: 194MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:24s; CPU Time elapsed 0h:00m:23s; Memory used current: 191MB peak: 194MB) Start final timing analysis (Real Time elapsed 0h:00m:25s; CPU Time elapsed 0h:00m:23s; Memory used current: 192MB peak: 194MB) @W:MT420 : | Found inferred clock top|clk with period 5.24ns. Please declare a user-defined clock on port clk. ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Sep 28 13:58:55 2018 # Top view: top Requested Frequency: 190.7 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -0.925 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------ top|clk 190.7 MHz 162.1 MHz 5.243 6.168 -0.925 inferred Autoconstr_clkgroup_0 ======================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------- top|clk top|clk | 5.243 -0.925 | No paths - | No paths - | No paths - ========================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: top|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------- mimago_2_0_0 top|clk ROM DO[0] real2[0] 0.317 -0.925 mimago_2_0_0 top|clk ROM DO[1] real2[1] 0.317 -0.925 mimago_2_0_0 top|clk ROM DO[2] real2[2] 0.317 -0.925 mimago_2_0_0 top|clk ROM DO[3] real2[3] 0.317 -0.925 mimago_2_0_0 top|clk ROM DO[4] real2[4] 0.317 -0.925 mimago_2_0_0 top|clk ROM DO[5] real2[5] 0.317 -0.925 mimago_2_0_0 top|clk ROM DO[6] real2[6] 0.317 -0.925 mimago_2_0_0 top|clk ROM DO[7] real2[7] 0.317 -0.925 mimago_2_0_0 top|clk ROM DO[8] real2[8] 0.317 -0.925 mimago_2_0_0 top|clk ROM DO[9] real1[0] 0.317 -0.925 ================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------- u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq top|clk ALU54D A[17] g[17] 1.111 -0.925 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq top|clk ALU54D A[18] g[17] 1.111 -0.925 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq top|clk ALU54D A[19] g[17] 1.111 -0.925 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq top|clk ALU54D A[20] g[17] 1.111 -0.925 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq top|clk ALU54D A[21] g[17] 1.111 -0.925 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq top|clk ALU54D A[22] g[17] 1.111 -0.925 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq top|clk ALU54D A[23] g[17] 1.111 -0.925 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq top|clk ALU54D A[24] g[17] 1.111 -0.925 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq top|clk ALU54D A[25] g[17] 1.111 -0.925 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq top|clk ALU54D A[26] g[17] 1.111 -0.925 ========================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.243 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.182 - Propagation time: 6.107 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.925 Number of logic level(s): 17 Starting point: mimago_2_0_0 / DO[0] Ending point: led\[1\] / D The start point is clocked by top|clk [rising] on pin CLK The end point is clocked by top|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------- mimago_2_0_0 ROM DO[0] Out 0.317 0.317 - real2[0] Net - - 0.535 - 2 u_complex_mult.u_complex_mult.\\genblk2\.mult9x9_insth MULT9X9 B[0] In - 0.852 - u_complex_mult.u_complex_mult.\\genblk2\.mult9x9_insth MULT9X9 DOUT[17] Out 0.466 1.318 - h[17] Net - - 0.718 - 37 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq ALU54D B[17] In - 2.036 - u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq ALU54D DOUT[3] Out 0.466 2.502 - imago[3] Net - - 0.535 - 2 un1_imago_0_I_9_0_RNO_0 LUT2 I1 In - 3.037 - un1_imago_0_I_9_0_RNO_0 LUT2 F Out 0.570 3.607 - un1_imago_0_I_9_0_RNO_0 Net - - 0.535 - 1 un1_imago_0_I_9_0 ALU I0 In - 4.142 - un1_imago_0_I_9_0 ALU COUT Out 0.549 4.691 - un1_imago_0_data_tmp[1] Net - - 0.000 - 1 un1_imago_0_I_15_0 ALU CIN In - 4.691 - un1_imago_0_I_15_0 ALU COUT Out 0.035 4.726 - un1_imago_0_data_tmp[2] Net - - 0.000 - 1 un1_imago_0_I_21_0 ALU CIN In - 4.726 - un1_imago_0_I_21_0 ALU COUT Out 0.035 4.761 - un1_imago_0_data_tmp[3] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_8 ALU CIN In - 4.761 - un1_imago_0_I_57_0_RNO_8 ALU COUT Out 0.035 4.796 - un1_imago_0_I_27_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_7 ALU CIN In - 4.796 - un1_imago_0_I_57_0_RNO_7 ALU COUT Out 0.035 4.831 - un1_imago_0_data_tmp[4] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_6 ALU CIN In - 4.831 - un1_imago_0_I_57_0_RNO_6 ALU COUT Out 0.035 4.866 - un1_imago_0_I_33_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_5 ALU CIN In - 4.866 - un1_imago_0_I_57_0_RNO_5 ALU COUT Out 0.035 4.901 - un1_imago_0_data_tmp[5] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_4 ALU CIN In - 4.901 - un1_imago_0_I_57_0_RNO_4 ALU COUT Out 0.035 4.936 - un1_imago_0_I_39_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_3 ALU CIN In - 4.936 - un1_imago_0_I_57_0_RNO_3 ALU COUT Out 0.035 4.971 - un1_imago_0_data_tmp[6] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_2 ALU CIN In - 4.971 - un1_imago_0_I_57_0_RNO_2 ALU COUT Out 0.035 5.006 - un1_imago_0_I_45_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_1 ALU CIN In - 5.006 - un1_imago_0_I_57_0_RNO_1 ALU COUT Out 0.035 5.041 - un1_imago_0_data_tmp[7] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_0 ALU CIN In - 5.041 - un1_imago_0_I_57_0_RNO_0 ALU COUT Out 0.035 5.076 - un1_imago_0_I_51_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO ALU CIN In - 5.076 - un1_imago_0_I_57_0_RNO ALU COUT Out 0.035 5.111 - un1_imago_0_data_tmp[8] Net - - 0.000 - 1 un1_imago_0_I_57_0 ALU CIN In - 5.111 - un1_imago_0_I_57_0 ALU COUT Out 0.035 5.146 - un1_imago_0_I_57_0_COUT Net - - 0.961 - 1 led\[1\] DFFS D In - 6.107 - ============================================================================================================================ Total path delay (propagation time + setup) of 6.168 is 2.884(46.8%) logic and 3.284(53.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 5.243 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.182 - Propagation time: 6.107 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.925 Number of logic level(s): 17 Starting point: mimago_2_0_0 / DO[1] Ending point: led\[1\] / D The start point is clocked by top|clk [rising] on pin CLK The end point is clocked by top|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------- mimago_2_0_0 ROM DO[1] Out 0.317 0.317 - real2[1] Net - - 0.535 - 2 u_complex_mult.u_complex_mult.\\genblk2\.mult9x9_insth MULT9X9 B[1] In - 0.852 - u_complex_mult.u_complex_mult.\\genblk2\.mult9x9_insth MULT9X9 DOUT[17] Out 0.466 1.318 - h[17] Net - - 0.718 - 37 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq ALU54D B[17] In - 2.036 - u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq ALU54D DOUT[3] Out 0.466 2.502 - imago[3] Net - - 0.535 - 2 un1_imago_0_I_9_0_RNO_0 LUT2 I1 In - 3.037 - un1_imago_0_I_9_0_RNO_0 LUT2 F Out 0.570 3.607 - un1_imago_0_I_9_0_RNO_0 Net - - 0.535 - 1 un1_imago_0_I_9_0 ALU I0 In - 4.142 - un1_imago_0_I_9_0 ALU COUT Out 0.549 4.691 - un1_imago_0_data_tmp[1] Net - - 0.000 - 1 un1_imago_0_I_15_0 ALU CIN In - 4.691 - un1_imago_0_I_15_0 ALU COUT Out 0.035 4.726 - un1_imago_0_data_tmp[2] Net - - 0.000 - 1 un1_imago_0_I_21_0 ALU CIN In - 4.726 - un1_imago_0_I_21_0 ALU COUT Out 0.035 4.761 - un1_imago_0_data_tmp[3] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_8 ALU CIN In - 4.761 - un1_imago_0_I_57_0_RNO_8 ALU COUT Out 0.035 4.796 - un1_imago_0_I_27_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_7 ALU CIN In - 4.796 - un1_imago_0_I_57_0_RNO_7 ALU COUT Out 0.035 4.831 - un1_imago_0_data_tmp[4] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_6 ALU CIN In - 4.831 - un1_imago_0_I_57_0_RNO_6 ALU COUT Out 0.035 4.866 - un1_imago_0_I_33_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_5 ALU CIN In - 4.866 - un1_imago_0_I_57_0_RNO_5 ALU COUT Out 0.035 4.901 - un1_imago_0_data_tmp[5] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_4 ALU CIN In - 4.901 - un1_imago_0_I_57_0_RNO_4 ALU COUT Out 0.035 4.936 - un1_imago_0_I_39_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_3 ALU CIN In - 4.936 - un1_imago_0_I_57_0_RNO_3 ALU COUT Out 0.035 4.971 - un1_imago_0_data_tmp[6] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_2 ALU CIN In - 4.971 - un1_imago_0_I_57_0_RNO_2 ALU COUT Out 0.035 5.006 - un1_imago_0_I_45_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_1 ALU CIN In - 5.006 - un1_imago_0_I_57_0_RNO_1 ALU COUT Out 0.035 5.041 - un1_imago_0_data_tmp[7] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_0 ALU CIN In - 5.041 - un1_imago_0_I_57_0_RNO_0 ALU COUT Out 0.035 5.076 - un1_imago_0_I_51_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO ALU CIN In - 5.076 - un1_imago_0_I_57_0_RNO ALU COUT Out 0.035 5.111 - un1_imago_0_data_tmp[8] Net - - 0.000 - 1 un1_imago_0_I_57_0 ALU CIN In - 5.111 - un1_imago_0_I_57_0 ALU COUT Out 0.035 5.146 - un1_imago_0_I_57_0_COUT Net - - 0.961 - 1 led\[1\] DFFS D In - 6.107 - ============================================================================================================================ Total path delay (propagation time + setup) of 6.168 is 2.884(46.8%) logic and 3.284(53.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 5.243 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.182 - Propagation time: 6.107 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.925 Number of logic level(s): 17 Starting point: mimago_2_0_0 / DO[2] Ending point: led\[1\] / D The start point is clocked by top|clk [rising] on pin CLK The end point is clocked by top|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------- mimago_2_0_0 ROM DO[2] Out 0.317 0.317 - real2[2] Net - - 0.535 - 2 u_complex_mult.u_complex_mult.\\genblk2\.mult9x9_insth MULT9X9 B[2] In - 0.852 - u_complex_mult.u_complex_mult.\\genblk2\.mult9x9_insth MULT9X9 DOUT[17] Out 0.466 1.318 - h[17] Net - - 0.718 - 37 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq ALU54D B[17] In - 2.036 - u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq ALU54D DOUT[3] Out 0.466 2.502 - imago[3] Net - - 0.535 - 2 un1_imago_0_I_9_0_RNO_0 LUT2 I1 In - 3.037 - un1_imago_0_I_9_0_RNO_0 LUT2 F Out 0.570 3.607 - un1_imago_0_I_9_0_RNO_0 Net - - 0.535 - 1 un1_imago_0_I_9_0 ALU I0 In - 4.142 - un1_imago_0_I_9_0 ALU COUT Out 0.549 4.691 - un1_imago_0_data_tmp[1] Net - - 0.000 - 1 un1_imago_0_I_15_0 ALU CIN In - 4.691 - un1_imago_0_I_15_0 ALU COUT Out 0.035 4.726 - un1_imago_0_data_tmp[2] Net - - 0.000 - 1 un1_imago_0_I_21_0 ALU CIN In - 4.726 - un1_imago_0_I_21_0 ALU COUT Out 0.035 4.761 - un1_imago_0_data_tmp[3] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_8 ALU CIN In - 4.761 - un1_imago_0_I_57_0_RNO_8 ALU COUT Out 0.035 4.796 - un1_imago_0_I_27_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_7 ALU CIN In - 4.796 - un1_imago_0_I_57_0_RNO_7 ALU COUT Out 0.035 4.831 - un1_imago_0_data_tmp[4] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_6 ALU CIN In - 4.831 - un1_imago_0_I_57_0_RNO_6 ALU COUT Out 0.035 4.866 - un1_imago_0_I_33_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_5 ALU CIN In - 4.866 - un1_imago_0_I_57_0_RNO_5 ALU COUT Out 0.035 4.901 - un1_imago_0_data_tmp[5] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_4 ALU CIN In - 4.901 - un1_imago_0_I_57_0_RNO_4 ALU COUT Out 0.035 4.936 - un1_imago_0_I_39_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_3 ALU CIN In - 4.936 - un1_imago_0_I_57_0_RNO_3 ALU COUT Out 0.035 4.971 - un1_imago_0_data_tmp[6] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_2 ALU CIN In - 4.971 - un1_imago_0_I_57_0_RNO_2 ALU COUT Out 0.035 5.006 - un1_imago_0_I_45_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_1 ALU CIN In - 5.006 - un1_imago_0_I_57_0_RNO_1 ALU COUT Out 0.035 5.041 - un1_imago_0_data_tmp[7] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_0 ALU CIN In - 5.041 - un1_imago_0_I_57_0_RNO_0 ALU COUT Out 0.035 5.076 - un1_imago_0_I_51_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO ALU CIN In - 5.076 - un1_imago_0_I_57_0_RNO ALU COUT Out 0.035 5.111 - un1_imago_0_data_tmp[8] Net - - 0.000 - 1 un1_imago_0_I_57_0 ALU CIN In - 5.111 - un1_imago_0_I_57_0 ALU COUT Out 0.035 5.146 - un1_imago_0_I_57_0_COUT Net - - 0.961 - 1 led\[1\] DFFS D In - 6.107 - ============================================================================================================================ Total path delay (propagation time + setup) of 6.168 is 2.884(46.8%) logic and 3.284(53.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 5.243 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.182 - Propagation time: 6.107 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.925 Number of logic level(s): 17 Starting point: mimago_2_0_0 / DO[3] Ending point: led\[1\] / D The start point is clocked by top|clk [rising] on pin CLK The end point is clocked by top|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------- mimago_2_0_0 ROM DO[3] Out 0.317 0.317 - real2[3] Net - - 0.535 - 2 u_complex_mult.u_complex_mult.\\genblk2\.mult9x9_insth MULT9X9 B[3] In - 0.852 - u_complex_mult.u_complex_mult.\\genblk2\.mult9x9_insth MULT9X9 DOUT[17] Out 0.466 1.318 - h[17] Net - - 0.718 - 37 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq ALU54D B[17] In - 2.036 - u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq ALU54D DOUT[3] Out 0.466 2.502 - imago[3] Net - - 0.535 - 2 un1_imago_0_I_9_0_RNO_0 LUT2 I1 In - 3.037 - un1_imago_0_I_9_0_RNO_0 LUT2 F Out 0.570 3.607 - un1_imago_0_I_9_0_RNO_0 Net - - 0.535 - 1 un1_imago_0_I_9_0 ALU I0 In - 4.142 - un1_imago_0_I_9_0 ALU COUT Out 0.549 4.691 - un1_imago_0_data_tmp[1] Net - - 0.000 - 1 un1_imago_0_I_15_0 ALU CIN In - 4.691 - un1_imago_0_I_15_0 ALU COUT Out 0.035 4.726 - un1_imago_0_data_tmp[2] Net - - 0.000 - 1 un1_imago_0_I_21_0 ALU CIN In - 4.726 - un1_imago_0_I_21_0 ALU COUT Out 0.035 4.761 - un1_imago_0_data_tmp[3] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_8 ALU CIN In - 4.761 - un1_imago_0_I_57_0_RNO_8 ALU COUT Out 0.035 4.796 - un1_imago_0_I_27_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_7 ALU CIN In - 4.796 - un1_imago_0_I_57_0_RNO_7 ALU COUT Out 0.035 4.831 - un1_imago_0_data_tmp[4] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_6 ALU CIN In - 4.831 - un1_imago_0_I_57_0_RNO_6 ALU COUT Out 0.035 4.866 - un1_imago_0_I_33_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_5 ALU CIN In - 4.866 - un1_imago_0_I_57_0_RNO_5 ALU COUT Out 0.035 4.901 - un1_imago_0_data_tmp[5] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_4 ALU CIN In - 4.901 - un1_imago_0_I_57_0_RNO_4 ALU COUT Out 0.035 4.936 - un1_imago_0_I_39_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_3 ALU CIN In - 4.936 - un1_imago_0_I_57_0_RNO_3 ALU COUT Out 0.035 4.971 - un1_imago_0_data_tmp[6] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_2 ALU CIN In - 4.971 - un1_imago_0_I_57_0_RNO_2 ALU COUT Out 0.035 5.006 - un1_imago_0_I_45_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_1 ALU CIN In - 5.006 - un1_imago_0_I_57_0_RNO_1 ALU COUT Out 0.035 5.041 - un1_imago_0_data_tmp[7] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_0 ALU CIN In - 5.041 - un1_imago_0_I_57_0_RNO_0 ALU COUT Out 0.035 5.076 - un1_imago_0_I_51_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO ALU CIN In - 5.076 - un1_imago_0_I_57_0_RNO ALU COUT Out 0.035 5.111 - un1_imago_0_data_tmp[8] Net - - 0.000 - 1 un1_imago_0_I_57_0 ALU CIN In - 5.111 - un1_imago_0_I_57_0 ALU COUT Out 0.035 5.146 - un1_imago_0_I_57_0_COUT Net - - 0.961 - 1 led\[1\] DFFS D In - 6.107 - ============================================================================================================================ Total path delay (propagation time + setup) of 6.168 is 2.884(46.8%) logic and 3.284(53.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 5.243 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.182 - Propagation time: 6.107 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.925 Number of logic level(s): 17 Starting point: mimago_2_0_0 / DO[4] Ending point: led\[1\] / D The start point is clocked by top|clk [rising] on pin CLK The end point is clocked by top|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------- mimago_2_0_0 ROM DO[4] Out 0.317 0.317 - real2[4] Net - - 0.535 - 2 u_complex_mult.u_complex_mult.\\genblk2\.mult9x9_insth MULT9X9 B[4] In - 0.852 - u_complex_mult.u_complex_mult.\\genblk2\.mult9x9_insth MULT9X9 DOUT[17] Out 0.466 1.318 - h[17] Net - - 0.718 - 37 u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq ALU54D B[17] In - 2.036 - u_complex_mult.u_complex_mult.\\genblk2\.alu54d_instq ALU54D DOUT[3] Out 0.466 2.502 - imago[3] Net - - 0.535 - 2 un1_imago_0_I_9_0_RNO_0 LUT2 I1 In - 3.037 - un1_imago_0_I_9_0_RNO_0 LUT2 F Out 0.570 3.607 - un1_imago_0_I_9_0_RNO_0 Net - - 0.535 - 1 un1_imago_0_I_9_0 ALU I0 In - 4.142 - un1_imago_0_I_9_0 ALU COUT Out 0.549 4.691 - un1_imago_0_data_tmp[1] Net - - 0.000 - 1 un1_imago_0_I_15_0 ALU CIN In - 4.691 - un1_imago_0_I_15_0 ALU COUT Out 0.035 4.726 - un1_imago_0_data_tmp[2] Net - - 0.000 - 1 un1_imago_0_I_21_0 ALU CIN In - 4.726 - un1_imago_0_I_21_0 ALU COUT Out 0.035 4.761 - un1_imago_0_data_tmp[3] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_8 ALU CIN In - 4.761 - un1_imago_0_I_57_0_RNO_8 ALU COUT Out 0.035 4.796 - un1_imago_0_I_27_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_7 ALU CIN In - 4.796 - un1_imago_0_I_57_0_RNO_7 ALU COUT Out 0.035 4.831 - un1_imago_0_data_tmp[4] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_6 ALU CIN In - 4.831 - un1_imago_0_I_57_0_RNO_6 ALU COUT Out 0.035 4.866 - un1_imago_0_I_33_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_5 ALU CIN In - 4.866 - un1_imago_0_I_57_0_RNO_5 ALU COUT Out 0.035 4.901 - un1_imago_0_data_tmp[5] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_4 ALU CIN In - 4.901 - un1_imago_0_I_57_0_RNO_4 ALU COUT Out 0.035 4.936 - un1_imago_0_I_39_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_3 ALU CIN In - 4.936 - un1_imago_0_I_57_0_RNO_3 ALU COUT Out 0.035 4.971 - un1_imago_0_data_tmp[6] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_2 ALU CIN In - 4.971 - un1_imago_0_I_57_0_RNO_2 ALU COUT Out 0.035 5.006 - un1_imago_0_I_45_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_1 ALU CIN In - 5.006 - un1_imago_0_I_57_0_RNO_1 ALU COUT Out 0.035 5.041 - un1_imago_0_data_tmp[7] Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO_0 ALU CIN In - 5.041 - un1_imago_0_I_57_0_RNO_0 ALU COUT Out 0.035 5.076 - un1_imago_0_I_51_carry Net - - 0.000 - 1 un1_imago_0_I_57_0_RNO ALU CIN In - 5.076 - un1_imago_0_I_57_0_RNO ALU COUT Out 0.035 5.111 - un1_imago_0_data_tmp[8] Net - - 0.000 - 1 un1_imago_0_I_57_0 ALU CIN In - 5.111 - un1_imago_0_I_57_0 ALU COUT Out 0.035 5.146 - un1_imago_0_I_57_0_COUT Net - - 0.961 - 1 led\[1\] DFFS D In - 6.107 - ============================================================================================================================ Total path delay (propagation time + setup) of 6.168 is 2.884(46.8%) logic and 3.284(53.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:30s; Memory used current: 194MB peak: 195MB) Finished timing report (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:30s; Memory used current: 194MB peak: 195MB) --------------------------------------- Resource Usage Report for top Mapping to part: gw2a_55pbga484-8 Cell usage: ALU 44 uses ALU54D 2 uses DFFR 1 use DFFRE 12 uses DFFS 2 uses GSR 2 uses ROM 3 uses LUT2 5 uses LUT3 4 uses LUT4 3 uses MULT9X9 4 uses I/O ports: 85 I/O primitives: 85 IBUF 3 uses OBUF 82 uses I/O Register bits: 0 Register bits not including I/Os: 15 of 41040 (0%) RAM/ROM usage summary Block Rams : 3 of 140 (2%) Block Multipliers: 4 of 20 (20%) Total load per clock: top|clk: 24 @S |Mapping Summary: Total LUTs: 12 (0%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:32s; CPU Time elapsed 0h:00m:30s; Memory used current: 41MB peak: 195MB) Process took 0h:00m:32s realtime, 0h:00m:30s cputime # Fri Sep 28 13:59:01 2018 ###########################################################]