Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\impl\gwsynthesis\cmult_9.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\cmult_9.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\cmult_9.sdc
Tool Version	V1.9.11.02 (64-bit)
Part Number	GW5A-LV25UG324ES
Device	GW5A-25
Device Version	A
Created Time	Tue Jun 10 15:52:14 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C ES
Hold Delay Model	Fast 0.945V 85C ES
Numbers of Paths Analyzed	1493
Numbers of Endpoints Analyzed	2194
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk1	Base	20.000	50.000	0.000	10.000			clk
2	clk2	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk1	50.000(MHz)	85.704(MHz)	8	TOP
2	clk2	20.000(MHz)	149.574(MHz)	6	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk1	Setup	0.000	0
clk1	Hold	0.000	0
clk2	Setup	0.000	0
clk2	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	8.332	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_18_s0/D	clk1:[R]	clk1:[R]	20.000	-0.025	11.629
2	8.339	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_17_s0/D	clk1:[R]	clk1:[R]	20.000	-0.034	11.631
3	8.439	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_15_s0/D	clk1:[R]	clk1:[R]	20.000	-0.034	11.531
4	8.441	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_16_s0/D	clk1:[R]	clk1:[R]	20.000	-0.034	11.529
5	8.539	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_13_s0/D	clk1:[R]	clk1:[R]	20.000	-0.034	11.431
6	8.541	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_14_s0/D	clk1:[R]	clk1:[R]	20.000	-0.034	11.429
7	8.641	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_12_s0/D	clk1:[R]	clk1:[R]	20.000	-0.034	11.329
8	8.648	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_11_s0/D	clk1:[R]	clk1:[R]	20.000	-0.043	11.331
9	8.748	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_9_s0/D	clk1:[R]	clk1:[R]	20.000	-0.043	11.231
10	8.751	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_10_s0/D	clk1:[R]	clk1:[R]	20.000	-0.043	11.229
11	8.848	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_7_s0/D	clk1:[R]	clk1:[R]	20.000	-0.043	11.131
12	8.851	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_8_s0/D	clk1:[R]	clk1:[R]	20.000	-0.043	11.129
13	8.939	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_5_s0/D	clk1:[R]	clk1:[R]	20.000	-0.034	11.031
14	8.951	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_6_s0/D	clk1:[R]	clk1:[R]	20.000	-0.043	11.029
15	9.039	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_3_s0/D	clk1:[R]	clk1:[R]	20.000	-0.034	10.931
16	9.041	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_4_s0/D	clk1:[R]	clk1:[R]	20.000	-0.034	10.929
17	9.139	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_1_s0/D	clk1:[R]	clk1:[R]	20.000	-0.034	10.831
18	9.141	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_2_s0/D	clk1:[R]	clk1:[R]	20.000	-0.034	10.829
19	9.494	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/realo_0_s0/D	clk1:[R]	clk1:[R]	20.000	-0.034	10.476
20	9.842	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/imago_16_s10/D	clk1:[R]	clk1:[R]	20.000	-0.009	10.104
21	9.949	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/imago_16_s11/D	clk1:[R]	clk1:[R]	20.000	-0.009	9.996
22	10.002	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/imago_16_s16/D	clk1:[R]	clk1:[R]	20.000	-0.034	9.969
23	10.039	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/imago_16_s1/D	clk1:[R]	clk1:[R]	20.000	-0.009	9.906
24	10.041	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/imago_16_s6/D	clk1:[R]	clk1:[R]	20.000	0.002	9.893
25	10.081	memreal1_memreal1_0_0_s/DO[3]	u_complex_mult/comp_mult_inst/imago_16_s9/D	clk1:[R]	clk1:[R]	20.000	-0.009	9.865

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.189	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11]	clk1:[R]	clk1:[R]	0.000	-0.009	0.235
2	0.189	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[10]	clk1:[R]	clk1:[R]	0.000	-0.009	0.235
3	0.193	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8]	clk1:[R]	clk1:[R]	0.000	-0.005	0.235
4	0.197	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14]	clk1:[R]	clk1:[R]	0.000	-0.001	0.235
5	0.197	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[13]	clk1:[R]	clk1:[R]	0.000	-0.001	0.235
6	0.210	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5]	clk1:[R]	clk1:[R]	0.000	0.024	0.223
7	0.210	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]	clk1:[R]	clk1:[R]	0.000	0.024	0.223
8	0.210	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]	clk1:[R]	clk1:[R]	0.000	0.024	0.223
9	0.212	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[15]	clk1:[R]	clk1:[R]	0.000	-0.009	0.258
10	0.212	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[14]	clk1:[R]	clk1:[R]	0.000	-0.009	0.258
11	0.220	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[15]	clk1:[R]	clk1:[R]	0.000	-0.001	0.258
12	0.241	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_48_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[0]	clk1:[R]	clk1:[R]	0.000	-0.006	0.284
13	0.273	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_33_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[1]	clk1:[R]	clk1:[R]	0.000	0.024	0.286
14	0.273	ad_7_s0/Q	memrealo_memrealo_0_0_s/AD[12]	clk1:[R]	clk1:[R]	0.000	0.015	0.293
15	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.300
16	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.300
17	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.300
18	0.278	gw_gao_inst_0/u_la0_top/word_count_0_s0/Q	gw_gao_inst_0/u_la0_top/word_count_0_s0/D	clk2:[R]	clk2:[R]	0.000	0.000	0.303
19	0.278	gw_gao_inst_0/u_la0_top/word_count_11_s0/Q	gw_gao_inst_0/u_la0_top/word_count_11_s0/D	clk2:[R]	clk2:[R]	0.000	0.000	0.303
20	0.278	gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_7_s0/D	clk2:[R]	clk2:[R]	0.000	0.000	0.303
21	0.278	gw_gao_inst_0/u_la0_top/address_counter_8_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_8_s0/D	clk2:[R]	clk2:[R]	0.000	0.000	0.303
22	0.278	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.303
23	0.278	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.303
24	0.278	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.303
25	0.278	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.303

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	7.689	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.015	1.979
2	7.689	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.015	1.979
3	7.689	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.015	1.979
4	7.689	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.015	1.979
5	7.720	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.038	1.970
6	7.720	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.038	1.970
7	7.729	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk1:[F]	clk1:[R]	10.000	-0.047	1.970
8	7.938	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk1:[F]	clk1:[R]	10.000	-0.038	1.753
9	8.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.040	1.660
10	8.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.040	1.660
11	8.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.040	1.660
12	8.156	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.006	1.503
13	8.156	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.006	1.503
14	8.161	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.011	1.503
15	8.161	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.011	1.503
16	8.164	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	0.002	1.486
17	8.269	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.000	1.384
18	8.337	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.002	1.317
19	8.337	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.002	1.317
20	8.337	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.002	1.317
21	8.337	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.002	1.317
22	8.337	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.002	1.317
23	8.337	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.002	1.317
24	8.359	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.009	1.303
25	8.361	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.002	1.294

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	10.303	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.005	0.245
2	10.303	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.005	0.245
3	10.303	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.005	0.245
4	10.413	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.001	0.359
5	10.413	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.001	0.359
6	10.413	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.001	0.359
7	10.413	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.001	0.359
8	10.413	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.001	0.359
9	10.413	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.001	0.359
10	10.423	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.001	0.369
11	10.423	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.001	0.369
12	10.423	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.001	0.369
13	10.423	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.001	0.369
14	10.427	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.005	0.369
15	10.427	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.005	0.369
16	10.427	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.005	0.369
17	10.427	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.005	0.369
18	10.427	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.005	0.369
19	10.429	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.009	0.367
20	10.484	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.003	0.434
21	10.484	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.003	0.434
22	10.484	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.003	0.434
23	10.484	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.003	0.434
24	10.492	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.009	0.430
25	10.510	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.004	0.461

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	7.751	8.751	1.000	Low Pulse Width	clk1	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
2	7.751	8.751	1.000	Low Pulse Width	clk1	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
3	7.753	8.753	1.000	Low Pulse Width	clk1	memreal1_memreal1_0_0_s
4	7.753	8.753	1.000	Low Pulse Width	clk1	memrealo_memrealo_0_0_s
5	7.757	8.757	1.000	Low Pulse Width	clk1	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
6	7.757	8.757	1.000	Low Pulse Width	clk1	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
7	7.762	8.762	1.000	High Pulse Width	clk1	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
8	7.762	8.762	1.000	High Pulse Width	clk1	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
9	7.762	8.762	1.000	Low Pulse Width	clk1	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
10	7.763	8.763	1.000	High Pulse Width	clk1	memreal1_memreal1_0_0_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	8.332
Data Arrival Time	14.243
Data Required Time	22.575
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_18_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.399	0.050	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/COUT
13.399	0.000	tNET	RR	2	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/CIN
13.449	0.050	tINS	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/COUT
13.449	0.000	tNET	RR	2	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/CIN
13.499	0.050	tINS	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/COUT
13.499	0.000	tNET	RR	2	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/CIN
13.549	0.050	tINS	RR	1	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/COUT
13.549	0.000	tNET	RR	2	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/CIN
13.599	0.050	tINS	RR	1	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/COUT
13.599	0.000	tNET	RR	2	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/CIN
13.649	0.050	tINS	RR	1	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/COUT
13.649	0.000	tNET	RR	2	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/CIN
13.699	0.050	tINS	RR	1	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/COUT
13.699	0.000	tNET	RR	2	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/CIN
13.749	0.050	tINS	RR	1	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/COUT
13.749	0.000	tNET	RR	2	R20C50[0][B]	u_complex_mult/comp_mult_inst/n132_s/CIN
13.799	0.050	tINS	RR	1	R20C50[0][B]	u_complex_mult/comp_mult_inst/n132_s/COUT
13.799	0.000	tNET	RR	2	R20C50[1][A]	u_complex_mult/comp_mult_inst/n131_s/CIN
13.849	0.050	tINS	RR	1	R20C50[1][A]	u_complex_mult/comp_mult_inst/n131_s/COUT
13.849	0.000	tNET	RR	2	R20C50[1][B]	u_complex_mult/comp_mult_inst/n130_s/CIN
13.899	0.050	tINS	RR	1	R20C50[1][B]	u_complex_mult/comp_mult_inst/n130_s/COUT
13.899	0.000	tNET	RR	2	R20C50[2][A]	u_complex_mult/comp_mult_inst/n129_s/CIN
13.949	0.050	tINS	RR	1	R20C50[2][A]	u_complex_mult/comp_mult_inst/n129_s/COUT
13.949	0.000	tNET	RR	2	R20C50[2][B]	u_complex_mult/comp_mult_inst/n128_s/CIN
13.999	0.050	tINS	RR	1	R20C50[2][B]	u_complex_mult/comp_mult_inst/n128_s/COUT
13.999	0.000	tNET	RR	2	R20C51[0][A]	u_complex_mult/comp_mult_inst/n127_s/CIN
14.243	0.244	tINS	RR	1	R20C51[0][A]	u_complex_mult/comp_mult_inst/n127_s/SUM
14.243	0.000	tNET	RR	1	R20C51[0][A]	u_complex_mult/comp_mult_inst/realo_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.639	1.956	tNET	RR	1	R20C51[0][A]	u_complex_mult/comp_mult_inst/realo_18_s0/CLK
22.575	-0.064	tSu		1	R20C51[0][A]	u_complex_mult/comp_mult_inst/realo_18_s0

Path Statistics:

Clock Skew	0.025
Setup Relationship	20.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.731, 57.885%; route: 2.883, 24.787%; tC2Q: 2.015, 17.327%
Required Clock Path Delay	cell: 0.683, 25.865%; route: 1.956, 74.135%

Path2

Path Summary:

Slack	8.339
Data Arrival Time	14.245
Data Required Time	22.584
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_17_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.399	0.050	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/COUT
13.399	0.000	tNET	RR	2	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/CIN
13.449	0.050	tINS	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/COUT
13.449	0.000	tNET	RR	2	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/CIN
13.499	0.050	tINS	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/COUT
13.499	0.000	tNET	RR	2	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/CIN
13.549	0.050	tINS	RR	1	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/COUT
13.549	0.000	tNET	RR	2	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/CIN
13.599	0.050	tINS	RR	1	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/COUT
13.599	0.000	tNET	RR	2	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/CIN
13.649	0.050	tINS	RR	1	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/COUT
13.649	0.000	tNET	RR	2	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/CIN
13.699	0.050	tINS	RR	1	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/COUT
13.699	0.000	tNET	RR	2	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/CIN
13.749	0.050	tINS	RR	1	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/COUT
13.749	0.000	tNET	RR	2	R20C50[0][B]	u_complex_mult/comp_mult_inst/n132_s/CIN
13.799	0.050	tINS	RR	1	R20C50[0][B]	u_complex_mult/comp_mult_inst/n132_s/COUT
13.799	0.000	tNET	RR	2	R20C50[1][A]	u_complex_mult/comp_mult_inst/n131_s/CIN
13.849	0.050	tINS	RR	1	R20C50[1][A]	u_complex_mult/comp_mult_inst/n131_s/COUT
13.849	0.000	tNET	RR	2	R20C50[1][B]	u_complex_mult/comp_mult_inst/n130_s/CIN
13.899	0.050	tINS	RR	1	R20C50[1][B]	u_complex_mult/comp_mult_inst/n130_s/COUT
13.899	0.000	tNET	RR	2	R20C50[2][A]	u_complex_mult/comp_mult_inst/n129_s/CIN
13.949	0.050	tINS	RR	1	R20C50[2][A]	u_complex_mult/comp_mult_inst/n129_s/COUT
13.949	0.000	tNET	RR	2	R20C50[2][B]	u_complex_mult/comp_mult_inst/n128_s/CIN
14.245	0.296	tINS	RR	1	R20C50[2][B]	u_complex_mult/comp_mult_inst/n128_s/SUM
14.245	0.000	tNET	RR	1	R20C50[2][B]	u_complex_mult/comp_mult_inst/realo_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C50[2][B]	u_complex_mult/comp_mult_inst/realo_17_s0/CLK
22.584	-0.064	tSu		1	R20C50[2][B]	u_complex_mult/comp_mult_inst/realo_17_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	20.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.734, 57.894%; route: 2.883, 24.782%; tC2Q: 2.015, 17.324%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path3

Path Summary:

Slack	8.439
Data Arrival Time	14.145
Data Required Time	22.584
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_15_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.399	0.050	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/COUT
13.399	0.000	tNET	RR	2	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/CIN
13.449	0.050	tINS	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/COUT
13.449	0.000	tNET	RR	2	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/CIN
13.499	0.050	tINS	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/COUT
13.499	0.000	tNET	RR	2	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/CIN
13.549	0.050	tINS	RR	1	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/COUT
13.549	0.000	tNET	RR	2	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/CIN
13.599	0.050	tINS	RR	1	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/COUT
13.599	0.000	tNET	RR	2	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/CIN
13.649	0.050	tINS	RR	1	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/COUT
13.649	0.000	tNET	RR	2	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/CIN
13.699	0.050	tINS	RR	1	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/COUT
13.699	0.000	tNET	RR	2	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/CIN
13.749	0.050	tINS	RR	1	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/COUT
13.749	0.000	tNET	RR	2	R20C50[0][B]	u_complex_mult/comp_mult_inst/n132_s/CIN
13.799	0.050	tINS	RR	1	R20C50[0][B]	u_complex_mult/comp_mult_inst/n132_s/COUT
13.799	0.000	tNET	RR	2	R20C50[1][A]	u_complex_mult/comp_mult_inst/n131_s/CIN
13.849	0.050	tINS	RR	1	R20C50[1][A]	u_complex_mult/comp_mult_inst/n131_s/COUT
13.849	0.000	tNET	RR	2	R20C50[1][B]	u_complex_mult/comp_mult_inst/n130_s/CIN
14.145	0.296	tINS	RR	1	R20C50[1][B]	u_complex_mult/comp_mult_inst/n130_s/SUM
14.145	0.000	tNET	RR	1	R20C50[1][B]	u_complex_mult/comp_mult_inst/realo_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C50[1][B]	u_complex_mult/comp_mult_inst/realo_15_s0/CLK
22.584	-0.064	tSu		1	R20C50[1][B]	u_complex_mult/comp_mult_inst/realo_15_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	20.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.634, 57.529%; route: 2.883, 24.997%; tC2Q: 2.015, 17.474%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path4

Path Summary:

Slack	8.441
Data Arrival Time	14.143
Data Required Time	22.584
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_16_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.399	0.050	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/COUT
13.399	0.000	tNET	RR	2	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/CIN
13.449	0.050	tINS	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/COUT
13.449	0.000	tNET	RR	2	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/CIN
13.499	0.050	tINS	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/COUT
13.499	0.000	tNET	RR	2	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/CIN
13.549	0.050	tINS	RR	1	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/COUT
13.549	0.000	tNET	RR	2	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/CIN
13.599	0.050	tINS	RR	1	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/COUT
13.599	0.000	tNET	RR	2	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/CIN
13.649	0.050	tINS	RR	1	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/COUT
13.649	0.000	tNET	RR	2	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/CIN
13.699	0.050	tINS	RR	1	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/COUT
13.699	0.000	tNET	RR	2	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/CIN
13.749	0.050	tINS	RR	1	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/COUT
13.749	0.000	tNET	RR	2	R20C50[0][B]	u_complex_mult/comp_mult_inst/n132_s/CIN
13.799	0.050	tINS	RR	1	R20C50[0][B]	u_complex_mult/comp_mult_inst/n132_s/COUT
13.799	0.000	tNET	RR	2	R20C50[1][A]	u_complex_mult/comp_mult_inst/n131_s/CIN
13.849	0.050	tINS	RR	1	R20C50[1][A]	u_complex_mult/comp_mult_inst/n131_s/COUT
13.849	0.000	tNET	RR	2	R20C50[1][B]	u_complex_mult/comp_mult_inst/n130_s/CIN
13.899	0.050	tINS	RR	1	R20C50[1][B]	u_complex_mult/comp_mult_inst/n130_s/COUT
13.899	0.000	tNET	RR	2	R20C50[2][A]	u_complex_mult/comp_mult_inst/n129_s/CIN
14.143	0.244	tINS	RR	1	R20C50[2][A]	u_complex_mult/comp_mult_inst/n129_s/SUM
14.143	0.000	tNET	RR	1	R20C50[2][A]	u_complex_mult/comp_mult_inst/realo_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C50[2][A]	u_complex_mult/comp_mult_inst/realo_16_s0/CLK
22.584	-0.064	tSu		1	R20C50[2][A]	u_complex_mult/comp_mult_inst/realo_16_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	20.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.631, 57.520%; route: 2.883, 25.002%; tC2Q: 2.015, 17.478%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path5

Path Summary:

Slack	8.539
Data Arrival Time	14.045
Data Required Time	22.584
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_13_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.399	0.050	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/COUT
13.399	0.000	tNET	RR	2	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/CIN
13.449	0.050	tINS	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/COUT
13.449	0.000	tNET	RR	2	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/CIN
13.499	0.050	tINS	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/COUT
13.499	0.000	tNET	RR	2	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/CIN
13.549	0.050	tINS	RR	1	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/COUT
13.549	0.000	tNET	RR	2	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/CIN
13.599	0.050	tINS	RR	1	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/COUT
13.599	0.000	tNET	RR	2	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/CIN
13.649	0.050	tINS	RR	1	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/COUT
13.649	0.000	tNET	RR	2	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/CIN
13.699	0.050	tINS	RR	1	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/COUT
13.699	0.000	tNET	RR	2	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/CIN
13.749	0.050	tINS	RR	1	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/COUT
13.749	0.000	tNET	RR	2	R20C50[0][B]	u_complex_mult/comp_mult_inst/n132_s/CIN
14.045	0.296	tINS	RR	1	R20C50[0][B]	u_complex_mult/comp_mult_inst/n132_s/SUM
14.045	0.000	tNET	RR	1	R20C50[0][B]	u_complex_mult/comp_mult_inst/realo_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C50[0][B]	u_complex_mult/comp_mult_inst/realo_13_s0/CLK
22.584	-0.064	tSu		1	R20C50[0][B]	u_complex_mult/comp_mult_inst/realo_13_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	20.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.534, 57.158%; route: 2.883, 25.216%; tC2Q: 2.015, 17.627%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path6

Path Summary:

Slack	8.541
Data Arrival Time	14.043
Data Required Time	22.584
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_14_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.399	0.050	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/COUT
13.399	0.000	tNET	RR	2	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/CIN
13.449	0.050	tINS	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/COUT
13.449	0.000	tNET	RR	2	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/CIN
13.499	0.050	tINS	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/COUT
13.499	0.000	tNET	RR	2	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/CIN
13.549	0.050	tINS	RR	1	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/COUT
13.549	0.000	tNET	RR	2	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/CIN
13.599	0.050	tINS	RR	1	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/COUT
13.599	0.000	tNET	RR	2	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/CIN
13.649	0.050	tINS	RR	1	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/COUT
13.649	0.000	tNET	RR	2	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/CIN
13.699	0.050	tINS	RR	1	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/COUT
13.699	0.000	tNET	RR	2	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/CIN
13.749	0.050	tINS	RR	1	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/COUT
13.749	0.000	tNET	RR	2	R20C50[0][B]	u_complex_mult/comp_mult_inst/n132_s/CIN
13.799	0.050	tINS	RR	1	R20C50[0][B]	u_complex_mult/comp_mult_inst/n132_s/COUT
13.799	0.000	tNET	RR	2	R20C50[1][A]	u_complex_mult/comp_mult_inst/n131_s/CIN
14.043	0.244	tINS	RR	1	R20C50[1][A]	u_complex_mult/comp_mult_inst/n131_s/SUM
14.043	0.000	tNET	RR	1	R20C50[1][A]	u_complex_mult/comp_mult_inst/realo_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C50[1][A]	u_complex_mult/comp_mult_inst/realo_14_s0/CLK
22.584	-0.064	tSu		1	R20C50[1][A]	u_complex_mult/comp_mult_inst/realo_14_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	20.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.531, 57.148%; route: 2.883, 25.221%; tC2Q: 2.015, 17.631%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path7

Path Summary:

Slack	8.641
Data Arrival Time	13.943
Data Required Time	22.584
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_12_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.399	0.050	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/COUT
13.399	0.000	tNET	RR	2	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/CIN
13.449	0.050	tINS	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/COUT
13.449	0.000	tNET	RR	2	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/CIN
13.499	0.050	tINS	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/COUT
13.499	0.000	tNET	RR	2	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/CIN
13.549	0.050	tINS	RR	1	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/COUT
13.549	0.000	tNET	RR	2	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/CIN
13.599	0.050	tINS	RR	1	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/COUT
13.599	0.000	tNET	RR	2	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/CIN
13.649	0.050	tINS	RR	1	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/COUT
13.649	0.000	tNET	RR	2	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/CIN
13.699	0.050	tINS	RR	1	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/COUT
13.699	0.000	tNET	RR	2	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/CIN
13.943	0.244	tINS	RR	1	R20C50[0][A]	u_complex_mult/comp_mult_inst/n133_s/SUM
13.943	0.000	tNET	RR	1	R20C50[0][A]	u_complex_mult/comp_mult_inst/realo_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C50[0][A]	u_complex_mult/comp_mult_inst/realo_12_s0/CLK
22.584	-0.064	tSu		1	R20C50[0][A]	u_complex_mult/comp_mult_inst/realo_12_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	20.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.431, 56.770%; route: 2.883, 25.444%; tC2Q: 2.015, 17.786%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path8

Path Summary:

Slack	8.648
Data Arrival Time	13.945
Data Required Time	22.594
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_11_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.399	0.050	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/COUT
13.399	0.000	tNET	RR	2	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/CIN
13.449	0.050	tINS	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/COUT
13.449	0.000	tNET	RR	2	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/CIN
13.499	0.050	tINS	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/COUT
13.499	0.000	tNET	RR	2	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/CIN
13.549	0.050	tINS	RR	1	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/COUT
13.549	0.000	tNET	RR	2	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/CIN
13.599	0.050	tINS	RR	1	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/COUT
13.599	0.000	tNET	RR	2	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/CIN
13.649	0.050	tINS	RR	1	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/COUT
13.649	0.000	tNET	RR	2	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/CIN
13.945	0.296	tINS	RR	1	R20C49[2][B]	u_complex_mult/comp_mult_inst/n134_s/SUM
13.945	0.000	tNET	RR	1	R20C49[2][B]	u_complex_mult/comp_mult_inst/realo_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.657	1.975	tNET	RR	1	R20C49[2][B]	u_complex_mult/comp_mult_inst/realo_11_s0/CLK
22.594	-0.064	tSu		1	R20C49[2][B]	u_complex_mult/comp_mult_inst/realo_11_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.434, 56.779%; route: 2.883, 25.438%; tC2Q: 2.015, 17.782%
Required Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%

Path9

Path Summary:

Slack	8.748
Data Arrival Time	13.845
Data Required Time	22.594
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_9_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.399	0.050	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/COUT
13.399	0.000	tNET	RR	2	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/CIN
13.449	0.050	tINS	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/COUT
13.449	0.000	tNET	RR	2	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/CIN
13.499	0.050	tINS	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/COUT
13.499	0.000	tNET	RR	2	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/CIN
13.549	0.050	tINS	RR	1	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/COUT
13.549	0.000	tNET	RR	2	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/CIN
13.845	0.296	tINS	RR	1	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/SUM
13.845	0.000	tNET	RR	1	R20C49[1][B]	u_complex_mult/comp_mult_inst/realo_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.657	1.975	tNET	RR	1	R20C49[1][B]	u_complex_mult/comp_mult_inst/realo_9_s0/CLK
22.594	-0.064	tSu		1	R20C49[1][B]	u_complex_mult/comp_mult_inst/realo_9_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.334, 56.395%; route: 2.883, 25.665%; tC2Q: 2.015, 17.941%
Required Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%

Path10

Path Summary:

Slack	8.751
Data Arrival Time	13.843
Data Required Time	22.594
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_10_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.399	0.050	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/COUT
13.399	0.000	tNET	RR	2	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/CIN
13.449	0.050	tINS	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/COUT
13.449	0.000	tNET	RR	2	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/CIN
13.499	0.050	tINS	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/COUT
13.499	0.000	tNET	RR	2	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/CIN
13.549	0.050	tINS	RR	1	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/COUT
13.549	0.000	tNET	RR	2	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/CIN
13.599	0.050	tINS	RR	1	R20C49[1][B]	u_complex_mult/comp_mult_inst/n136_s/COUT
13.599	0.000	tNET	RR	2	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/CIN
13.843	0.244	tINS	RR	1	R20C49[2][A]	u_complex_mult/comp_mult_inst/n135_s/SUM
13.843	0.000	tNET	RR	1	R20C49[2][A]	u_complex_mult/comp_mult_inst/realo_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.657	1.975	tNET	RR	1	R20C49[2][A]	u_complex_mult/comp_mult_inst/realo_10_s0/CLK
22.594	-0.064	tSu		1	R20C49[2][A]	u_complex_mult/comp_mult_inst/realo_10_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.331, 56.385%; route: 2.883, 25.670%; tC2Q: 2.015, 17.945%
Required Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%

Path11

Path Summary:

Slack	8.848
Data Arrival Time	13.745
Data Required Time	22.594
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_7_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.399	0.050	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/COUT
13.399	0.000	tNET	RR	2	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/CIN
13.449	0.050	tINS	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/COUT
13.449	0.000	tNET	RR	2	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/CIN
13.745	0.296	tINS	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/SUM
13.745	0.000	tNET	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/realo_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.657	1.975	tNET	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/realo_7_s0/CLK
22.594	-0.064	tSu		1	R20C49[0][B]	u_complex_mult/comp_mult_inst/realo_7_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.234, 56.003%; route: 2.883, 25.895%; tC2Q: 2.015, 18.102%
Required Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%

Path12

Path Summary:

Slack	8.851
Data Arrival Time	13.743
Data Required Time	22.594
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_8_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.399	0.050	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/COUT
13.399	0.000	tNET	RR	2	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/CIN
13.449	0.050	tINS	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/COUT
13.449	0.000	tNET	RR	2	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/CIN
13.499	0.050	tINS	RR	1	R20C49[0][B]	u_complex_mult/comp_mult_inst/n138_s/COUT
13.499	0.000	tNET	RR	2	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/CIN
13.743	0.244	tINS	RR	1	R20C49[1][A]	u_complex_mult/comp_mult_inst/n137_s/SUM
13.743	0.000	tNET	RR	1	R20C49[1][A]	u_complex_mult/comp_mult_inst/realo_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.657	1.975	tNET	RR	1	R20C49[1][A]	u_complex_mult/comp_mult_inst/realo_8_s0/CLK
22.594	-0.064	tSu		1	R20C49[1][A]	u_complex_mult/comp_mult_inst/realo_8_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.231, 55.993%; route: 2.883, 25.901%; tC2Q: 2.015, 18.106%
Required Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%

Path13

Path Summary:

Slack	8.939
Data Arrival Time	13.645
Data Required Time	22.584
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_5_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.645	0.296	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/SUM
13.645	0.000	tNET	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/realo_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/realo_5_s0/CLK
22.584	-0.064	tSu		1	R20C48[2][B]	u_complex_mult/comp_mult_inst/realo_5_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.134, 55.604%; route: 2.883, 26.130%; tC2Q: 2.015, 18.266%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path14

Path Summary:

Slack	8.951
Data Arrival Time	13.643
Data Required Time	22.594
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_6_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.349	0.050	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/COUT
13.349	0.000	tNET	RR	2	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/CIN
13.399	0.050	tINS	RR	1	R20C48[2][B]	u_complex_mult/comp_mult_inst/n140_s/COUT
13.399	0.000	tNET	RR	2	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/CIN
13.643	0.244	tINS	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/n139_s/SUM
13.643	0.000	tNET	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/realo_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.657	1.975	tNET	RR	1	R20C49[0][A]	u_complex_mult/comp_mult_inst/realo_6_s0/CLK
22.594	-0.064	tSu		1	R20C49[0][A]	u_complex_mult/comp_mult_inst/realo_6_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.131, 55.594%; route: 2.883, 26.136%; tC2Q: 2.015, 18.270%
Required Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%

Path15

Path Summary:

Slack	9.039
Data Arrival Time	13.545
Data Required Time	22.584
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_3_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.545	0.296	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/SUM
13.545	0.000	tNET	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/realo_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/realo_3_s0/CLK
22.584	-0.064	tSu		1	R20C48[1][B]	u_complex_mult/comp_mult_inst/realo_3_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.034, 55.198%; route: 2.883, 26.369%; tC2Q: 2.015, 18.433%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path16

Path Summary:

Slack	9.041
Data Arrival Time	13.543
Data Required Time	22.584
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_4_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.249	0.050	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/COUT
13.249	0.000	tNET	RR	2	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/CIN
13.299	0.050	tINS	RR	1	R20C48[1][B]	u_complex_mult/comp_mult_inst/n142_s/COUT
13.299	0.000	tNET	RR	2	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/CIN
13.543	0.244	tINS	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/n141_s/SUM
13.543	0.000	tNET	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/realo_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C48[2][A]	u_complex_mult/comp_mult_inst/realo_4_s0/CLK
22.584	-0.064	tSu		1	R20C48[2][A]	u_complex_mult/comp_mult_inst/realo_4_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 6.031, 55.188%; route: 2.883, 26.375%; tC2Q: 2.015, 18.437%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path17

Path Summary:

Slack	9.139
Data Arrival Time	13.445
Data Required Time	22.584
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_1_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.445	0.296	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/SUM
13.445	0.000	tNET	RR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/realo_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/realo_1_s0/CLK
22.584	-0.064	tSu		1	R20C48[0][B]	u_complex_mult/comp_mult_inst/realo_1_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 5.934, 54.784%; route: 2.883, 26.612%; tC2Q: 2.015, 18.603%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path18

Path Summary:

Slack	9.141
Data Arrival Time	13.443
Data Required Time	22.584
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_2_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.149	0.556	tINS	RF	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/COUT
13.149	0.000	tNET	FF	2	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/CIN
13.199	0.050	tINS	FR	1	R20C48[0][B]	u_complex_mult/comp_mult_inst/n144_s/COUT
13.199	0.000	tNET	RR	2	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/CIN
13.443	0.244	tINS	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/n143_s/SUM
13.443	0.000	tNET	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/realo_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C48[1][A]	u_complex_mult/comp_mult_inst/realo_2_s0/CLK
22.584	-0.064	tSu		1	R20C48[1][A]	u_complex_mult/comp_mult_inst/realo_2_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 5.931, 54.774%; route: 2.883, 26.619%; tC2Q: 2.015, 18.608%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path19

Path Summary:

Slack	9.494
Data Arrival Time	13.090
Data Required Time	22.584
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/realo_0_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.593	0.875	tNET	RR	2	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/I0
13.090	0.498	tINS	RR	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/n145_s/SUM
13.090	0.000	tNET	RR	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/realo_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C48[0][A]	u_complex_mult/comp_mult_inst/realo_0_s0/CLK
22.584	-0.064	tSu		1	R20C48[0][A]	u_complex_mult/comp_mult_inst/realo_0_s0

Path Statistics:

Clock Skew	0.034
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 5.579, 53.252%; route: 2.883, 27.514%; tC2Q: 2.015, 19.234%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path20

Path Summary:

Slack	9.842
Data Arrival Time	12.718
Data Required Time	22.559
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/imago_16_s10
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.762	4.016	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[9]
12.718	0.956	tNET	RR	1	R18C49[1][B]	u_complex_mult/comp_mult_inst/imago_16_s10/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	R18C49[1][B]	u_complex_mult/comp_mult_inst/imago_16_s10/CLK
22.559	-0.064	tSu		1	R18C49[1][B]	u_complex_mult/comp_mult_inst/imago_16_s10

Path Statistics:

Clock Skew	0.009
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 5.125, 50.723%; route: 2.964, 29.333%; tC2Q: 2.015, 19.943%
Required Clock Path Delay	cell: 0.683, 26.019%; route: 1.941, 73.981%

Path21

Path Summary:

Slack	9.949
Data Arrival Time	12.610
Data Required Time	22.559
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/imago_16_s11
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.774	4.028	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[10]
12.610	0.836	tNET	RR	1	R18C49[3][A]	u_complex_mult/comp_mult_inst/imago_16_s11/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	R18C49[3][A]	u_complex_mult/comp_mult_inst/imago_16_s11/CLK
22.559	-0.064	tSu		1	R18C49[3][A]	u_complex_mult/comp_mult_inst/imago_16_s11

Path Statistics:

Clock Skew	0.009
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 5.137, 51.393%; route: 2.844, 28.449%; tC2Q: 2.015, 20.158%
Required Clock Path Delay	cell: 0.683, 26.019%; route: 1.941, 73.981%

Path22

Path Summary:

Slack	10.002
Data Arrival Time	12.583
Data Required Time	22.584
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/imago_16_s16
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.755	4.010	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[15]
12.583	0.827	tNET	RR	1	R20C52[0][A]	u_complex_mult/comp_mult_inst/imago_16_s16/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C52[0][A]	u_complex_mult/comp_mult_inst/imago_16_s16/CLK
22.584	-0.064	tSu		1	R20C52[0][A]	u_complex_mult/comp_mult_inst/imago_16_s16

Path Statistics:

Clock Skew	0.034
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 5.119, 51.347%; route: 2.835, 28.440%; tC2Q: 2.015, 20.214%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path23

Path Summary:

Slack	10.039
Data Arrival Time	12.520
Data Required Time	22.559
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/imago_16_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.718	3.973	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[0]
12.520	0.803	tNET	RR	1	R18C49[0][B]	u_complex_mult/comp_mult_inst/imago_16_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	R18C49[0][B]	u_complex_mult/comp_mult_inst/imago_16_s1/CLK
22.559	-0.064	tSu		1	R18C49[0][B]	u_complex_mult/comp_mult_inst/imago_16_s1

Path Statistics:

Clock Skew	0.009
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 5.081, 51.294%; route: 2.810, 28.365%; tC2Q: 2.015, 20.340%
Required Clock Path Delay	cell: 0.683, 26.019%; route: 1.941, 73.981%

Path24

Path Summary:

Slack	10.041
Data Arrival Time	12.507
Data Required Time	22.548
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/imago_16_s6
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.724	3.979	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[5]
12.507	0.782	tNET	RR	1	R17C50[2][B]	u_complex_mult/comp_mult_inst/imago_16_s6/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.612	1.929	tNET	RR	1	R17C50[2][B]	u_complex_mult/comp_mult_inst/imago_16_s6/CLK
22.548	-0.064	tSu		1	R17C50[2][B]	u_complex_mult/comp_mult_inst/imago_16_s6

Path Statistics:

Clock Skew	-0.002
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 5.088, 51.429%; route: 2.790, 28.203%; tC2Q: 2.015, 20.368%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path25

Path Summary:

Slack	10.081
Data Arrival Time	12.479
Data Required Time	22.559
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/imago_16_s9
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[15]	memreal1_memreal1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[15]	memreal1_memreal1_0_0_s/DO[3]
6.175	1.546	tNET	RR	2	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/I0
6.738	0.563	tINS	RF	1	R21C50[1][B]	u_complex_mult/comp_mult_inst/sum1_3_s/COUT
6.738	0.000	tNET	FF	2	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/CIN
6.788	0.050	tINS	FR	1	R21C50[2][A]	u_complex_mult/comp_mult_inst/sum1_4_s/COUT
6.788	0.000	tNET	RR	2	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/CIN
6.838	0.050	tINS	RR	1	R21C50[2][B]	u_complex_mult/comp_mult_inst/sum1_5_s/COUT
6.838	0.000	tNET	RR	2	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/CIN
6.888	0.050	tINS	RR	1	R21C51[0][A]	u_complex_mult/comp_mult_inst/sum1_6_s/COUT
6.888	0.000	tNET	RR	2	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/CIN
6.938	0.050	tINS	RR	1	R21C51[0][B]	u_complex_mult/comp_mult_inst/sum1_7_s/COUT
6.938	0.000	tNET	RR	2	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/CIN
6.988	0.050	tINS	RR	1	R21C51[1][A]	u_complex_mult/comp_mult_inst/sum1_8_s/COUT
6.988	0.000	tNET	RR	2	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/CIN
7.284	0.296	tINS	RR	3	R21C51[1][B]	u_complex_mult/comp_mult_inst/sum1_9_s/SUM
7.745	0.461	tNET	RR	24	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/B[11]
11.731	3.986	tINS	RR	2	DSP_R19[16][B]	u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[8]
12.479	0.747	tNET	RR	1	R18C49[0][A]	u_complex_mult/comp_mult_inst/imago_16_s9/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	R18C49[0][A]	u_complex_mult/comp_mult_inst/imago_16_s9/CLK
22.559	-0.064	tSu		1	R18C49[0][A]	u_complex_mult/comp_mult_inst/imago_16_s9

Path Statistics:

Clock Skew	0.009
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 5.095, 51.645%; route: 2.755, 27.928%; tC2Q: 2.015, 20.427%
Required Clock Path Delay	cell: 0.683, 26.019%; route: 1.941, 73.981%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.189
Data Arrival Time	1.604
Data Required Time	1.415
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/CLK
1.510	0.141	tC2Q	RF	1	R11C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q
1.604	0.094	tNET	FF	1	BSRAM_R10[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R10[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.415	0.037	tHld		1	BSRAM_R10[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path2

Path Summary:

Slack	0.189
Data Arrival Time	1.604
Data Required Time	1.415
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/CLK
1.510	0.141	tC2Q	RF	1	R11C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q
1.604	0.094	tNET	FF	1	BSRAM_R10[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R10[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.415	0.037	tHld		1	BSRAM_R10[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path3

Path Summary:

Slack	0.193
Data Arrival Time	1.604
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/CLK
1.510	0.141	tC2Q	RF	1	R11C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q
1.604	0.094	tNET	FF	1	BSRAM_R10[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R10[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.411	0.037	tHld		1	BSRAM_R10[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path4

Path Summary:

Slack	0.197
Data Arrival Time	1.609
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C57[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/CLK
1.515	0.141	tC2Q	RF	1	R11C57[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q
1.609	0.094	tNET	FF	1	BSRAM_R10[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R10[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.411	0.037	tHld		1	BSRAM_R10[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path5

Path Summary:

Slack	0.197
Data Arrival Time	1.609
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/CLK
1.515	0.141	tC2Q	RF	1	R11C57[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/Q
1.609	0.094	tNET	FF	1	BSRAM_R10[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R10[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.411	0.037	tHld		1	BSRAM_R10[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path6

Path Summary:

Slack	0.210
Data Arrival Time	1.617
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.394	0.719	tNET	RR	1	R20C59[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/CLK
1.535	0.141	tC2Q	RF	1	R20C59[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/Q
1.617	0.082	tNET	FF	1	BSRAM_R10[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R10[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.408	0.037	tHld		1	BSRAM_R10[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.024
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.449%; route: 0.719, 51.551%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.082, 36.771%; tC2Q: 0.141, 63.229%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path7

Path Summary:

Slack	0.210
Data Arrival Time	1.617
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.394	0.719	tNET	RR	1	R20C59[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/CLK
1.535	0.141	tC2Q	RF	1	R20C59[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/Q
1.617	0.082	tNET	FF	1	BSRAM_R10[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R10[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.408	0.037	tHld		1	BSRAM_R10[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.024
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.449%; route: 0.719, 51.551%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.082, 36.771%; tC2Q: 0.141, 63.229%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path8

Path Summary:

Slack	0.210
Data Arrival Time	1.617
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.394	0.719	tNET	RR	1	R20C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/CLK
1.535	0.141	tC2Q	RF	1	R20C59[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q
1.617	0.082	tNET	FF	1	BSRAM_R10[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R10[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.408	0.037	tHld		1	BSRAM_R10[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.024
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.449%; route: 0.719, 51.551%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.082, 36.771%; tC2Q: 0.141, 63.229%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path9

Path Summary:

Slack	0.212
Data Arrival Time	1.627
Data Required Time	1.415
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C54[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/CLK
1.510	0.141	tC2Q	RF	1	R11C54[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q
1.627	0.117	tNET	FF	1	BSRAM_R10[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R10[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.415	0.037	tHld		1	BSRAM_R10[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path10

Path Summary:

Slack	0.212
Data Arrival Time	1.627
Data Required Time	1.415
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/CLK
1.510	0.141	tC2Q	RF	1	R11C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q
1.627	0.117	tNET	FF	1	BSRAM_R10[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R10[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.415	0.037	tHld		1	BSRAM_R10[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path11

Path Summary:

Slack	0.220
Data Arrival Time	1.632
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0/CLK
1.515	0.141	tC2Q	RF	1	R11C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0/Q
1.632	0.117	tNET	FF	1	BSRAM_R10[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R10[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.411	0.037	tHld		1	BSRAM_R10[17]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path12

Path Summary:

Slack	0.241
Data Arrival Time	1.653
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_48_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C60[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_48_s0/CLK
1.513	0.144	tC2Q	RR	1	R14C60[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_48_s0/Q
1.653	0.140	tNET	RR	1	BSRAM_R10[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R10[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.411	0.037	tHld		1	BSRAM_R10[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.140, 49.296%; tC2Q: 0.144, 50.704%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path13

Path Summary:

Slack	0.273
Data Arrival Time	1.680
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_33_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.394	0.719	tNET	RR	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_33_s0/CLK
1.535	0.141	tC2Q	RF	1	R20C59[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_33_s0/Q
1.680	0.145	tNET	FF	1	BSRAM_R10[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R10[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.408	0.037	tHld		1	BSRAM_R10[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.024
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.449%; route: 0.719, 51.551%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.145, 50.699%; tC2Q: 0.141, 49.301%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path14

Path Summary:

Slack	0.273
Data Arrival Time	1.679
Data Required Time	1.406
From	ad_7_s0
To	memrealo_memrealo_0_0_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.385	0.710	tNET	RR	1	R25C51[3][A]	ad_7_s0/CLK
1.530	0.144	tC2Q	RR	6	R25C51[3][A]	ad_7_s0/Q
1.678	0.149	tNET	RR	1	BSRAM_R28[15]	memrealo_memrealo_0_0_s/AD[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[15]	memrealo_memrealo_0_0_s/CLK
1.406	0.035	tHld		1	BSRAM_R28[15]	memrealo_memrealo_0_0_s

Path Statistics:

Clock Skew	-0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.755%; route: 0.710, 51.245%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.149, 50.853%; tC2Q: 0.144, 49.147%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path15

Path Summary:

Slack	0.275
Data Arrival Time	1.673
Data Required Time	1.397
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R15C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.513	0.141	tC2Q	RF	9	R15C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
1.520	0.006	tNET	FF	1	R15C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n589_s1/I2
1.673	0.153	tINS	FF	1	R15C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n589_s1/F
1.673	0.000	tNET	FF	1	R15C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R15C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.397	0.025	tHld		1	R15C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path16

Path Summary:

Slack	0.275
Data Arrival Time	1.665
Data Required Time	1.390
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
1.506	0.141	tC2Q	RF	7	R13C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q
1.512	0.006	tNET	FF	1	R13C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n585_s2/I2
1.665	0.153	tINS	FF	1	R13C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n585_s2/F
1.665	0.000	tNET	FF	1	R13C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
1.390	0.025	tHld		1	R13C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path17

Path Summary:

Slack	0.275
Data Arrival Time	1.676
Data Required Time	1.401
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.376	0.701	tNET	RR	1	R18C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
1.517	0.141	tC2Q	RF	3	R18C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/Q
1.523	0.006	tNET	FF	1	R18C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n491_s0/I1
1.676	0.153	tINS	FF	1	R18C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n491_s0/F
1.676	0.000	tNET	FF	1	R18C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.376	0.701	tNET	RR	1	R18C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
1.401	0.025	tHld		1	R18C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.083%; route: 0.701, 50.917%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.083%; route: 0.701, 50.917%

Path18

Path Summary:

Slack	0.278
Data Arrival Time	2.733
Data Required Time	2.455
From	gw_gao_inst_0/u_la0_top/word_count_0_s0
To	gw_gao_inst_0/u_la0_top/word_count_0_s0
Launch Clk	clk2:[R]
Latch Clk	clk2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	350	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.430	1.079	tNET	RR	1	R24C55[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.571	0.141	tC2Q	RF	5	R24C55[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/Q
2.580	0.009	tNET	FF	1	R24C55[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/I1
2.733	0.153	tINS	FF	1	R24C55[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/F
2.733	0.000	tNET	FF	1	R24C55[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	350	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.430	1.079	tNET	RR	1	R24C55[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.455	0.025	tHld		1	R24C55[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.602%; route: 1.079, 44.398%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.602%; route: 1.079, 44.398%

Path19

Path Summary:

Slack	0.278
Data Arrival Time	2.733
Data Required Time	2.455
From	gw_gao_inst_0/u_la0_top/word_count_11_s0
To	gw_gao_inst_0/u_la0_top/word_count_11_s0
Launch Clk	clk2:[R]
Latch Clk	clk2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	350	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.430	1.079	tNET	RR	1	R24C57[1][A]	gw_gao_inst_0/u_la0_top/word_count_11_s0/CLK
2.571	0.141	tC2Q	RF	4	R24C57[1][A]	gw_gao_inst_0/u_la0_top/word_count_11_s0/Q
2.580	0.009	tNET	FF	1	R24C57[1][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_11_s0/I2
2.733	0.153	tINS	FF	1	R24C57[1][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_11_s0/F
2.733	0.000	tNET	FF	1	R24C57[1][A]	gw_gao_inst_0/u_la0_top/word_count_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	350	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.430	1.079	tNET	RR	1	R24C57[1][A]	gw_gao_inst_0/u_la0_top/word_count_11_s0/CLK
2.455	0.025	tHld		1	R24C57[1][A]	gw_gao_inst_0/u_la0_top/word_count_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.602%; route: 1.079, 44.398%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.602%; route: 1.079, 44.398%

Path20

Path Summary:

Slack	0.278
Data Arrival Time	2.734
Data Required Time	2.457
From	gw_gao_inst_0/u_la0_top/address_counter_7_s0
To	gw_gao_inst_0/u_la0_top/address_counter_7_s0
Launch Clk	clk2:[R]
Latch Clk	clk2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	350	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.431	1.081	tNET	RR	1	R23C63[0][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0/CLK
2.572	0.141	tC2Q	RF	8	R23C63[0][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q
2.582	0.009	tNET	FF	1	R23C63[0][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_7_s0/I1
2.734	0.153	tINS	FF	1	R23C63[0][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_7_s0/F
2.734	0.000	tNET	FF	1	R23C63[0][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	350	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.431	1.081	tNET	RR	1	R23C63[0][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0/CLK
2.457	0.025	tHld		1	R23C63[0][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.562%; route: 1.081, 44.438%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.562%; route: 1.081, 44.438%

Path21

Path Summary:

Slack	0.278
Data Arrival Time	2.734
Data Required Time	2.457
From	gw_gao_inst_0/u_la0_top/address_counter_8_s0
To	gw_gao_inst_0/u_la0_top/address_counter_8_s0
Launch Clk	clk2:[R]
Latch Clk	clk2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	350	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.431	1.081	tNET	RR	1	R23C63[1][A]	gw_gao_inst_0/u_la0_top/address_counter_8_s0/CLK
2.572	0.141	tC2Q	RF	7	R23C63[1][A]	gw_gao_inst_0/u_la0_top/address_counter_8_s0/Q
2.582	0.009	tNET	FF	1	R23C63[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_8_s0/I2
2.734	0.153	tINS	FF	1	R23C63[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_8_s0/F
2.734	0.000	tNET	FF	1	R23C63[1][A]	gw_gao_inst_0/u_la0_top/address_counter_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	350	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.431	1.081	tNET	RR	1	R23C63[1][A]	gw_gao_inst_0/u_la0_top/address_counter_8_s0/CLK
2.457	0.025	tHld		1	R23C63[1][A]	gw_gao_inst_0/u_la0_top/address_counter_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.562%; route: 1.081, 44.438%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.562%; route: 1.081, 44.438%

Path22

Path Summary:

Slack	0.278
Data Arrival Time	1.671
Data Required Time	1.393
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.510	0.141	tC2Q	RF	9	R14C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.518	0.009	tNET	FF	1	R14C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n587_s1/I1
1.671	0.153	tINS	FF	1	R14C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n587_s1/F
1.671	0.000	tNET	FF	1	R14C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.393	0.025	tHld		1	R14C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path23

Path Summary:

Slack	0.278
Data Arrival Time	1.679
Data Required Time	1.401
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.376	0.701	tNET	RR	1	R18C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
1.517	0.141	tC2Q	RF	3	R18C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/Q
1.526	0.009	tNET	FF	1	R18C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n493_s0/I2
1.679	0.153	tINS	FF	1	R18C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n493_s0/F
1.679	0.000	tNET	FF	1	R18C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.376	0.701	tNET	RR	1	R18C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
1.401	0.025	tHld		1	R18C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.083%; route: 0.701, 50.917%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 49.083%; route: 0.701, 50.917%

Path24

Path Summary:

Slack	0.278
Data Arrival Time	1.668
Data Required Time	1.390
From	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C52[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.506	0.141	tC2Q	RF	8	R13C52[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/Q
1.515	0.009	tNET	FF	1	R13C52[0][A]	gw_gao_inst_0/u_la0_top/n3185_s1/I0
1.668	0.153	tINS	FF	1	R13C52[0][A]	gw_gao_inst_0/u_la0_top/n3185_s1/F
1.668	0.000	tNET	FF	1	R13C52[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C52[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.390	0.025	tHld		1	R13C52[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path25

Path Summary:

Slack	0.278
Data Arrival Time	1.675
Data Required Time	1.397
From	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.513	0.141	tC2Q	RF	6	R14C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q
1.522	0.009	tNET	FF	1	R14C53[0][A]	gw_gao_inst_0/u_la0_top/n3184_s1/I2
1.675	0.153	tINS	FF	1	R14C53[0][A]	gw_gao_inst_0/u_la0_top/n3184_s1/F
1.675	0.000	tNET	FF	1	R14C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.397	0.025	tHld		1	R14C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	7.689
Data Arrival Time	14.587
Data Required Time	22.276
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.587	1.536	tNET	FF	1	R18C57[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	R18C57[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
22.276	-0.347	tSu		1	R18C57[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	0.015
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.536, 77.637%; tC2Q: 0.442, 22.363%
Required Clock Path Delay	cell: 0.683, 26.019%; route: 1.941, 73.981%

Path2

Path Summary:

Slack	7.689
Data Arrival Time	14.587
Data Required Time	22.276
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.587	1.536	tNET	FF	1	R18C57[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	R18C57[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
22.276	-0.347	tSu		1	R18C57[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	0.015
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.536, 77.637%; tC2Q: 0.442, 22.363%
Required Clock Path Delay	cell: 0.683, 26.019%; route: 1.941, 73.981%

Path3

Path Summary:

Slack	7.689
Data Arrival Time	14.587
Data Required Time	22.276
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.587	1.536	tNET	FF	1	R18C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	R18C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
22.276	-0.347	tSu		1	R18C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	0.015
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.536, 77.637%; tC2Q: 0.442, 22.363%
Required Clock Path Delay	cell: 0.683, 26.019%; route: 1.941, 73.981%

Path4

Path Summary:

Slack	7.689
Data Arrival Time	14.587
Data Required Time	22.276
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.587	1.536	tNET	FF	1	R18C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	R18C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
22.276	-0.347	tSu		1	R18C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	0.015
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.536, 77.637%; tC2Q: 0.442, 22.363%
Required Clock Path Delay	cell: 0.683, 26.019%; route: 1.941, 73.981%

Path5

Path Summary:

Slack	7.720
Data Arrival Time	14.578
Data Required Time	22.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.578	1.528	tNET	FF	1	R21C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.646	1.963	tNET	RR	1	R21C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
22.298	-0.347	tSu		1	R21C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.038
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.528, 77.538%; tC2Q: 0.442, 22.462%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path6

Path Summary:

Slack	7.720
Data Arrival Time	14.578
Data Required Time	22.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.578	1.528	tNET	FF	1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.646	1.963	tNET	RR	1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
22.298	-0.347	tSu		1	R21C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	0.038
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.528, 77.538%; tC2Q: 0.442, 22.462%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path7

Path Summary:

Slack	7.729
Data Arrival Time	14.578
Data Required Time	22.307
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.578	1.528	tNET	FF	1	R21C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.655	1.972	tNET	RR	1	R21C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
22.308	-0.347	tSu		1	R21C57[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	0.047
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.528, 77.538%; tC2Q: 0.442, 22.462%
Required Clock Path Delay	cell: 0.683, 25.706%; route: 1.972, 74.294%

Path8

Path Summary:

Slack	7.938
Data Arrival Time	14.361
Data Required Time	22.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.361	1.310	tNET	FF	1	R21C54[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.646	1.963	tNET	RR	1	R21C54[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
22.298	-0.347	tSu		1	R21C54[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	0.038
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.310, 74.750%; tC2Q: 0.442, 25.250%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path9

Path Summary:

Slack	8.033
Data Arrival Time	14.268
Data Required Time	22.301
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.268	1.217	tNET	FF	1	R20C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
22.301	-0.347	tSu		1	R20C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.040
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.217, 73.343%; tC2Q: 0.442, 26.657%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path10

Path Summary:

Slack	8.033
Data Arrival Time	14.268
Data Required Time	22.301
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.268	1.217	tNET	FF	1	R20C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
22.301	-0.347	tSu		1	R20C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	0.040
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.217, 73.343%; tC2Q: 0.442, 26.657%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path11

Path Summary:

Slack	8.033
Data Arrival Time	14.268
Data Required Time	22.301
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.268	1.217	tNET	FF	1	R20C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
22.301	-0.347	tSu		1	R20C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	0.040
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.217, 73.343%; tC2Q: 0.442, 26.657%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path12

Path Summary:

Slack	8.156
Data Arrival Time	14.111
Data Required Time	22.266
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.111	1.060	tNET	FF	1	R18C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.614	1.931	tNET	RR	1	R18C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
22.266	-0.347	tSu		1	R18C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.060, 70.549%; tC2Q: 0.442, 29.451%
Required Clock Path Delay	cell: 0.683, 26.112%; route: 1.931, 73.888%

Path13

Path Summary:

Slack	8.156
Data Arrival Time	14.111
Data Required Time	22.266
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.111	1.060	tNET	FF	1	R18C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.614	1.931	tNET	RR	1	R18C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
22.266	-0.347	tSu		1	R18C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.060, 70.549%; tC2Q: 0.442, 29.451%
Required Clock Path Delay	cell: 0.683, 26.112%; route: 1.931, 73.888%

Path14

Path Summary:

Slack	8.161
Data Arrival Time	14.111
Data Required Time	22.272
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.111	1.060	tNET	FF	1	R16C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.619	1.937	tNET	RR	1	R16C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
22.272	-0.347	tSu		1	R16C57[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.060, 70.549%; tC2Q: 0.442, 29.451%
Required Clock Path Delay	cell: 0.683, 26.056%; route: 1.937, 73.944%

Path15

Path Summary:

Slack	8.161
Data Arrival Time	14.111
Data Required Time	22.272
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.111	1.060	tNET	FF	1	R16C57[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.619	1.937	tNET	RR	1	R16C57[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
22.272	-0.347	tSu		1	R16C57[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.060, 70.549%; tC2Q: 0.442, 29.451%
Required Clock Path Delay	cell: 0.683, 26.056%; route: 1.937, 73.944%

Path16

Path Summary:

Slack	8.164
Data Arrival Time	14.094
Data Required Time	22.258
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.094	1.044	tNET	FF	1	R13C57[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.606	1.923	tNET	RR	1	R13C57[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
22.258	-0.347	tSu		1	R13C57[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.044, 70.227%; tC2Q: 0.442, 29.773%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path17

Path Summary:

Slack	8.269
Data Arrival Time	13.992
Data Required Time	22.261
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.992	0.941	tNET	FF	1	R15C52[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.608	1.926	tNET	RR	1	R15C52[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLK
22.261	-0.347	tSu		1	R15C52[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.941, 68.022%; tC2Q: 0.442, 31.978%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path18

Path Summary:

Slack	8.337
Data Arrival Time	13.926
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.926	0.875	tNET	FF	1	R16C52[3][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R16C52[3][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
22.263	-0.347	tSu		1	R16C52[3][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.875, 66.414%; tC2Q: 0.442, 33.586%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path19

Path Summary:

Slack	8.337
Data Arrival Time	13.926
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.926	0.875	tNET	FF	1	R16C52[1][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R16C52[1][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
22.263	-0.347	tSu		1	R16C52[1][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.875, 66.414%; tC2Q: 0.442, 33.586%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path20

Path Summary:

Slack	8.337
Data Arrival Time	13.926
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.926	0.875	tNET	FF	1	R16C52[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R16C52[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
22.263	-0.347	tSu		1	R16C52[0][A]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.875, 66.414%; tC2Q: 0.442, 33.586%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path21

Path Summary:

Slack	8.337
Data Arrival Time	13.926
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.926	0.875	tNET	FF	1	R16C52[0][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R16C52[0][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
22.263	-0.347	tSu		1	R16C52[0][B]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.875, 66.414%; tC2Q: 0.442, 33.586%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path22

Path Summary:

Slack	8.337
Data Arrival Time	13.926
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.926	0.875	tNET	FF	1	R16C52[3][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R16C52[3][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
22.263	-0.347	tSu		1	R16C52[3][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.875, 66.414%; tC2Q: 0.442, 33.586%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path23

Path Summary:

Slack	8.337
Data Arrival Time	13.926
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.926	0.875	tNET	FF	1	R16C52[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R16C52[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
22.263	-0.347	tSu		1	R16C52[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.875, 66.414%; tC2Q: 0.442, 33.586%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path24

Path Summary:

Slack	8.359
Data Arrival Time	13.911
Data Required Time	22.270
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.911	0.860	tNET	FF	1	R15C57[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.618	1.935	tNET	RR	1	R15C57[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
22.270	-0.347	tSu		1	R15C57[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	0.009
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.860, 66.027%; tC2Q: 0.442, 33.973%
Required Clock Path Delay	cell: 0.683, 26.074%; route: 1.935, 73.925%

Path25

Path Summary:

Slack	8.361
Data Arrival Time	13.902
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	286	IOB29[A]	clk_ibuf/O
12.608	1.921	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.051	0.442	tC2Q	FF	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.902	0.851	tNET	FF	1	R16C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	286	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R16C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
22.263	-0.347	tSu		1	R16C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.360%; route: 1.921, 73.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.851, 65.797%; tC2Q: 0.442, 34.203%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	10.303
Data Arrival Time	11.618
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.618	0.087	tNET	RR	1	R13C53[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R13C53[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
1.316	-0.053	tHld		1	R13C53[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.087, 35.510%; tC2Q: 0.158, 64.490%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path2

Path Summary:

Slack	10.303
Data Arrival Time	11.618
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.618	0.087	tNET	RR	1	R13C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R13C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
1.316	-0.053	tHld		1	R13C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.087, 35.510%; tC2Q: 0.158, 64.490%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path3

Path Summary:

Slack	10.303
Data Arrival Time	11.618
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.618	0.087	tNET	RR	1	R13C53[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R13C53[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
1.316	-0.053	tHld		1	R13C53[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.087, 35.510%; tC2Q: 0.158, 64.490%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path4

Path Summary:

Slack	10.413
Data Arrival Time	11.733
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.733	0.201	tNET	RR	1	R14C53[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C53[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.319	-0.053	tHld		1	R14C53[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path5

Path Summary:

Slack	10.413
Data Arrival Time	11.733
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.733	0.201	tNET	RR	1	R14C53[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C53[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
1.319	-0.053	tHld		1	R14C53[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path6

Path Summary:

Slack	10.413
Data Arrival Time	11.733
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.733	0.201	tNET	RR	1	R14C53[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C53[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
1.319	-0.053	tHld		1	R14C53[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path7

Path Summary:

Slack	10.413
Data Arrival Time	11.733
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.733	0.201	tNET	RR	1	R14C53[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C53[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.319	-0.053	tHld		1	R14C53[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	-0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path8

Path Summary:

Slack	10.413
Data Arrival Time	11.733
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.733	0.201	tNET	RR	1	R14C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.319	-0.053	tHld		1	R14C53[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	-0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path9

Path Summary:

Slack	10.413
Data Arrival Time	11.733
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.733	0.201	tNET	RR	1	R14C53[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R14C53[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
1.319	-0.053	tHld		1	R14C53[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	-0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path10

Path Summary:

Slack	10.423
Data Arrival Time	11.743
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.743	0.211	tNET	RR	1	R15C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R15C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
1.319	-0.053	tHld		1	R15C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.211, 57.182%; tC2Q: 0.158, 42.818%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path11

Path Summary:

Slack	10.423
Data Arrival Time	11.743
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.743	0.211	tNET	RR	1	R15C54[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R15C54[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
1.319	-0.053	tHld		1	R15C54[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew	-0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.211, 57.182%; tC2Q: 0.158, 42.818%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path12

Path Summary:

Slack	10.423
Data Arrival Time	11.743
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.743	0.211	tNET	RR	1	R15C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R15C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLK
1.319	-0.053	tHld		1	R15C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0

Path Statistics:

Clock Skew	-0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.211, 57.182%; tC2Q: 0.158, 42.818%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path13

Path Summary:

Slack	10.423
Data Arrival Time	11.743
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.743	0.211	tNET	RR	1	R15C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R15C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLK
1.319	-0.053	tHld		1	R15C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0

Path Statistics:

Clock Skew	-0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.211, 57.182%; tC2Q: 0.158, 42.818%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path14

Path Summary:

Slack	10.427
Data Arrival Time	11.743
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.743	0.211	tNET	RR	1	R14C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLK
1.316	-0.053	tHld		1	R14C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.211, 57.182%; tC2Q: 0.158, 42.818%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path15

Path Summary:

Slack	10.427
Data Arrival Time	11.743
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.743	0.211	tNET	RR	1	R14C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLK
1.316	-0.053	tHld		1	R14C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.211, 57.182%; tC2Q: 0.158, 42.818%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path16

Path Summary:

Slack	10.427
Data Arrival Time	11.743
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.743	0.211	tNET	RR	1	R14C54[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C54[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0/CLK
1.316	-0.053	tHld		1	R14C54[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.211, 57.182%; tC2Q: 0.158, 42.818%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path17

Path Summary:

Slack	10.427
Data Arrival Time	11.743
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.743	0.211	tNET	RR	1	R14C54[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C54[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLK
1.316	-0.053	tHld		1	R14C54[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.211, 57.182%; tC2Q: 0.158, 42.818%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path18

Path Summary:

Slack	10.427
Data Arrival Time	11.743
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.743	0.211	tNET	RR	1	R14C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLK
1.316	-0.053	tHld		1	R14C54[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.211, 57.182%; tC2Q: 0.158, 42.818%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path19

Path Summary:

Slack	10.429
Data Arrival Time	11.740
Data Required Time	1.312
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.740	0.209	tNET	RR	1	R13C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
1.312	-0.053	tHld		1	R13C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path20

Path Summary:

Slack	10.484
Data Arrival Time	11.807
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.807	0.276	tNET	RR	1	R15C53[3][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.377	0.701	tNET	RR	1	R15C53[3][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
1.324	-0.053	tHld		1	R15C53[3][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.276, 63.594%; tC2Q: 0.158, 36.406%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path21

Path Summary:

Slack	10.484
Data Arrival Time	11.807
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.807	0.276	tNET	RR	1	R15C53[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.377	0.701	tNET	RR	1	R15C53[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK
1.324	-0.053	tHld		1	R15C53[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.276, 63.594%; tC2Q: 0.158, 36.406%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path22

Path Summary:

Slack	10.484
Data Arrival Time	11.807
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.807	0.276	tNET	RR	1	R15C53[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.377	0.701	tNET	RR	1	R15C53[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
1.324	-0.053	tHld		1	R15C53[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.276, 63.594%; tC2Q: 0.158, 36.406%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path23

Path Summary:

Slack	10.484
Data Arrival Time	11.807
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.807	0.276	tNET	RR	1	R15C53[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.377	0.701	tNET	RR	1	R15C53[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
1.324	-0.053	tHld		1	R15C53[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.276, 63.594%; tC2Q: 0.158, 36.406%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path24

Path Summary:

Slack	10.492
Data Arrival Time	11.804
Data Required Time	1.312
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.804	0.272	tNET	RR	1	R13C52[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C52[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.312	-0.053	tHld		1	R13C52[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 63.256%; tC2Q: 0.158, 36.744%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path25

Path Summary:

Slack	10.510
Data Arrival Time	11.834
Data Required Time	1.325
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	286	IOB29[A]	clk_ibuf/O
11.373	0.696	tNET	FF	1	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	69	R13C53[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.834	0.303	tNET	RR	1	R16C53[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	286	IOB29[A]	clk_ibuf/O
1.378	0.702	tNET	RR	1	R16C53[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
1.325	-0.053	tHld		1	R16C53[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.303, 65.727%; tC2Q: 0.158, 34.273%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk1
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk1
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW2

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk1
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk1
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA

MPW3

MPW Summary:

Slack:	7.753
Actual Width:	8.753
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk1
Objects:	memreal1_memreal1_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.618	1.930	tNET	FF	memreal1_memreal1_0_0_s/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk1
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.371	0.695	tNET	RR	memreal1_memreal1_0_0_s/CLK

MPW4

MPW Summary:

Slack:	7.753
Actual Width:	8.753
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk1
Objects:	memrealo_memrealo_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.618	1.930	tNET	FF	memrealo_memrealo_0_0_s/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk1
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.371	0.695	tNET	RR	memrealo_memrealo_0_0_s/CLK

MPW5

MPW Summary:

Slack:	7.757
Actual Width:	8.757
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk1
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.618	1.930	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk1
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.375	0.699	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

MPW6

MPW Summary:

Slack:	7.757
Actual Width:	8.757
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk1
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.618	1.930	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk1
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.375	0.699	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW7

MPW Summary:

Slack:	7.762
Actual Width:	8.762
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk1
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk1
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.623	1.941	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.385	0.708	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA

MPW8

MPW Summary:

Slack:	7.762
Actual Width:	8.762
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk1
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk1
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.623	1.941	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.385	0.708	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW9

MPW Summary:

Slack:	7.762
Actual Width:	8.762
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk1
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.608	1.921	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk1
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.371	0.695	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

MPW10

MPW Summary:

Slack:	7.763
Actual Width:	8.763
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk1
Objects:	memreal1_memreal1_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk1
0.000	0.000	tCL	RR	clk_ibuf/I
0.683	0.683	tINS	RR	clk_ibuf/O
2.614	1.932	tNET	RR	memreal1_memreal1_0_0_s/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk1
10.000	0.000	tCL	FF	clk_ibuf/I
10.677	0.678	tINS	FF	clk_ibuf/O
11.377	0.700	tNET	FF	memreal1_memreal1_0_0_s/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
350	gw_gao_inst_0/control0[0]	43.314	2.733
286	clk_d	8.332	1.975
98	gw_gao_inst_0/u_la0_top/n20_3	46.226	1.760
78	gw_gao_inst_0/u_la0_top/data_out_shift_reg_75_7	45.234	1.423
77	gw_gao_inst_0/u_la0_top/n907_5	44.845	1.531
69	gw_gao_inst_0/u_la0_top/rst_ao	7.689	1.536
61	gw_gao_inst_0/u_la0_top/n907_11	45.048	1.322
39	gw_gao_inst_0/u_la0_top/module_state[1]	43.636	1.636
36	gw_gao_inst_0/u_la0_top/crc_30_9	44.113	0.861
35	gw_gao_inst_0/u_la0_top/module_state[2]	43.642	1.541

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C6	100.00%
R2C8	100.00%
R2C9	100.00%
R2C25	100.00%
R2C57	100.00%
R3C30	100.00%
R4C68	100.00%
R7C54	100.00%
R13C89	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk1 -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name clk2 -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clk1}] -group [get_clocks {clk2}]