Power Messages

Report Title Power Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\impl\gwsynthesis\cmult_9.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\cmult_9.cst
Timing Constraints File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\cmult_9.sdc
Tool Version V1.9.11.02 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Jun 10 15:52:14 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade Commercial
Process Typical
Ambient Temperature 25.000
Use Custom Theta JA false
Heat Sink None
Air Flow LFM_0
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Related Vcd File
Related Saif File
Filter Glitches false
Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125

Power Summary

Power Information:

Total Power (mW) 71.213
Quiescent Power (mW) 53.534
Dynamic Power (mW) 17.679

Thermal Information:

Junction Temperature 26.951
Theta JA 27.400
Max Allowed Ambient Temperature 83.049

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 0.900 12.484 30.022 38.256
VCCX 3.300 0.976 3.000 13.122
VCCIO33 3.300 0.976 1.035 6.636
VCCLDO 3.300 0.000 4.000 13.200

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 0.202 NA 4.032
IO 19.391 12.072 7.636
BSRAM 9.961 NA NA
DSP 0.197 NA 0.005

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW)
top 10.361 10.361(9.793)
top/gw_gao_inst_0/ 9.499 9.499(9.499)
top/gw_gao_inst_0/u_icon_top/ 0.002 0.002(0.000)
top/gw_gao_inst_0/u_la0_top/ 9.497 9.497(9.451)
top/gw_gao_inst_0/u_la0_top/u_ao_crc32/ 0.004 0.004(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_match_0/ 0.004 0.004(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/ 9.442 9.442(0.000)
top/u_complex_mult/ 0.294 0.294(0.294)
top/u_complex_mult/comp_mult_inst/ 0.294 0.294(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
clk1 50.000 7.626
clk2 20.000 2.734
NO CLOCK DOMAIN 0.000 0.000