Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\gw_jtag.v
C:\Users\vito\Desktop\comp_mult_update\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue May 27 17:58:16 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.406s, Peak memory usage = 65.352MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 65.352MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 65.352MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 65.352MB
    Optimizing Phase 2: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.185s, Peak memory usage = 65.352MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 65.352MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 65.352MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 65.352MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 65.352MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 65.352MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.095s, Peak memory usage = 65.352MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 65.352MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 90.672MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 90.672MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 90.672MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 90.672MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 73
I/O Buf 73
    IBUF 72
    OBUF 1
Register 504
    DFFRE 1
    DFFPE 36
    DFFCE 467
LUT 479
    LUT2 50
    LUT3 114
    LUT4 315
MUX 1
    MUX16 1
ALU 13
    ALU 13
INV 4
    INV 4
BSRAM 4
    SDPB 4
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 504(491 LUT, 13 ALU) / 23040 3%
Register 504 / 23682 3%
  --Register as Latch 0 / 23682 0%
  --Register as FF 504 / 23682 3%
BSRAM 4 / 56 8%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 214.420(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.336
Data Arrival Time 4.727
Data Required Time 10.064
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 198 clk_ibuf/O
0.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
0.757 0.382 tC2Q RR 8 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.132 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n500_s9/I0
1.659 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n500_s9/F
2.034 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n500_s6/I0
2.560 0.526 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n500_s6/F
2.935 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n500_s4/I1
3.451 0.516 tINS RR 10 u_la0_top/u_ao_mem_ctrl/n500_s4/F
3.826 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
4.352 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
4.727 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 198 clk_ibuf/O
10.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.064 -0.311 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 5.456
Data Arrival Time 4.608
Data Required Time 10.064
From u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 198 clk_ibuf/O
0.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
0.757 0.382 tC2Q RR 4 u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/Q
1.132 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n406_s2/I0
1.659 0.526 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n406_s2/F
2.034 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/I2
2.495 0.461 tINS RR 2 u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/F
2.870 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I0
3.396 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
3.771 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I2
4.233 0.461 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
4.608 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 198 clk_ibuf/O
10.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.064 -0.311 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.975, 46.663%; route: 1.875, 44.300%; tC2Q: 0.382, 9.037%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 5.649
Data Arrival Time 4.662
Data Required Time 10.311
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 198 clk_ibuf/O
0.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
0.757 0.382 tC2Q RR 8 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.132 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n500_s9/I0
1.659 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n500_s9/F
2.034 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n500_s6/I0
2.560 0.526 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n500_s6/F
2.935 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n500_s4/I1
3.451 0.516 tINS RR 10 u_la0_top/u_ao_mem_ctrl/n500_s4/F
3.826 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n508_s1/I2
4.287 0.461 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n508_s1/F
4.662 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 198 clk_ibuf/O
10.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.311 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.030, 47.347%; route: 1.875, 43.732%; tC2Q: 0.382, 8.921%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 5.649
Data Arrival Time 4.662
Data Required Time 10.311
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 198 clk_ibuf/O
0.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
0.757 0.382 tC2Q RR 8 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.132 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n500_s9/I0
1.659 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n500_s9/F
2.034 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n500_s6/I0
2.560 0.526 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n500_s6/F
2.935 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n500_s4/I1
3.451 0.516 tINS RR 10 u_la0_top/u_ao_mem_ctrl/n500_s4/F
3.826 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n506_s1/I2
4.287 0.461 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n506_s1/F
4.662 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 198 clk_ibuf/O
10.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.311 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.030, 47.347%; route: 1.875, 43.732%; tC2Q: 0.382, 8.921%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 5.649
Data Arrival Time 4.662
Data Required Time 10.311
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 198 clk_ibuf/O
0.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
0.757 0.382 tC2Q RR 8 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.132 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n500_s9/I0
1.659 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n500_s9/F
2.034 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n500_s6/I0
2.560 0.526 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n500_s6/F
2.935 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n500_s4/I1
3.451 0.516 tINS RR 10 u_la0_top/u_ao_mem_ctrl/n500_s4/F
3.826 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n503_s1/I2
4.287 0.461 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n503_s1/F
4.662 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 198 clk_ibuf/O
10.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
10.311 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.030, 47.347%; route: 1.875, 43.732%; tC2Q: 0.382, 8.921%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%