Project Settings
Project Name cmult_18 Device Name rev_1: GOWIN-GW2A : GW2A_55
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 27 4 0 - 00m:01s - 2018/9/28
14:03:11
(premap)Complete 13 0 0 0m:05s 0m:06s 193MB 2018/9/28
14:03:19
(fpga_mapper)Complete 241 6 0 0m:48s 0m:49s 197MB 2018/9/28
14:04:09
Multi-srs Generator Complete2018/9/28
14:03:12

Area Summary
I/O ports (io_port) 157 Non I/O Register bits (non_io_reg) 39 (0%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 5 (140)
Block Multipliers (dsp_used) 2 (20) LUTs (total_luts) 16 (0%)

Timing Summary
Clock NameReq FreqEst FreqSlack
top|clk214.9 MHz182.7 MHz-0.821

Optimizations Summary
Combined Clock Conversion 1 / 0