Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.11.02_x64_internal\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.11.02_x64_internal\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.11.02_x64_internal\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.11.02_x64_internal\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.11.02_x64_internal\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.11.02_x64_internal\IDE\data\ipcores\gw_jtag.v
C:\Users\davec\Desktop\complex_multiplier verification\Gowin_Complex_Multiplier_RefDesign_mod\Complex_Multiplier_18\project\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed May 14 16:46:39 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.325s, Peak memory usage = 79.461MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 79.461MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 79.461MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 79.461MB
    Optimizing Phase 2: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.323s, Peak memory usage = 79.461MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 79.461MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 79.461MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 79.461MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 79.461MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 79.461MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.196s, Peak memory usage = 79.461MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 79.461MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 103.363MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 103.363MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 103.363MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 103.363MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 229
I/O Buf 229
    IBUF 228
    OBUF 1
Register 1158
    DFFRE 1
    DFFPE 36
    DFFCE 1121
LUT 624
    LUT2 40
    LUT3 102
    LUT4 482
MUX 1
    MUX16 1
ALU 13
    ALU 13
INV 4
    INV 4
BSRAM 13
    SDPX9B 13
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 649(636 LUT, 13 ALU) / 23040 3%
Register 1158 / 23685 5%
  --Register as Latch 0 / 23685 0%
  --Register as FF 1158 / 23685 5%
BSRAM 13 / 56 24%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 190.749(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.758
Data Arrival Time 5.554
Data Required Time 10.311
From u_la0_top/capture_window_sel_0_s3
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 534 clk_ibuf/O
0.375 0.375 tNET RR 1 u_la0_top/capture_window_sel_0_s3/CLK
0.757 0.382 tC2Q RR 14 u_la0_top/capture_window_sel_0_s3/Q
1.132 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/I1
1.649 0.516 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/F
2.024 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s16/I0
2.550 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s16/F
2.925 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/I1
3.441 0.516 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/F
3.816 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/I0
4.342 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/F
4.717 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I2
5.179 0.461 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F
5.554 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 534 clk_ibuf/O
10.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK
10.311 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.546, 49.167%; route: 2.250, 43.447%; tC2Q: 0.382, 7.386%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 4.966
Data Arrival Time 5.345
Data Required Time 10.311
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 534 clk_ibuf/O
0.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
0.757 0.382 tC2Q RR 19 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
1.132 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n1335_s2/I0
1.659 0.526 tINS RR 4 u_la0_top/u_ao_mem_ctrl/n1335_s2/F
2.034 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n1334_s2/I1
2.550 0.516 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n1334_s2/F
2.925 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n1331_s2/I3
3.188 0.262 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n1331_s2/F
3.563 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n1330_s3/I1
4.079 0.516 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n1330_s3/F
4.454 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n1330_s2/I1
4.970 0.516 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n1330_s2/F
5.345 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 534 clk_ibuf/O
10.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.311 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.338, 47.032%; route: 2.250, 45.272%; tC2Q: 0.382, 7.696%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 5.326
Data Arrival Time 4.737
Data Required Time 10.064
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 534 clk_ibuf/O
0.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
0.757 0.382 tC2Q RR 16 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.132 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n1330_s7/I0
1.659 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n1330_s7/F
2.034 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n1330_s5/I0
2.560 0.526 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n1330_s5/F
2.935 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n1330_s4/I0
3.461 0.526 tINS RR 10 u_la0_top/u_ao_mem_ctrl/n1330_s4/F
3.836 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
4.362 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
4.737 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 534 clk_ibuf/O
10.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.064 -0.311 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.105, 48.252%; route: 1.875, 42.980%; tC2Q: 0.382, 8.768%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 5.639
Data Arrival Time 4.672
Data Required Time 10.311
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 534 clk_ibuf/O
0.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
0.757 0.382 tC2Q RR 16 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.132 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n1330_s7/I0
1.659 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n1330_s7/F
2.034 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n1330_s5/I0
2.560 0.526 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n1330_s5/F
2.935 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n1330_s4/I0
3.461 0.526 tINS RR 10 u_la0_top/u_ao_mem_ctrl/n1330_s4/F
3.836 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n1338_s1/I2
4.297 0.461 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n1338_s1/F
4.672 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 534 clk_ibuf/O
10.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.311 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.040, 47.469%; route: 1.875, 43.630%; tC2Q: 0.382, 8.901%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 5.659
Data Arrival Time 4.652
Data Required Time 10.311
From u_la0_top/capture_window_sel_0_s3
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 534 clk_ibuf/O
0.375 0.375 tNET RR 1 u_la0_top/capture_window_sel_0_s3/CLK
0.757 0.382 tC2Q RR 14 u_la0_top/capture_window_sel_0_s3/Q
1.132 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s13/I1
1.649 0.516 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s13/F
2.024 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s12/I1
2.540 0.516 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s12/F
2.915 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s10/I0
3.441 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s10/F
3.816 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/I2
4.277 0.461 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/F
4.652 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 534 clk_ibuf/O
10.375 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/CLK
10.311 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.020, 47.224%; route: 1.875, 43.834%; tC2Q: 0.382, 8.942%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%