Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\PDM2PCM\data\pdm2pcm_wrap.v
C:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\PDM2PCM\data\pdm2pcm.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Jun 18 10:39:15 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module PDM2PCM_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.3s, Peak memory usage = 73.082MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 73.082MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 73.082MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 73.082MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 73.082MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 73.082MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 73.082MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 73.082MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 73.082MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 73.082MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 73.082MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 73.082MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.746s, Peak memory usage = 98.910MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.119s, Peak memory usage = 98.910MB
Generate output files:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 98.910MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 98.910MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 34
I/O Buf 34
    IBUF 8
    OBUF 26
Register 2095
    DFFRE 25
    DFFPE 9
    DFFCE 2061
LUT 515
    LUT2 129
    LUT3 200
    LUT4 186
ALU 790
    ALU 790
INV 10
    INV 10
DSP
    MULTALU27X18 1
BSRAM 2
    SDPX9B 1
    pROMX9 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1315(525 LUT, 790 ALU) / 23040 6%
Register 2095 / 23685 9%
  --Register as Latch 0 / 23685 0%
  --Register as FF 2095 / 23685 9%
BSRAM 2 / 56 4%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 173.772(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.245
Data Arrival Time 6.066
Data Required Time 10.311
From u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s
To u_pdm2pcm/u0_cic_cmp/dsp_out_36_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 2099 clk_ibuf/O
0.375 0.375 tNET RR 18 u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/CLK
0.684 0.309 tC2Q RR 1 u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/DO[1]
1.059 0.375 tNET RR 95 u_pdm2pcm/u0_cic_cmp/n662_s0/B[1]
4.800 3.741 tINS RR 1 u_pdm2pcm/u0_cic_cmp/n662_s0/DOUT[36]
5.175 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/n705_s2/I1
5.691 0.516 tINS RR 1 u_pdm2pcm/u0_cic_cmp/n705_s2/F
6.066 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/dsp_out_36_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 2099 clk_ibuf/O
10.375 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/dsp_out_36_s0/CLK
10.311 -0.064 tSu 1 u_pdm2pcm/u0_cic_cmp/dsp_out_36_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.257, 74.807%; route: 1.125, 19.768%; tC2Q: 0.309, 5.425%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 4.297
Data Arrival Time 6.014
Data Required Time 10.311
From u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s
To u_pdm2pcm/u0_cic_cmp/dsp_out_39_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 2099 clk_ibuf/O
0.375 0.375 tNET RR 18 u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/CLK
0.684 0.309 tC2Q RR 1 u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/DO[1]
1.059 0.375 tNET RR 95 u_pdm2pcm/u0_cic_cmp/n662_s0/B[1]
4.748 3.689 tINS RR 1 u_pdm2pcm/u0_cic_cmp/n662_s0/DOUT[39]
5.123 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/n702_s2/I1
5.639 0.516 tINS RR 1 u_pdm2pcm/u0_cic_cmp/n702_s2/F
6.014 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/dsp_out_39_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 2099 clk_ibuf/O
10.375 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/dsp_out_39_s0/CLK
10.311 -0.064 tSu 1 u_pdm2pcm/u0_cic_cmp/dsp_out_39_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.205, 74.575%; route: 1.125, 19.950%; tC2Q: 0.309, 5.475%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 4.313
Data Arrival Time 5.998
Data Required Time 10.311
From u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s
To u_pdm2pcm/u0_cic_cmp/dsp_out_38_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 2099 clk_ibuf/O
0.375 0.375 tNET RR 18 u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/CLK
0.684 0.309 tC2Q RR 1 u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/DO[1]
1.059 0.375 tNET RR 95 u_pdm2pcm/u0_cic_cmp/n662_s0/B[1]
4.732 3.673 tINS RR 1 u_pdm2pcm/u0_cic_cmp/n662_s0/DOUT[38]
5.107 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/n703_s2/I1
5.623 0.516 tINS RR 1 u_pdm2pcm/u0_cic_cmp/n703_s2/F
5.998 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/dsp_out_38_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 2099 clk_ibuf/O
10.375 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/dsp_out_38_s0/CLK
10.311 -0.064 tSu 1 u_pdm2pcm/u0_cic_cmp/dsp_out_38_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.189, 74.503%; route: 1.125, 20.006%; tC2Q: 0.309, 5.491%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 4.379
Data Arrival Time 5.932
Data Required Time 10.311
From u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s
To u_pdm2pcm/u0_cic_cmp/dsp_out_37_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 2099 clk_ibuf/O
0.375 0.375 tNET RR 18 u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/CLK
0.684 0.309 tC2Q RR 1 u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/DO[1]
1.059 0.375 tNET RR 95 u_pdm2pcm/u0_cic_cmp/n662_s0/B[1]
4.666 3.607 tINS RR 1 u_pdm2pcm/u0_cic_cmp/n662_s0/DOUT[37]
5.041 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/n704_s2/I1
5.557 0.516 tINS RR 1 u_pdm2pcm/u0_cic_cmp/n704_s2/F
5.932 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/dsp_out_37_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 2099 clk_ibuf/O
10.375 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/dsp_out_37_s0/CLK
10.311 -0.064 tSu 1 u_pdm2pcm/u0_cic_cmp/dsp_out_37_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.123, 74.199%; route: 1.125, 20.245%; tC2Q: 0.309, 5.556%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 4.401
Data Arrival Time 5.910
Data Required Time 10.311
From u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s
To u_pdm2pcm/u0_cic_cmp/dsp_out_35_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 2099 clk_ibuf/O
0.375 0.375 tNET RR 18 u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/CLK
0.684 0.309 tC2Q RR 1 u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/DO[1]
1.059 0.375 tNET RR 95 u_pdm2pcm/u0_cic_cmp/n662_s0/B[1]
4.669 3.610 tINS RF 1 u_pdm2pcm/u0_cic_cmp/n662_s0/DOUT[35]
5.019 0.350 tNET FF 1 u_pdm2pcm/u0_cic_cmp/n706_s2/I1
5.535 0.516 tINS FR 1 u_pdm2pcm/u0_cic_cmp/n706_s2/F
5.910 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/dsp_out_35_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 2099 clk_ibuf/O
10.375 0.375 tNET RR 1 u_pdm2pcm/u0_cic_cmp/dsp_out_35_s0/CLK
10.311 -0.064 tSu 1 u_pdm2pcm/u0_cic_cmp/dsp_out_35_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.126, 74.549%; route: 1.100, 19.873%; tC2Q: 0.309, 5.578%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%