Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.11.03\Gowin_PDM2PCM_RefDesign\GW-5A\project\impl\gwsynthesis\Ref_design.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.11.03\Gowin_PDM2PCM_RefDesign\GW-5A\project\src\Top.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.11.03\Gowin_PDM2PCM_RefDesign\GW-5A\project\src\pdm2pcm.sdc
Tool Version	V1.9.11.03 (64-bit)
Part Number	GW5A-LV25UG324ES
Device	GW5A-25
Device Version	A
Created Time	Thu Jun 26 09:34:40 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C ES
Hold Delay Model	Fast 0.945V 85C ES
Numbers of Paths Analyzed	7551
Numbers of Endpoints Analyzed	9071
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk1	Base	20.000	50.000	0.000	10.000			SYM_CLK
2	tck_pad	Base	20.000	50.000	0.000	10.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk1	50.000(MHz)	69.979(MHz)	11	TOP
2	tck_pad	50.000(MHz)	120.978(MHz)	7	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk1	Setup	0.000	0
clk1	Hold	0.000	0
tck_pad	Setup	0.000	0
tck_pad	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.710	drom_addr_12_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0/D	clk1:[R]	clk1:[R]	20.000	0.036	14.190
2	6.042	drom_addr_12_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0/D	clk1:[R]	clk1:[R]	20.000	0.027	13.867
3	6.044	drom_addr_12_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0/D	clk1:[R]	clk1:[R]	20.000	0.027	13.865
4	6.044	drom_addr_12_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/D	clk1:[R]	clk1:[R]	20.000	0.027	13.865
5	6.352	drom_addr_12_s0/Q	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_3_s0/D	clk1:[R]	clk1:[R]	20.000	0.046	13.539
6	6.354	drom_addr_12_s0/Q	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_0_s0/D	clk1:[R]	clk1:[R]	20.000	0.046	13.536
7	6.354	drom_addr_12_s0/Q	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_1_s0/D	clk1:[R]	clk1:[R]	20.000	0.046	13.536
8	6.354	drom_addr_12_s0/Q	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_2_s0/D	clk1:[R]	clk1:[R]	20.000	0.046	13.536
9	11.734	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_10_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.026	7.929
10	11.935	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_5_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.015	7.739
11	11.935	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_8_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.015	7.739
12	11.935	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_9_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.015	7.739
13	12.127	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_4_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.018	7.544
14	12.127	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_11_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.018	7.544
15	12.127	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_12_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.018	7.544
16	12.236	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_6_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.017	7.436
17	12.236	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_7_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.017	7.436
18	12.245	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_0_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.007	7.436
19	12.245	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_1_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.007	7.436
20	12.245	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_2_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.007	7.436
21	12.245	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_3_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.007	7.436
22	12.513	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_13_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.017	7.159
23	12.513	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_14_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.017	7.159
24	12.513	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/word_count_15_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.017	7.159
25	12.700	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_1_s0/CE	tck_pad:[R]	tck_pad:[R]	20.000	0.017	6.973

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.184	gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/ADB[7]	tck_pad:[R]	tck_pad:[R]	0.000	0.001	0.218
2	0.193	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s/DI[0]	clk1:[R]	clk1:[R]	0.000	-0.005	0.235
3	0.195	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_1_s0/Q	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/AD[5]	clk1:[R]	clk1:[R]	0.000	-0.005	0.235
4	0.199	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_2_s0/Q	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/AD[6]	clk1:[R]	clk1:[R]	0.000	-0.001	0.235
5	0.216	gw_gao_inst_0/u_la0_top/address_counter_6_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/ADB[6]	tck_pad:[R]	tck_pad:[R]	0.000	0.001	0.250
6	0.222	gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/ADB[4]	tck_pad:[R]	tck_pad:[R]	0.000	0.005	0.252
7	0.222	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_5_s0/Q	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/AD[9]	clk1:[R]	clk1:[R]	0.000	-0.001	0.258
8	0.222	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_4_s0/Q	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/AD[8]	clk1:[R]	clk1:[R]	0.000	-0.001	0.258
9	0.222	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_3_s0/Q	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/AD[7]	clk1:[R]	clk1:[R]	0.000	-0.001	0.258
10	0.224	gw_gao_inst_0/u_la0_top/address_counter_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/ADB[0]	tck_pad:[R]	tck_pad:[R]	0.000	0.009	0.250
11	0.248	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_4_s0/Q	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/u0_sdpx9b_dmem/DI[4]	clk1:[R]	clk1:[R]	0.000	-0.001	0.286
12	0.249	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/DI[0]	clk1:[R]	clk1:[R]	0.000	0.002	0.284
13	0.250	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/DI[0]	clk1:[R]	clk1:[R]	0.000	-0.005	0.292
14	0.252	gw_gao_inst_0/u_la0_top/address_counter_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s/ADB[3]	tck_pad:[R]	tck_pad:[R]	0.000	-0.003	0.290
15	0.252	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_3_s0/Q	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/u0_sdpx9b_dmem/DI[3]	clk1:[R]	clk1:[R]	0.000	0.003	0.286
16	0.261	gw_gao_inst_0/u_la0_top/address_counter_9_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/ADB[9]	tck_pad:[R]	tck_pad:[R]	0.000	0.005	0.291
17	0.261	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_19_s0/Q	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/gowin_add_SDPX9B_u0_sdpx9b_dmem/DI[1]	clk1:[R]	clk1:[R]	0.000	-0.001	0.299
18	0.261	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_18_s0/Q	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/gowin_add_SDPX9B_u0_sdpx9b_dmem/DI[0]	clk1:[R]	clk1:[R]	0.000	-0.001	0.299
19	0.271	gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_23_s/ADB[10]	tck_pad:[R]	tck_pad:[R]	0.000	-0.006	0.312
20	0.274	gw_gao_inst_0/u_la0_top/address_counter_12_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/ADB[12]	tck_pad:[R]	tck_pad:[R]	0.000	-0.010	0.319
21	0.275	gw_gao_inst_0/u_la0_top/word_count_7_s0/Q	gw_gao_inst_0/u_la0_top/word_count_7_s0/D	tck_pad:[R]	tck_pad:[R]	0.000	0.000	0.300
22	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.300
23	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.300
24	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.300
25	0.275	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	7.024	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.020	2.608
2	7.024	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.014	2.614
3	7.024	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.014	2.614
4	7.028	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk1:[F]	clk1:[R]	10.000	0.001	2.624
5	7.028	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	0.001	2.624
6	7.028	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_13_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.003	2.628
7	7.028	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.001	2.624
8	7.028	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR	clk1:[F]	clk1:[R]	10.000	0.002	2.622
9	7.028	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	0.002	2.622
10	7.028	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.626
11	7.028	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.002	2.622
12	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.011	2.608
13	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.005	2.614
14	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.005	2.614
15	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.011	2.608
16	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.011	2.608
17	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.005	2.614
18	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_9_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.005	2.614
19	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.620
20	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.620
21	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.620
22	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.620
23	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.620
24	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.620
25	7.033	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.620

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk1:[F]	clk1:[R]	-10.000	-0.003	1.052
2	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.003	1.052
3	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.003	1.052
4	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.003	1.052
5	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.003	1.052
6	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.004	1.054
7	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.004	1.054
8	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_13_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.004	1.054
9	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.004	1.054
10	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.003	1.052
11	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.004	1.054
12	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.004	1.054
13	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.004	1.054
14	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.003	1.052
15	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_12_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.007	1.056
16	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_13_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.007	1.056
17	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.004	1.054
18	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.004	1.054
19	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.004	1.054
20	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.004	1.054
21	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.005	1.055
22	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.005	1.055
23	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.005	1.055
24	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.005	1.055
25	11.102	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	-0.005	1.055

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	7.356	8.356	1.000	Low Pulse Width	tck_pad	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_16_s
2	7.356	8.356	1.000	Low Pulse Width	tck_pad	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s
3	7.362	8.362	1.000	Low Pulse Width	tck_pad	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
4	7.362	8.362	1.000	Low Pulse Width	tck_pad	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
5	7.362	8.362	1.000	Low Pulse Width	tck_pad	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s
6	7.362	8.362	1.000	Low Pulse Width	tck_pad	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_11_s
7	7.362	8.362	1.000	Low Pulse Width	tck_pad	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s
8	7.362	8.362	1.000	Low Pulse Width	tck_pad	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s
9	7.362	8.362	1.000	Low Pulse Width	tck_pad	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_26_s
10	7.362	8.362	1.000	Low Pulse Width	tck_pad	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_30_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.710
Data Arrival Time	16.847
Data Required Time	22.558
From	drom_addr_12_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
2.658	1.975	tNET	RR	1	R20C53[0][A]	drom_addr_12_s0/CLK
3.025	0.368	tC2Q	RF	407	R20C53[0][A]	drom_addr_12_s0/Q
4.023	0.998	tNET	FF	1	R25C52[2][A]	n124_s28841/I0
4.484	0.461	tINS	FR	21	R25C52[2][A]	n124_s28841/F
7.249	2.765	tNET	RR	1	R3C48[3][A]	n124_s30645/I2
7.664	0.415	tINS	RR	26	R3C48[3][A]	n124_s30645/F
10.106	2.442	tNET	RR	1	R20C55[2][A]	n124_s30263/I1
10.622	0.516	tINS	RR	2	R20C55[2][A]	n124_s30263/F
11.162	0.540	tNET	RR	1	R24C55[2][A]	n124_s30262/I1
11.679	0.516	tINS	RR	1	R24C55[2][A]	n124_s30262/F
11.681	0.003	tNET	RR	1	R24C55[3][A]	n124_s29520/I0
12.096	0.415	tINS	RR	1	R24C55[3][A]	n124_s29520/F
12.099	0.003	tNET	RR	1	R24C55[3][B]	n124_s29081/I0
12.514	0.415	tINS	RR	1	R24C55[3][B]	n124_s29081/F
12.516	0.003	tNET	RR	1	R24C55[2][B]	n124_s28905/I0
13.042	0.526	tINS	RR	1	R24C55[2][B]	n124_s28905/F
13.959	0.916	tNET	RR	1	R14C49[0][B]	n124_s30780/I2
14.194	0.235	tINS	RF	1	R14C49[0][B]	n124_s30780/F
14.194	0.000	tNET	FF	1	R14C49[0][A]	n124_s30754/I1
14.390	0.196	tINS	FF	1	R14C49[0][A]	n124_s30754/O
14.390	0.000	tNET	FF	1	R14C49[0][B]	n124_s30742/I1
14.491	0.101	tINS	FF	1	R14C49[0][B]	n124_s30742/O
14.491	0.000	tNET	FF	1	R14C49[1][B]	n124_s28807/I1
14.592	0.101	tINS	FF	1	R14C49[1][B]	n124_s28807/O
14.919	0.326	tNET	FF	1	R15C50[1][A]	u_PDM2PCM_Top_26_s0/I2
15.181	0.262	tINS	FR	8	R15C50[1][A]	u_PDM2PCM_Top_26_s0/F
16.847	1.666	tNET	RR	1	R27C44[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.621	1.939	tNET	RR	1	R27C44[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0/CLK
22.558	-0.064	tSu		1	R27C44[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0

Path Statistics:

Clock Skew	-0.036
Setup Relationship	20.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%
Arrival Data Path Delay	cell: 4.161, 29.325%; route: 9.661, 68.085%; tC2Q: 0.368, 2.590%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path2

Path Summary:

Slack	6.042
Data Arrival Time	16.525
Data Required Time	22.567
From	drom_addr_12_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
2.658	1.975	tNET	RR	1	R20C53[0][A]	drom_addr_12_s0/CLK
3.025	0.368	tC2Q	RF	407	R20C53[0][A]	drom_addr_12_s0/Q
4.023	0.998	tNET	FF	1	R25C52[2][A]	n124_s28841/I0
4.484	0.461	tINS	FR	21	R25C52[2][A]	n124_s28841/F
7.249	2.765	tNET	RR	1	R3C48[3][A]	n124_s30645/I2
7.664	0.415	tINS	RR	26	R3C48[3][A]	n124_s30645/F
10.106	2.442	tNET	RR	1	R20C55[2][A]	n124_s30263/I1
10.622	0.516	tINS	RR	2	R20C55[2][A]	n124_s30263/F
11.162	0.540	tNET	RR	1	R24C55[2][A]	n124_s30262/I1
11.679	0.516	tINS	RR	1	R24C55[2][A]	n124_s30262/F
11.681	0.003	tNET	RR	1	R24C55[3][A]	n124_s29520/I0
12.096	0.415	tINS	RR	1	R24C55[3][A]	n124_s29520/F
12.099	0.003	tNET	RR	1	R24C55[3][B]	n124_s29081/I0
12.514	0.415	tINS	RR	1	R24C55[3][B]	n124_s29081/F
12.516	0.003	tNET	RR	1	R24C55[2][B]	n124_s28905/I0
13.042	0.526	tINS	RR	1	R24C55[2][B]	n124_s28905/F
13.959	0.916	tNET	RR	1	R14C49[0][B]	n124_s30780/I2
14.194	0.235	tINS	RF	1	R14C49[0][B]	n124_s30780/F
14.194	0.000	tNET	FF	1	R14C49[0][A]	n124_s30754/I1
14.390	0.196	tINS	FF	1	R14C49[0][A]	n124_s30754/O
14.390	0.000	tNET	FF	1	R14C49[0][B]	n124_s30742/I1
14.491	0.101	tINS	FF	1	R14C49[0][B]	n124_s30742/O
14.491	0.000	tNET	FF	1	R14C49[1][B]	n124_s28807/I1
14.592	0.101	tINS	FF	1	R14C49[1][B]	n124_s28807/O
14.919	0.326	tNET	FF	1	R15C50[1][A]	u_PDM2PCM_Top_26_s0/I2
15.181	0.262	tINS	FR	8	R15C50[1][A]	u_PDM2PCM_Top_26_s0/F
16.525	1.344	tNET	RR	1	R27C45[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.631	1.948	tNET	RR	1	R27C45[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0/CLK
22.567	-0.064	tSu		1	R27C45[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%
Arrival Data Path Delay	cell: 4.161, 30.007%; route: 9.339, 67.343%; tC2Q: 0.368, 2.650%
Required Clock Path Delay	cell: 0.683, 25.944%; route: 1.948, 74.056%

Path3

Path Summary:

Slack	6.044
Data Arrival Time	16.522
Data Required Time	22.567
From	drom_addr_12_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
2.658	1.975	tNET	RR	1	R20C53[0][A]	drom_addr_12_s0/CLK
3.025	0.368	tC2Q	RF	407	R20C53[0][A]	drom_addr_12_s0/Q
4.023	0.998	tNET	FF	1	R25C52[2][A]	n124_s28841/I0
4.484	0.461	tINS	FR	21	R25C52[2][A]	n124_s28841/F
7.249	2.765	tNET	RR	1	R3C48[3][A]	n124_s30645/I2
7.664	0.415	tINS	RR	26	R3C48[3][A]	n124_s30645/F
10.106	2.442	tNET	RR	1	R20C55[2][A]	n124_s30263/I1
10.622	0.516	tINS	RR	2	R20C55[2][A]	n124_s30263/F
11.162	0.540	tNET	RR	1	R24C55[2][A]	n124_s30262/I1
11.679	0.516	tINS	RR	1	R24C55[2][A]	n124_s30262/F
11.681	0.003	tNET	RR	1	R24C55[3][A]	n124_s29520/I0
12.096	0.415	tINS	RR	1	R24C55[3][A]	n124_s29520/F
12.099	0.003	tNET	RR	1	R24C55[3][B]	n124_s29081/I0
12.514	0.415	tINS	RR	1	R24C55[3][B]	n124_s29081/F
12.516	0.003	tNET	RR	1	R24C55[2][B]	n124_s28905/I0
13.042	0.526	tINS	RR	1	R24C55[2][B]	n124_s28905/F
13.959	0.916	tNET	RR	1	R14C49[0][B]	n124_s30780/I2
14.194	0.235	tINS	RF	1	R14C49[0][B]	n124_s30780/F
14.194	0.000	tNET	FF	1	R14C49[0][A]	n124_s30754/I1
14.390	0.196	tINS	FF	1	R14C49[0][A]	n124_s30754/O
14.390	0.000	tNET	FF	1	R14C49[0][B]	n124_s30742/I1
14.491	0.101	tINS	FF	1	R14C49[0][B]	n124_s30742/O
14.491	0.000	tNET	FF	1	R14C49[1][B]	n124_s28807/I1
14.592	0.101	tINS	FF	1	R14C49[1][B]	n124_s28807/O
14.919	0.326	tNET	FF	1	R15C50[1][A]	u_PDM2PCM_Top_26_s0/I2
15.181	0.262	tINS	FR	8	R15C50[1][A]	u_PDM2PCM_Top_26_s0/F
16.522	1.341	tNET	RR	1	R27C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.631	1.948	tNET	RR	1	R27C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0/CLK
22.567	-0.064	tSu		1	R27C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%
Arrival Data Path Delay	cell: 4.161, 30.013%; route: 9.336, 67.337%; tC2Q: 0.368, 2.651%
Required Clock Path Delay	cell: 0.683, 25.944%; route: 1.948, 74.056%

Path4

Path Summary:

Slack	6.044
Data Arrival Time	16.522
Data Required Time	22.567
From	drom_addr_12_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
2.658	1.975	tNET	RR	1	R20C53[0][A]	drom_addr_12_s0/CLK
3.025	0.368	tC2Q	RF	407	R20C53[0][A]	drom_addr_12_s0/Q
4.023	0.998	tNET	FF	1	R25C52[2][A]	n124_s28841/I0
4.484	0.461	tINS	FR	21	R25C52[2][A]	n124_s28841/F
7.249	2.765	tNET	RR	1	R3C48[3][A]	n124_s30645/I2
7.664	0.415	tINS	RR	26	R3C48[3][A]	n124_s30645/F
10.106	2.442	tNET	RR	1	R20C55[2][A]	n124_s30263/I1
10.622	0.516	tINS	RR	2	R20C55[2][A]	n124_s30263/F
11.162	0.540	tNET	RR	1	R24C55[2][A]	n124_s30262/I1
11.679	0.516	tINS	RR	1	R24C55[2][A]	n124_s30262/F
11.681	0.003	tNET	RR	1	R24C55[3][A]	n124_s29520/I0
12.096	0.415	tINS	RR	1	R24C55[3][A]	n124_s29520/F
12.099	0.003	tNET	RR	1	R24C55[3][B]	n124_s29081/I0
12.514	0.415	tINS	RR	1	R24C55[3][B]	n124_s29081/F
12.516	0.003	tNET	RR	1	R24C55[2][B]	n124_s28905/I0
13.042	0.526	tINS	RR	1	R24C55[2][B]	n124_s28905/F
13.959	0.916	tNET	RR	1	R14C49[0][B]	n124_s30780/I2
14.194	0.235	tINS	RF	1	R14C49[0][B]	n124_s30780/F
14.194	0.000	tNET	FF	1	R14C49[0][A]	n124_s30754/I1
14.390	0.196	tINS	FF	1	R14C49[0][A]	n124_s30754/O
14.390	0.000	tNET	FF	1	R14C49[0][B]	n124_s30742/I1
14.491	0.101	tINS	FF	1	R14C49[0][B]	n124_s30742/O
14.491	0.000	tNET	FF	1	R14C49[1][B]	n124_s28807/I1
14.592	0.101	tINS	FF	1	R14C49[1][B]	n124_s28807/O
14.919	0.326	tNET	FF	1	R15C50[1][A]	u_PDM2PCM_Top_26_s0/I2
15.181	0.262	tINS	FR	8	R15C50[1][A]	u_PDM2PCM_Top_26_s0/F
16.522	1.341	tNET	RR	1	R27C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.631	1.948	tNET	RR	1	R27C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/CLK
22.567	-0.064	tSu		1	R27C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%
Arrival Data Path Delay	cell: 4.161, 30.013%; route: 9.336, 67.337%; tC2Q: 0.368, 2.651%
Required Clock Path Delay	cell: 0.683, 25.944%; route: 1.948, 74.056%

Path5

Path Summary:

Slack	6.352
Data Arrival Time	16.196
Data Required Time	22.548
From	drom_addr_12_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_3_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
2.658	1.975	tNET	RR	1	R20C53[0][A]	drom_addr_12_s0/CLK
3.025	0.368	tC2Q	RF	407	R20C53[0][A]	drom_addr_12_s0/Q
4.023	0.998	tNET	FF	1	R25C52[2][A]	n124_s28841/I0
4.484	0.461	tINS	FR	21	R25C52[2][A]	n124_s28841/F
7.249	2.765	tNET	RR	1	R3C48[3][A]	n124_s30645/I2
7.664	0.415	tINS	RR	26	R3C48[3][A]	n124_s30645/F
10.106	2.442	tNET	RR	1	R20C55[2][A]	n124_s30263/I1
10.622	0.516	tINS	RR	2	R20C55[2][A]	n124_s30263/F
11.162	0.540	tNET	RR	1	R24C55[2][A]	n124_s30262/I1
11.679	0.516	tINS	RR	1	R24C55[2][A]	n124_s30262/F
11.681	0.003	tNET	RR	1	R24C55[3][A]	n124_s29520/I0
12.096	0.415	tINS	RR	1	R24C55[3][A]	n124_s29520/F
12.099	0.003	tNET	RR	1	R24C55[3][B]	n124_s29081/I0
12.514	0.415	tINS	RR	1	R24C55[3][B]	n124_s29081/F
12.516	0.003	tNET	RR	1	R24C55[2][B]	n124_s28905/I0
13.042	0.526	tINS	RR	1	R24C55[2][B]	n124_s28905/F
13.959	0.916	tNET	RR	1	R14C49[0][B]	n124_s30780/I2
14.194	0.235	tINS	RF	1	R14C49[0][B]	n124_s30780/F
14.194	0.000	tNET	FF	1	R14C49[0][A]	n124_s30754/I1
14.390	0.196	tINS	FF	1	R14C49[0][A]	n124_s30754/O
14.390	0.000	tNET	FF	1	R14C49[0][B]	n124_s30742/I1
14.491	0.101	tINS	FF	1	R14C49[0][B]	n124_s30742/O
14.491	0.000	tNET	FF	1	R14C49[1][B]	n124_s28807/I1
14.592	0.101	tINS	FF	1	R14C49[1][B]	n124_s28807/O
14.919	0.326	tNET	FF	1	R15C50[1][A]	u_PDM2PCM_Top_26_s0/I2
15.181	0.262	tINS	FR	8	R15C50[1][A]	u_PDM2PCM_Top_26_s0/F
16.196	1.015	tNET	RR	1	R14C33[3][A]	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.612	1.929	tNET	RR	1	R14C33[3][A]	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_3_s0/CLK
22.548	-0.064	tSu		1	R14C33[3][A]	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_3_s0

Path Statistics:

Clock Skew	-0.046
Setup Relationship	20.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%
Arrival Data Path Delay	cell: 4.161, 30.736%; route: 9.010, 66.550%; tC2Q: 0.368, 2.714%
Required Clock Path Delay	cell: 0.683, 26.134%; route: 1.929, 73.866%

Path6

Path Summary:

Slack	6.354
Data Arrival Time	16.194
Data Required Time	22.548
From	drom_addr_12_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_0_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
2.658	1.975	tNET	RR	1	R20C53[0][A]	drom_addr_12_s0/CLK
3.025	0.368	tC2Q	RF	407	R20C53[0][A]	drom_addr_12_s0/Q
4.023	0.998	tNET	FF	1	R25C52[2][A]	n124_s28841/I0
4.484	0.461	tINS	FR	21	R25C52[2][A]	n124_s28841/F
7.249	2.765	tNET	RR	1	R3C48[3][A]	n124_s30645/I2
7.664	0.415	tINS	RR	26	R3C48[3][A]	n124_s30645/F
10.106	2.442	tNET	RR	1	R20C55[2][A]	n124_s30263/I1
10.622	0.516	tINS	RR	2	R20C55[2][A]	n124_s30263/F
11.162	0.540	tNET	RR	1	R24C55[2][A]	n124_s30262/I1
11.679	0.516	tINS	RR	1	R24C55[2][A]	n124_s30262/F
11.681	0.003	tNET	RR	1	R24C55[3][A]	n124_s29520/I0
12.096	0.415	tINS	RR	1	R24C55[3][A]	n124_s29520/F
12.099	0.003	tNET	RR	1	R24C55[3][B]	n124_s29081/I0
12.514	0.415	tINS	RR	1	R24C55[3][B]	n124_s29081/F
12.516	0.003	tNET	RR	1	R24C55[2][B]	n124_s28905/I0
13.042	0.526	tINS	RR	1	R24C55[2][B]	n124_s28905/F
13.959	0.916	tNET	RR	1	R14C49[0][B]	n124_s30780/I2
14.194	0.235	tINS	RF	1	R14C49[0][B]	n124_s30780/F
14.194	0.000	tNET	FF	1	R14C49[0][A]	n124_s30754/I1
14.390	0.196	tINS	FF	1	R14C49[0][A]	n124_s30754/O
14.390	0.000	tNET	FF	1	R14C49[0][B]	n124_s30742/I1
14.491	0.101	tINS	FF	1	R14C49[0][B]	n124_s30742/O
14.491	0.000	tNET	FF	1	R14C49[1][B]	n124_s28807/I1
14.592	0.101	tINS	FF	1	R14C49[1][B]	n124_s28807/O
14.919	0.326	tNET	FF	1	R15C50[1][A]	u_PDM2PCM_Top_26_s0/I2
15.181	0.262	tINS	FR	8	R15C50[1][A]	u_PDM2PCM_Top_26_s0/F
16.194	1.013	tNET	RR	1	R14C33[1][B]	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.612	1.929	tNET	RR	1	R14C33[1][B]	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_0_s0/CLK
22.548	-0.064	tSu		1	R14C33[1][B]	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_0_s0

Path Statistics:

Clock Skew	-0.046
Setup Relationship	20.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%
Arrival Data Path Delay	cell: 4.161, 30.742%; route: 9.007, 66.544%; tC2Q: 0.368, 2.715%
Required Clock Path Delay	cell: 0.683, 26.134%; route: 1.929, 73.866%

Path7

Path Summary:

Slack	6.354
Data Arrival Time	16.194
Data Required Time	22.548
From	drom_addr_12_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_1_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
2.658	1.975	tNET	RR	1	R20C53[0][A]	drom_addr_12_s0/CLK
3.025	0.368	tC2Q	RF	407	R20C53[0][A]	drom_addr_12_s0/Q
4.023	0.998	tNET	FF	1	R25C52[2][A]	n124_s28841/I0
4.484	0.461	tINS	FR	21	R25C52[2][A]	n124_s28841/F
7.249	2.765	tNET	RR	1	R3C48[3][A]	n124_s30645/I2
7.664	0.415	tINS	RR	26	R3C48[3][A]	n124_s30645/F
10.106	2.442	tNET	RR	1	R20C55[2][A]	n124_s30263/I1
10.622	0.516	tINS	RR	2	R20C55[2][A]	n124_s30263/F
11.162	0.540	tNET	RR	1	R24C55[2][A]	n124_s30262/I1
11.679	0.516	tINS	RR	1	R24C55[2][A]	n124_s30262/F
11.681	0.003	tNET	RR	1	R24C55[3][A]	n124_s29520/I0
12.096	0.415	tINS	RR	1	R24C55[3][A]	n124_s29520/F
12.099	0.003	tNET	RR	1	R24C55[3][B]	n124_s29081/I0
12.514	0.415	tINS	RR	1	R24C55[3][B]	n124_s29081/F
12.516	0.003	tNET	RR	1	R24C55[2][B]	n124_s28905/I0
13.042	0.526	tINS	RR	1	R24C55[2][B]	n124_s28905/F
13.959	0.916	tNET	RR	1	R14C49[0][B]	n124_s30780/I2
14.194	0.235	tINS	RF	1	R14C49[0][B]	n124_s30780/F
14.194	0.000	tNET	FF	1	R14C49[0][A]	n124_s30754/I1
14.390	0.196	tINS	FF	1	R14C49[0][A]	n124_s30754/O
14.390	0.000	tNET	FF	1	R14C49[0][B]	n124_s30742/I1
14.491	0.101	tINS	FF	1	R14C49[0][B]	n124_s30742/O
14.491	0.000	tNET	FF	1	R14C49[1][B]	n124_s28807/I1
14.592	0.101	tINS	FF	1	R14C49[1][B]	n124_s28807/O
14.919	0.326	tNET	FF	1	R15C50[1][A]	u_PDM2PCM_Top_26_s0/I2
15.181	0.262	tINS	FR	8	R15C50[1][A]	u_PDM2PCM_Top_26_s0/F
16.194	1.013	tNET	RR	1	R14C33[2][A]	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.612	1.929	tNET	RR	1	R14C33[2][A]	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_1_s0/CLK
22.548	-0.064	tSu		1	R14C33[2][A]	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_1_s0

Path Statistics:

Clock Skew	-0.046
Setup Relationship	20.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%
Arrival Data Path Delay	cell: 4.161, 30.742%; route: 9.007, 66.544%; tC2Q: 0.368, 2.715%
Required Clock Path Delay	cell: 0.683, 26.134%; route: 1.929, 73.866%

Path8

Path Summary:

Slack	6.354
Data Arrival Time	16.194
Data Required Time	22.548
From	drom_addr_12_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_2_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
2.658	1.975	tNET	RR	1	R20C53[0][A]	drom_addr_12_s0/CLK
3.025	0.368	tC2Q	RF	407	R20C53[0][A]	drom_addr_12_s0/Q
4.023	0.998	tNET	FF	1	R25C52[2][A]	n124_s28841/I0
4.484	0.461	tINS	FR	21	R25C52[2][A]	n124_s28841/F
7.249	2.765	tNET	RR	1	R3C48[3][A]	n124_s30645/I2
7.664	0.415	tINS	RR	26	R3C48[3][A]	n124_s30645/F
10.106	2.442	tNET	RR	1	R20C55[2][A]	n124_s30263/I1
10.622	0.516	tINS	RR	2	R20C55[2][A]	n124_s30263/F
11.162	0.540	tNET	RR	1	R24C55[2][A]	n124_s30262/I1
11.679	0.516	tINS	RR	1	R24C55[2][A]	n124_s30262/F
11.681	0.003	tNET	RR	1	R24C55[3][A]	n124_s29520/I0
12.096	0.415	tINS	RR	1	R24C55[3][A]	n124_s29520/F
12.099	0.003	tNET	RR	1	R24C55[3][B]	n124_s29081/I0
12.514	0.415	tINS	RR	1	R24C55[3][B]	n124_s29081/F
12.516	0.003	tNET	RR	1	R24C55[2][B]	n124_s28905/I0
13.042	0.526	tINS	RR	1	R24C55[2][B]	n124_s28905/F
13.959	0.916	tNET	RR	1	R14C49[0][B]	n124_s30780/I2
14.194	0.235	tINS	RF	1	R14C49[0][B]	n124_s30780/F
14.194	0.000	tNET	FF	1	R14C49[0][A]	n124_s30754/I1
14.390	0.196	tINS	FF	1	R14C49[0][A]	n124_s30754/O
14.390	0.000	tNET	FF	1	R14C49[0][B]	n124_s30742/I1
14.491	0.101	tINS	FF	1	R14C49[0][B]	n124_s30742/O
14.491	0.000	tNET	FF	1	R14C49[1][B]	n124_s28807/I1
14.592	0.101	tINS	FF	1	R14C49[1][B]	n124_s28807/O
14.919	0.326	tNET	FF	1	R15C50[1][A]	u_PDM2PCM_Top_26_s0/I2
15.181	0.262	tINS	FR	8	R15C50[1][A]	u_PDM2PCM_Top_26_s0/F
16.194	1.013	tNET	RR	1	R14C33[2][B]	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.612	1.929	tNET	RR	1	R14C33[2][B]	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_2_s0/CLK
22.548	-0.064	tSu		1	R14C33[2][B]	u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_2_s0

Path Statistics:

Clock Skew	-0.046
Setup Relationship	20.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.683, 25.682%; route: 1.975, 74.318%
Arrival Data Path Delay	cell: 4.161, 30.742%; route: 9.007, 66.544%; tC2Q: 0.368, 2.715%
Required Clock Path Delay	cell: 0.683, 26.134%; route: 1.929, 73.866%

Path9

Path Summary:

Slack	11.734
Data Arrival Time	12.000
Data Required Time	23.734
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_10_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
12.000	1.122	tNET	RR	1	R35C50[2][B]	gw_gao_inst_0/u_la0_top/word_count_10_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.045	2.680	tNET	RR	1	R35C50[2][B]	gw_gao_inst_0/u_la0_top/word_count_10_s0/CLK
23.734	-0.311	tSu		1	R35C50[2][B]	gw_gao_inst_0/u_la0_top/word_count_10_s0

Path Statistics:

Clock Skew	-0.026
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 37.112%; route: 4.604, 58.064%; tC2Q: 0.382, 4.824%
Required Clock Path Delay	cell: 1.365, 33.745%; route: 2.680, 66.255%

Path10

Path Summary:

Slack	11.935
Data Arrival Time	11.810
Data Required Time	23.745
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_5_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.810	0.933	tNET	RR	1	R36C51[2][B]	gw_gao_inst_0/u_la0_top/word_count_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.056	2.691	tNET	RR	1	R36C51[2][B]	gw_gao_inst_0/u_la0_top/word_count_5_s0/CLK
23.745	-0.311	tSu		1	R36C51[2][B]	gw_gao_inst_0/u_la0_top/word_count_5_s0

Path Statistics:

Clock Skew	-0.015
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 38.023%; route: 4.414, 57.034%; tC2Q: 0.382, 4.943%
Required Clock Path Delay	cell: 1.365, 33.652%; route: 2.691, 66.348%

Path11

Path Summary:

Slack	11.935
Data Arrival Time	11.810
Data Required Time	23.745
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_8_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.810	0.933	tNET	RR	1	R36C51[1][B]	gw_gao_inst_0/u_la0_top/word_count_8_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.056	2.691	tNET	RR	1	R36C51[1][B]	gw_gao_inst_0/u_la0_top/word_count_8_s0/CLK
23.745	-0.311	tSu		1	R36C51[1][B]	gw_gao_inst_0/u_la0_top/word_count_8_s0

Path Statistics:

Clock Skew	-0.015
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 38.023%; route: 4.414, 57.034%; tC2Q: 0.382, 4.943%
Required Clock Path Delay	cell: 1.365, 33.652%; route: 2.691, 66.348%

Path12

Path Summary:

Slack	11.935
Data Arrival Time	11.810
Data Required Time	23.745
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_9_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.810	0.933	tNET	RR	1	R36C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_9_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.056	2.691	tNET	RR	1	R36C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_9_s0/CLK
23.745	-0.311	tSu		1	R36C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_9_s0

Path Statistics:

Clock Skew	-0.015
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 38.023%; route: 4.414, 57.034%; tC2Q: 0.382, 4.943%
Required Clock Path Delay	cell: 1.365, 33.652%; route: 2.691, 66.348%

Path13

Path Summary:

Slack	12.127
Data Arrival Time	11.615
Data Required Time	23.741
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_4_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.615	0.737	tNET	RR	1	R34C51[1][B]	gw_gao_inst_0/u_la0_top/word_count_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.052	2.688	tNET	RR	1	R34C51[1][B]	gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
23.741	-0.311	tSu		1	R34C51[1][B]	gw_gao_inst_0/u_la0_top/word_count_4_s0

Path Statistics:

Clock Skew	-0.018
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 39.006%; route: 4.219, 55.924%; tC2Q: 0.382, 5.070%
Required Clock Path Delay	cell: 1.365, 33.683%; route: 2.688, 66.317%

Path14

Path Summary:

Slack	12.127
Data Arrival Time	11.615
Data Required Time	23.741
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_11_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.615	0.737	tNET	RR	1	R34C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_11_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.052	2.688	tNET	RR	1	R34C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_11_s0/CLK
23.741	-0.311	tSu		1	R34C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_11_s0

Path Statistics:

Clock Skew	-0.018
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 39.006%; route: 4.219, 55.924%; tC2Q: 0.382, 5.070%
Required Clock Path Delay	cell: 1.365, 33.683%; route: 2.688, 66.317%

Path15

Path Summary:

Slack	12.127
Data Arrival Time	11.615
Data Required Time	23.741
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_12_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.615	0.737	tNET	RR	1	R34C51[0][B]	gw_gao_inst_0/u_la0_top/word_count_12_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.052	2.688	tNET	RR	1	R34C51[0][B]	gw_gao_inst_0/u_la0_top/word_count_12_s0/CLK
23.741	-0.311	tSu		1	R34C51[0][B]	gw_gao_inst_0/u_la0_top/word_count_12_s0

Path Statistics:

Clock Skew	-0.018
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 39.006%; route: 4.219, 55.924%; tC2Q: 0.382, 5.070%
Required Clock Path Delay	cell: 1.365, 33.683%; route: 2.688, 66.317%

Path16

Path Summary:

Slack	12.236
Data Arrival Time	11.507
Data Required Time	23.743
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_6_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.507	0.630	tNET	RR	1	R35C51[2][B]	gw_gao_inst_0/u_la0_top/word_count_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.054	2.689	tNET	RR	1	R35C51[2][B]	gw_gao_inst_0/u_la0_top/word_count_6_s0/CLK
23.743	-0.311	tSu		1	R35C51[2][B]	gw_gao_inst_0/u_la0_top/word_count_6_s0

Path Statistics:

Clock Skew	-0.017
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 39.570%; route: 4.111, 55.287%; tC2Q: 0.382, 5.144%
Required Clock Path Delay	cell: 1.365, 33.667%; route: 2.689, 66.333%

Path17

Path Summary:

Slack	12.236
Data Arrival Time	11.507
Data Required Time	23.743
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_7_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.507	0.630	tNET	RR	1	R35C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.054	2.689	tNET	RR	1	R35C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_7_s0/CLK
23.743	-0.311	tSu		1	R35C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_7_s0

Path Statistics:

Clock Skew	-0.017
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 39.570%; route: 4.111, 55.287%; tC2Q: 0.382, 5.144%
Required Clock Path Delay	cell: 1.365, 33.667%; route: 2.689, 66.333%

Path18

Path Summary:

Slack	12.245
Data Arrival Time	11.507
Data Required Time	23.753
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_0_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.507	0.630	tNET	RR	1	R35C52[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.064	2.699	tNET	RR	1	R35C52[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
23.753	-0.311	tSu		1	R35C52[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 39.570%; route: 4.111, 55.287%; tC2Q: 0.382, 5.144%
Required Clock Path Delay	cell: 1.365, 33.590%; route: 2.699, 66.410%

Path19

Path Summary:

Slack	12.245
Data Arrival Time	11.507
Data Required Time	23.753
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_1_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.507	0.630	tNET	RR	1	R35C52[0][B]	gw_gao_inst_0/u_la0_top/word_count_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.064	2.699	tNET	RR	1	R35C52[0][B]	gw_gao_inst_0/u_la0_top/word_count_1_s0/CLK
23.753	-0.311	tSu		1	R35C52[0][B]	gw_gao_inst_0/u_la0_top/word_count_1_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 39.570%; route: 4.111, 55.287%; tC2Q: 0.382, 5.144%
Required Clock Path Delay	cell: 1.365, 33.590%; route: 2.699, 66.410%

Path20

Path Summary:

Slack	12.245
Data Arrival Time	11.507
Data Required Time	23.753
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_2_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.507	0.630	tNET	RR	1	R35C52[1][B]	gw_gao_inst_0/u_la0_top/word_count_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.064	2.699	tNET	RR	1	R35C52[1][B]	gw_gao_inst_0/u_la0_top/word_count_2_s0/CLK
23.753	-0.311	tSu		1	R35C52[1][B]	gw_gao_inst_0/u_la0_top/word_count_2_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 39.570%; route: 4.111, 55.287%; tC2Q: 0.382, 5.144%
Required Clock Path Delay	cell: 1.365, 33.590%; route: 2.699, 66.410%

Path21

Path Summary:

Slack	12.245
Data Arrival Time	11.507
Data Required Time	23.753
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_3_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.507	0.630	tNET	RR	1	R35C52[1][A]	gw_gao_inst_0/u_la0_top/word_count_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.064	2.699	tNET	RR	1	R35C52[1][A]	gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK
23.753	-0.311	tSu		1	R35C52[1][A]	gw_gao_inst_0/u_la0_top/word_count_3_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 39.570%; route: 4.111, 55.287%; tC2Q: 0.382, 5.144%
Required Clock Path Delay	cell: 1.365, 33.590%; route: 2.699, 66.410%

Path22

Path Summary:

Slack	12.513
Data Arrival Time	11.230
Data Required Time	23.743
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_13_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.230	0.352	tNET	RR	1	R32C52[2][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.054	2.689	tNET	RR	1	R32C52[2][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
23.743	-0.311	tSu		1	R32C52[2][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0

Path Statistics:

Clock Skew	-0.017
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 41.104%; route: 3.834, 53.553%; tC2Q: 0.382, 5.343%
Required Clock Path Delay	cell: 1.365, 33.670%; route: 2.689, 66.330%

Path23

Path Summary:

Slack	12.513
Data Arrival Time	11.230
Data Required Time	23.743
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_14_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.230	0.352	tNET	RR	1	R32C52[3][A]	gw_gao_inst_0/u_la0_top/word_count_14_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.054	2.689	tNET	RR	1	R32C52[3][A]	gw_gao_inst_0/u_la0_top/word_count_14_s0/CLK
23.743	-0.311	tSu		1	R32C52[3][A]	gw_gao_inst_0/u_la0_top/word_count_14_s0

Path Statistics:

Clock Skew	-0.017
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 41.104%; route: 3.834, 53.553%; tC2Q: 0.382, 5.343%
Required Clock Path Delay	cell: 1.365, 33.670%; route: 2.689, 66.330%

Path24

Path Summary:

Slack	12.513
Data Arrival Time	11.230
Data Required Time	23.743
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/word_count_15_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.567	0.352	tNET	RR	1	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I3
10.028	0.461	tINS	RR	7	R30C51[2][A]	gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F
10.361	0.332	tNET	RR	1	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/I3
10.877	0.516	tINS	RR	16	R30C53[1][B]	gw_gao_inst_0/u_la0_top/word_ct_en_s23/F
11.230	0.352	tNET	RR	1	R32C52[2][B]	gw_gao_inst_0/u_la0_top/word_count_15_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.054	2.689	tNET	RR	1	R32C52[2][B]	gw_gao_inst_0/u_la0_top/word_count_15_s0/CLK
23.743	-0.311	tSu		1	R32C52[2][B]	gw_gao_inst_0/u_la0_top/word_count_15_s0

Path Statistics:

Clock Skew	-0.017
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.943, 41.104%; route: 3.834, 53.553%; tC2Q: 0.382, 5.343%
Required Clock Path Delay	cell: 1.365, 33.670%; route: 2.689, 66.330%

Path25

Path Summary:

Slack	12.700
Data Arrival Time	11.043
Data Required Time	23.743
From	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
To	gw_gao_inst_0/u_la0_top/address_counter_1_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
4.071	2.706	tNET	RR	1	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK
4.453	0.382	tC2Q	RR	2	R26C55[0][A]	gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q
5.112	0.659	tNET	RR	1	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/I0
5.573	0.461	tINS	RR	6	R26C50[0][A]	gw_gao_inst_0/u_la0_top/n20_s1/F
6.648	1.075	tNET	RR	1	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/I3
7.170	0.521	tINS	RR	35	R33C52[3][A]	gw_gao_inst_0/u_la0_top/op_reg_en_s4/F
8.230	1.060	tNET	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/I1
8.751	0.521	tINS	RR	1	R29C52[3][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s6/F
8.753	0.003	tNET	RR	1	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/I1
9.215	0.461	tINS	RR	3	R29C52[2][B]	gw_gao_inst_0/u_la0_top/bit_count_4_s5/F
9.377	0.162	tNET	RR	1	R30C52[2][B]	gw_gao_inst_0/u_la0_top/n684_s1/I2
9.893	0.516	tINS	RR	18	R30C52[2][B]	gw_gao_inst_0/u_la0_top/n684_s1/F
10.053	0.160	tNET	RR	1	R29C52[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s24/I1
10.515	0.461	tINS	RR	14	R29C52[1][B]	gw_gao_inst_0/u_la0_top/addr_ct_en_s24/F
11.043	0.529	tNET	RR	1	R27C50[2][A]	gw_gao_inst_0/u_la0_top/address_counter_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					tck_pad
20.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
20.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
20.683	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.365	0.683	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
24.054	2.689	tNET	RR	1	R27C50[2][A]	gw_gao_inst_0/u_la0_top/address_counter_1_s0/CLK
23.743	-0.311	tSu		1	R27C50[2][A]	gw_gao_inst_0/u_la0_top/address_counter_1_s0

Path Statistics:

Clock Skew	-0.017
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 1.365, 33.530%; route: 2.706, 66.470%
Arrival Data Path Delay	cell: 2.942, 42.201%; route: 3.648, 52.313%; tC2Q: 0.382, 5.486%
Required Clock Path Delay	cell: 1.365, 33.667%; route: 2.689, 66.333%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.184
Data Arrival Time	2.640
Data Required Time	2.456
From	gw_gao_inst_0/u_la0_top/address_counter_7_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.422	1.071	tNET	RR	1	R27C52[2][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0/CLK
2.563	0.141	tC2Q	RF	36	R27C52[2][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q
2.640	0.077	tNET	FF	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/ADB[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.421	1.070	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/CLKB
2.456	0.035	tHld		1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 55.780%; route: 1.071, 44.220%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.077, 35.321%; tC2Q: 0.141, 64.679%
Required Clock Path Delay	cell: 1.351, 55.815%; route: 1.070, 44.185%

Path2

Path Summary:

Slack	0.193
Data Arrival Time	1.609
Data Required Time	1.415
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.374	0.698	tNET	RR	1	R11C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/CLK
1.515	0.141	tC2Q	RF	1	R11C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q
1.609	0.094	tNET	FF	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s/CLKA
1.415	0.037	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path3

Path Summary:

Slack	0.195
Data Arrival Time	1.600
Data Required Time	1.406
From	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_1_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.365	0.690	tNET	RR	1	R11C27[0][B]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_1_s0/CLK
1.507	0.141	tC2Q	RF	1	R11C27[0][B]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_1_s0/Q
1.600	0.094	tNET	FF	1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/AD[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/CLK
1.406	0.035	tHld		1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path4

Path Summary:

Slack	0.199
Data Arrival Time	1.604
Data Required Time	1.406
From	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_2_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.369	0.694	tNET	RR	1	R11C26[1][B]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_2_s0/CLK
1.510	0.141	tC2Q	RF	1	R11C26[1][B]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_2_s0/Q
1.604	0.094	tNET	FF	1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/AD[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/CLK
1.406	0.035	tHld		1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path5

Path Summary:

Slack	0.216
Data Arrival Time	2.664
Data Required Time	2.448
From	gw_gao_inst_0/u_la0_top/address_counter_6_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.414	1.063	tNET	RR	1	R27C50[0][B]	gw_gao_inst_0/u_la0_top/address_counter_6_s0/CLK
2.558	0.144	tC2Q	RR	34	R27C50[0][B]	gw_gao_inst_0/u_la0_top/address_counter_6_s0/Q
2.664	0.106	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/ADB[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.413	1.062	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/CLKB
2.448	0.035	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 55.965%; route: 1.063, 44.035%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.106, 42.400%; tC2Q: 0.144, 57.600%
Required Clock Path Delay	cell: 1.351, 55.988%; route: 1.062, 44.012%

Path6

Path Summary:

Slack	0.222
Data Arrival Time	2.670
Data Required Time	2.448
From	gw_gao_inst_0/u_la0_top/address_counter_4_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.418	1.067	tNET	RR	1	R27C51[2][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK
2.562	0.144	tC2Q	RR	36	R27C51[2][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q
2.670	0.108	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/ADB[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.413	1.062	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/CLKB
2.448	0.035	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 55.873%; route: 1.067, 44.127%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.108, 42.857%; tC2Q: 0.144, 57.143%
Required Clock Path Delay	cell: 1.351, 55.988%; route: 1.062, 44.012%

Path7

Path Summary:

Slack	0.222
Data Arrival Time	1.627
Data Required Time	1.406
From	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_5_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.369	0.694	tNET	RR	1	R11C26[0][A]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_5_s0/CLK
1.510	0.141	tC2Q	RF	1	R11C26[0][A]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_5_s0/Q
1.627	0.117	tNET	FF	1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/AD[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/CLK
1.406	0.035	tHld		1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path8

Path Summary:

Slack	0.222
Data Arrival Time	1.627
Data Required Time	1.406
From	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_4_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.369	0.694	tNET	RR	1	R11C26[0][B]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_4_s0/CLK
1.510	0.141	tC2Q	RF	1	R11C26[0][B]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_4_s0/Q
1.627	0.117	tNET	FF	1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/AD[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/CLK
1.406	0.035	tHld		1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path9

Path Summary:

Slack	0.222
Data Arrival Time	1.627
Data Required Time	1.406
From	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_3_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.369	0.694	tNET	RR	1	R11C26[1][A]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_3_s0/CLK
1.510	0.141	tC2Q	RF	1	R11C26[1][A]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/cmem_addr_3_s0/Q
1.627	0.117	tNET	FF	1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/AD[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s/CLK
1.406	0.035	tHld		1	BSRAM_R10[7]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/coeff_mem_coeff_mem_0_0_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path10

Path Summary:

Slack	0.224
Data Arrival Time	2.672
Data Required Time	2.448
From	gw_gao_inst_0/u_la0_top/address_counter_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.422	1.071	tNET	RR	1	R27C52[0][B]	gw_gao_inst_0/u_la0_top/address_counter_0_s0/CLK
2.566	0.144	tC2Q	RR	37	R27C52[0][B]	gw_gao_inst_0/u_la0_top/address_counter_0_s0/Q
2.672	0.106	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/ADB[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.413	1.062	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/CLKB
2.448	0.035	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s

Path Statistics:

Clock Skew	-0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 55.780%; route: 1.071, 44.220%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.106, 42.400%; tC2Q: 0.144, 57.600%
Required Clock Path Delay	cell: 1.351, 55.988%; route: 1.062, 44.012%

Path11

Path Summary:

Slack	0.248
Data Arrival Time	1.660
Data Required Time	1.411
From	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_4_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/u0_sdpx9b_dmem
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.374	0.698	tNET	RR	1	R16C10[0][A]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_4_s0/CLK
1.518	0.144	tC2Q	RR	1	R16C10[0][A]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_4_s0/Q
1.660	0.142	tNET	RR	1	BSRAM_R28[1]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/u0_sdpx9b_dmem/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[1]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/u0_sdpx9b_dmem/CLKA
1.411	0.037	tHld		1	BSRAM_R28[1]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/u0_sdpx9b_dmem

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.172%; route: 0.698, 50.828%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.142, 49.650%; tC2Q: 0.144, 50.350%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path12

Path Summary:

Slack	0.249
Data Arrival Time	1.664
Data Required Time	1.415
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.380	0.705	tNET	RR	1	R18C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/CLK
1.524	0.144	tC2Q	RR	1	R18C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q
1.664	0.140	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/CLKA
1.415	0.037	tHld		1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.940%; route: 0.705, 51.060%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.140, 49.296%; tC2Q: 0.144, 50.704%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path13

Path Summary:

Slack	0.250
Data Arrival Time	1.661
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.369	0.694	tNET	RR	1	R29C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/CLK
1.510	0.141	tC2Q	RF	1	R29C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/Q
1.661	0.151	tNET	FF	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/CLKA
1.411	0.037	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.151, 51.712%; tC2Q: 0.141, 48.288%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path14

Path Summary:

Slack	0.252
Data Arrival Time	2.704
Data Required Time	2.452
From	gw_gao_inst_0/u_la0_top/address_counter_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.414	1.063	tNET	RR	1	R27C50[2][B]	gw_gao_inst_0/u_la0_top/address_counter_3_s0/CLK
2.558	0.144	tC2Q	RR	34	R27C50[2][B]	gw_gao_inst_0/u_la0_top/address_counter_3_s0/Q
2.704	0.146	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s/ADB[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.417	1.066	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s/CLKB
2.452	0.035	tHld		1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 55.965%; route: 1.063, 44.035%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.146, 50.345%; tC2Q: 0.144, 49.655%
Required Clock Path Delay	cell: 1.351, 55.896%; route: 1.066, 44.104%

Path15

Path Summary:

Slack	0.252
Data Arrival Time	1.664
Data Required Time	1.411
From	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_3_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/u0_sdpx9b_dmem
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R16C9[0][A]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_3_s0/CLK
1.522	0.144	tC2Q	RR	1	R16C9[0][A]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_3_s0/Q
1.664	0.142	tNET	RR	1	BSRAM_R28[1]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/u0_sdpx9b_dmem/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[1]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/u0_sdpx9b_dmem/CLKA
1.411	0.037	tHld		1	BSRAM_R28[1]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/u0_sdpx9b_dmem

Path Statistics:

Clock Skew	-0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.142, 49.650%; tC2Q: 0.144, 50.350%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path16

Path Summary:

Slack	0.261
Data Arrival Time	2.709
Data Required Time	2.448
From	gw_gao_inst_0/u_la0_top/address_counter_9_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.418	1.067	tNET	RR	1	R27C51[0][B]	gw_gao_inst_0/u_la0_top/address_counter_9_s0/CLK
2.562	0.144	tC2Q	RR	34	R27C51[0][B]	gw_gao_inst_0/u_la0_top/address_counter_9_s0/Q
2.709	0.147	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/ADB[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.413	1.062	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/CLKB
2.448	0.035	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 55.873%; route: 1.067, 44.127%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.147, 50.515%; tC2Q: 0.144, 49.485%
Required Clock Path Delay	cell: 1.351, 55.988%; route: 1.062, 44.012%

Path17

Path Summary:

Slack	0.261
Data Arrival Time	1.668
Data Required Time	1.408
From	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_19_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/gowin_add_SDPX9B_u0_sdpx9b_dmem
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.369	0.694	tNET	RR	1	R11C24[1][A]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_19_s0/CLK
1.510	0.141	tC2Q	RF	1	R11C24[1][A]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_19_s0/Q
1.668	0.158	tNET	FF	1	BSRAM_R10[6]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/gowin_add_SDPX9B_u0_sdpx9b_dmem/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R10[6]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/gowin_add_SDPX9B_u0_sdpx9b_dmem/CLKA
1.408	0.037	tHld		1	BSRAM_R10[6]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/gowin_add_SDPX9B_u0_sdpx9b_dmem

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.158, 52.843%; tC2Q: 0.141, 47.157%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path18

Path Summary:

Slack	0.261
Data Arrival Time	1.668
Data Required Time	1.408
From	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_18_s0
To	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/gowin_add_SDPX9B_u0_sdpx9b_dmem
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.369	0.694	tNET	RR	1	R11C24[1][B]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_18_s0/CLK
1.510	0.141	tC2Q	RF	1	R11C24[1][B]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/in_data_r_18_s0/Q
1.668	0.158	tNET	FF	1	BSRAM_R10[6]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/gowin_add_SDPX9B_u0_sdpx9b_dmem/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R10[6]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/gowin_add_SDPX9B_u0_sdpx9b_dmem/CLKA
1.408	0.037	tHld		1	BSRAM_R10[6]	u_PDM2PCM_Top/u_pdm2pcm/u0_cic_cmp/gowin_add_SDPX9B_u0_sdpx9b_dmem

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.158, 52.843%; tC2Q: 0.141, 47.157%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path19

Path Summary:

Slack	0.271
Data Arrival Time	2.715
Data Required Time	2.444
From	gw_gao_inst_0/u_la0_top/address_counter_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_23_s
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.403	1.052	tNET	RR	1	R30C52[0][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/CLK
2.544	0.141	tC2Q	RF	36	R30C52[0][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q
2.715	0.171	tNET	FF	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_23_s/ADB[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.409	1.058	tNET	RR	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_23_s/CLKB
2.444	0.035	tHld		1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_23_s

Path Statistics:

Clock Skew	0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 56.221%; route: 1.052, 43.779%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.171, 54.808%; tC2Q: 0.141, 45.192%
Required Clock Path Delay	cell: 1.351, 56.081%; route: 1.058, 43.919%

Path20

Path Summary:

Slack	0.274
Data Arrival Time	2.722
Data Required Time	2.448
From	gw_gao_inst_0/u_la0_top/address_counter_12_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.403	1.052	tNET	RR	1	R30C52[1][B]	gw_gao_inst_0/u_la0_top/address_counter_12_s0/CLK
2.544	0.141	tC2Q	RF	34	R30C52[1][B]	gw_gao_inst_0/u_la0_top/address_counter_12_s0/Q
2.722	0.178	tNET	FF	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/ADB[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.413	1.062	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s/CLKB
2.448	0.035	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_21_s

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 56.221%; route: 1.052, 43.779%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.178, 55.799%; tC2Q: 0.141, 44.201%
Required Clock Path Delay	cell: 1.351, 55.988%; route: 1.062, 44.012%

Path21

Path Summary:

Slack	0.275
Data Arrival Time	2.714
Data Required Time	2.439
From	gw_gao_inst_0/u_la0_top/word_count_7_s0
To	gw_gao_inst_0/u_la0_top/word_count_7_s0
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.414	1.063	tNET	RR	1	R35C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_7_s0/CLK
2.555	0.141	tC2Q	RF	2	R35C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_7_s0/Q
2.561	0.006	tNET	FF	1	R35C51[1][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_7_s0/I2
2.714	0.153	tINS	FF	1	R35C51[1][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_7_s0/F
2.714	0.000	tNET	FF	1	R35C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	305	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.414	1.063	tNET	RR	1	R35C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_7_s0/CLK
2.439	0.025	tHld		1	R35C51[1][A]	gw_gao_inst_0/u_la0_top/word_count_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.977%; route: 1.063, 44.023%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 55.977%; route: 1.063, 44.023%

Path22

Path Summary:

Slack	0.275
Data Arrival Time	1.678
Data Required Time	1.403
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
1.519	0.141	tC2Q	RF	6	R34C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/Q
1.525	0.006	tNET	FF	1	R34C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n298_s2/I1
1.678	0.153	tINS	FF	1	R34C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n298_s2/F
1.678	0.000	tNET	FF	1	R34C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
1.403	0.025	tHld		1	R34C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Path23

Path Summary:

Slack	0.275
Data Arrival Time	1.679
Data Required Time	1.404
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.379	0.704	tNET	RR	1	R35C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
1.520	0.141	tC2Q	RF	3	R35C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/Q
1.526	0.006	tNET	FF	1	R35C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n292_s0/I2
1.679	0.153	tINS	FF	1	R35C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n292_s0/F
1.679	0.000	tNET	FF	1	R35C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.379	0.704	tNET	RR	1	R35C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
1.404	0.025	tHld		1	R35C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 48.985%; route: 0.704, 51.015%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 48.985%; route: 0.704, 51.015%

Path24

Path Summary:

Slack	0.275
Data Arrival Time	1.678
Data Required Time	1.403
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
1.519	0.141	tC2Q	RF	4	R34C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q
1.525	0.006	tNET	FF	1	R34C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n291_s0/I1
1.678	0.153	tINS	FF	1	R34C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n291_s0/F
1.678	0.000	tNET	FF	1	R34C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
1.403	0.025	tHld		1	R34C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Path25

Path Summary:

Slack	0.275
Data Arrival Time	1.674
Data Required Time	1.399
From	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.374	0.698	tNET	RR	1	R34C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK
1.515	0.141	tC2Q	RF	5	R34C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/Q
1.521	0.006	tNET	FF	1	R34C56[0][A]	gw_gao_inst_0/u_la0_top/n2071_s1/I1
1.674	0.153	tINS	FF	1	R34C56[0][A]	gw_gao_inst_0/u_la0_top/n2071_s1/F
1.674	0.000	tNET	FF	1	R34C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.374	0.698	tNET	RR	1	R34C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK
1.399	0.025	tHld		1	R34C56[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.172%; route: 0.698, 50.828%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.172%; route: 0.698, 50.828%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	7.024
Data Arrival Time	15.209
Data Required Time	22.233
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.209	2.166	tNET	FF	1	R30C55[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.581	1.898	tNET	RR	1	R30C55[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLK
22.233	-0.347	tSu		1	R30C55[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0

Path Statistics:

Clock Skew	-0.020
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.166, 83.034%; tC2Q: 0.442, 16.966%
Required Clock Path Delay	cell: 0.683, 26.444%; route: 1.898, 73.556%

Path2

Path Summary:

Slack	7.024
Data Arrival Time	15.215
Data Required Time	22.239
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.215	2.172	tNET	FF	1	R31C55[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.587	1.904	tNET	RR	1	R31C55[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLK
22.239	-0.347	tSu		1	R31C55[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.172, 83.072%; tC2Q: 0.442, 16.928%
Required Clock Path Delay	cell: 0.683, 26.383%; route: 1.904, 73.617%

Path3

Path Summary:

Slack	7.024
Data Arrival Time	15.215
Data Required Time	22.239
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.215	2.172	tNET	FF	1	R31C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.587	1.904	tNET	RR	1	R31C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLK
22.239	-0.347	tSu		1	R31C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.172, 83.072%; tC2Q: 0.442, 16.928%
Required Clock Path Delay	cell: 0.683, 26.383%; route: 1.904, 73.617%

Path4

Path Summary:

Slack	7.028
Data Arrival Time	15.225
Data Required Time	22.253
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.225	2.181	tNET	FF	1	R34C55[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.601	1.918	tNET	RR	1	R34C55[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
22.253	-0.347	tSu		1	R34C55[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	-0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.181, 83.135%; tC2Q: 0.442, 16.865%
Required Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%

Path5

Path Summary:

Slack	7.028
Data Arrival Time	15.225
Data Required Time	22.253
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.225	2.181	tNET	FF	1	R34C55[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.601	1.918	tNET	RR	1	R34C55[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
22.253	-0.347	tSu		1	R34C55[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.181, 83.135%; tC2Q: 0.442, 16.865%
Required Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%

Path6

Path Summary:

Slack	7.028
Data Arrival Time	15.229
Data Required Time	22.257
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_13_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.229	2.185	tNET	FF	1	R36C55[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_13_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.604	1.922	tNET	RR	1	R36C55[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_13_s1/CLK
22.257	-0.347	tSu		1	R36C55[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_13_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.185, 83.159%; tC2Q: 0.442, 16.841%
Required Clock Path Delay	cell: 0.683, 26.206%; route: 1.922, 73.794%

Path7

Path Summary:

Slack	7.028
Data Arrival Time	15.225
Data Required Time	22.253
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.225	2.181	tNET	FF	1	R34C55[1][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.601	1.918	tNET	RR	1	R34C55[1][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
22.253	-0.347	tSu		1	R34C55[1][B]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.181, 83.135%; tC2Q: 0.442, 16.865%
Required Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%

Path8

Path Summary:

Slack	7.028
Data Arrival Time	15.223
Data Required Time	22.251
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.223	2.179	tNET	FF	1	R33C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.599	1.916	tNET	RR	1	R33C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK
22.251	-0.347	tSu		1	R33C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.179, 83.123%; tC2Q: 0.442, 16.877%
Required Clock Path Delay	cell: 0.683, 26.263%; route: 1.916, 73.737%

Path9

Path Summary:

Slack	7.028
Data Arrival Time	15.223
Data Required Time	22.251
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.223	2.179	tNET	FF	1	R33C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.599	1.916	tNET	RR	1	R33C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
22.251	-0.347	tSu		1	R33C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.179, 83.123%; tC2Q: 0.442, 16.877%
Required Clock Path Delay	cell: 0.683, 26.263%; route: 1.916, 73.737%

Path10

Path Summary:

Slack	7.028
Data Arrival Time	15.227
Data Required Time	22.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.227	2.183	tNET	FF	1	R35C55[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.603	1.920	tNET	RR	1	R35C55[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
22.255	-0.347	tSu		1	R35C55[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.183, 83.147%; tC2Q: 0.442, 16.853%
Required Clock Path Delay	cell: 0.683, 26.225%; route: 1.920, 73.775%

Path11

Path Summary:

Slack	7.028
Data Arrival Time	15.223
Data Required Time	22.251
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.223	2.179	tNET	FF	1	R33C55[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.599	1.916	tNET	RR	1	R33C55[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
22.251	-0.347	tSu		1	R33C55[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.179, 83.123%; tC2Q: 0.442, 16.877%
Required Clock Path Delay	cell: 0.683, 26.263%; route: 1.916, 73.737%

Path12

Path Summary:

Slack	7.033
Data Arrival Time	15.209
Data Required Time	22.243
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.209	2.166	tNET	FF	1	R30C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.590	1.908	tNET	RR	1	R30C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLK
22.243	-0.347	tSu		1	R30C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.166, 83.034%; tC2Q: 0.442, 16.966%
Required Clock Path Delay	cell: 0.683, 26.348%; route: 1.908, 73.652%

Path13

Path Summary:

Slack	7.033
Data Arrival Time	15.215
Data Required Time	22.249
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.215	2.172	tNET	FF	1	R31C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.596	1.914	tNET	RR	1	R31C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLK
22.249	-0.347	tSu		1	R31C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0

Path Statistics:

Clock Skew	-0.005
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.172, 83.072%; tC2Q: 0.442, 16.928%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path14

Path Summary:

Slack	7.033
Data Arrival Time	15.215
Data Required Time	22.249
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.215	2.172	tNET	FF	1	R31C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.596	1.914	tNET	RR	1	R31C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLK
22.249	-0.347	tSu		1	R31C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0

Path Statistics:

Clock Skew	-0.005
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.172, 83.072%; tC2Q: 0.442, 16.928%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path15

Path Summary:

Slack	7.033
Data Arrival Time	15.209
Data Required Time	22.243
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.209	2.166	tNET	FF	1	R30C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.590	1.908	tNET	RR	1	R30C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0/CLK
22.243	-0.347	tSu		1	R30C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.166, 83.034%; tC2Q: 0.442, 16.966%
Required Clock Path Delay	cell: 0.683, 26.348%; route: 1.908, 73.652%

Path16

Path Summary:

Slack	7.033
Data Arrival Time	15.209
Data Required Time	22.243
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.209	2.166	tNET	FF	1	R30C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.590	1.908	tNET	RR	1	R30C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLK
22.243	-0.347	tSu		1	R30C56[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.166, 83.034%; tC2Q: 0.442, 16.966%
Required Clock Path Delay	cell: 0.683, 26.348%; route: 1.908, 73.652%

Path17

Path Summary:

Slack	7.033
Data Arrival Time	15.215
Data Required Time	22.249
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.215	2.172	tNET	FF	1	R31C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.596	1.914	tNET	RR	1	R31C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLK
22.249	-0.347	tSu		1	R31C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0

Path Statistics:

Clock Skew	-0.005
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.172, 83.072%; tC2Q: 0.442, 16.928%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path18

Path Summary:

Slack	7.033
Data Arrival Time	15.215
Data Required Time	22.249
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_9_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.215	2.172	tNET	FF	1	R31C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.596	1.914	tNET	RR	1	R31C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_9_s0/CLK
22.249	-0.347	tSu		1	R31C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_9_s0

Path Statistics:

Clock Skew	-0.005
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.172, 83.072%; tC2Q: 0.442, 16.928%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path19

Path Summary:

Slack	7.033
Data Arrival Time	15.221
Data Required Time	22.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.221	2.178	tNET	FF	1	R32C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.602	1.920	tNET	RR	1	R32C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
22.255	-0.347	tSu		1	R32C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.178, 83.111%; tC2Q: 0.442, 16.889%
Required Clock Path Delay	cell: 0.683, 26.228%; route: 1.920, 73.772%

Path20

Path Summary:

Slack	7.033
Data Arrival Time	15.221
Data Required Time	22.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.221	2.178	tNET	FF	1	R32C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.602	1.920	tNET	RR	1	R32C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
22.255	-0.347	tSu		1	R32C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.178, 83.111%; tC2Q: 0.442, 16.889%
Required Clock Path Delay	cell: 0.683, 26.228%; route: 1.920, 73.772%

Path21

Path Summary:

Slack	7.033
Data Arrival Time	15.221
Data Required Time	22.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.221	2.178	tNET	FF	1	R32C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.602	1.920	tNET	RR	1	R32C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
22.255	-0.347	tSu		1	R32C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.178, 83.111%; tC2Q: 0.442, 16.889%
Required Clock Path Delay	cell: 0.683, 26.228%; route: 1.920, 73.772%

Path22

Path Summary:

Slack	7.033
Data Arrival Time	15.221
Data Required Time	22.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.221	2.178	tNET	FF	1	R32C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.602	1.920	tNET	RR	1	R32C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLK
22.255	-0.347	tSu		1	R32C54[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.178, 83.111%; tC2Q: 0.442, 16.889%
Required Clock Path Delay	cell: 0.683, 26.228%; route: 1.920, 73.772%

Path23

Path Summary:

Slack	7.033
Data Arrival Time	15.221
Data Required Time	22.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.221	2.178	tNET	FF	1	R32C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.602	1.920	tNET	RR	1	R32C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLK
22.255	-0.347	tSu		1	R32C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.178, 83.111%; tC2Q: 0.442, 16.889%
Required Clock Path Delay	cell: 0.683, 26.228%; route: 1.920, 73.772%

Path24

Path Summary:

Slack	7.033
Data Arrival Time	15.221
Data Required Time	22.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.221	2.178	tNET	FF	1	R32C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.602	1.920	tNET	RR	1	R32C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
22.255	-0.347	tSu		1	R32C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.178, 83.111%; tC2Q: 0.442, 16.889%
Required Clock Path Delay	cell: 0.683, 26.228%; route: 1.920, 73.772%

Path25

Path Summary:

Slack	7.033
Data Arrival Time	15.221
Data Required Time	22.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
12.601	1.914	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.044	0.442	tC2Q	FF	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.221	2.178	tNET	FF	1	R32C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
22.602	1.920	tNET	RR	1	R32C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK
22.255	-0.347	tSu		1	R32C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.178, 83.111%; tC2Q: 0.442, 16.889%
Required Clock Path Delay	cell: 0.683, 26.228%; route: 1.920, 73.772%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	11.102
Data Arrival Time	12.426
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.426	0.894	tNET	RR	1	R33C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.377	0.701	tNET	RR	1	R33C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
1.324	-0.053	tHld		1	R33C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.894, 84.985%; tC2Q: 0.158, 15.015%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path2

Path Summary:

Slack	11.102
Data Arrival Time	12.426
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.426	0.894	tNET	RR	1	R33C45[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.377	0.701	tNET	RR	1	R33C45[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.324	-0.053	tHld		1	R33C45[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.894, 84.985%; tC2Q: 0.158, 15.015%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path3

Path Summary:

Slack	11.102
Data Arrival Time	12.426
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.426	0.894	tNET	RR	1	R33C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.377	0.701	tNET	RR	1	R33C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
1.324	-0.053	tHld		1	R33C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.894, 84.985%; tC2Q: 0.158, 15.015%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path4

Path Summary:

Slack	11.102
Data Arrival Time	12.426
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.426	0.894	tNET	RR	1	R33C45[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.377	0.701	tNET	RR	1	R33C45[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
1.324	-0.053	tHld		1	R33C45[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.894, 84.985%; tC2Q: 0.158, 15.015%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path5

Path Summary:

Slack	11.102
Data Arrival Time	12.426
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.426	0.894	tNET	RR	1	R33C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.377	0.701	tNET	RR	1	R33C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.324	-0.053	tHld		1	R33C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.894, 84.985%; tC2Q: 0.158, 15.015%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path6

Path Summary:

Slack	11.102
Data Arrival Time	12.427
Data Required Time	1.325
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.427	0.896	tNET	RR	1	R34C45[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C45[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
1.325	-0.053	tHld		1	R34C45[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.896, 85.002%; tC2Q: 0.158, 14.998%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Path7

Path Summary:

Slack	11.102
Data Arrival Time	12.427
Data Required Time	1.325
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.427	0.896	tNET	RR	1	R34C45[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C45[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLK
1.325	-0.053	tHld		1	R34C45[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.896, 85.002%; tC2Q: 0.158, 14.998%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Path8

Path Summary:

Slack	11.102
Data Arrival Time	12.427
Data Required Time	1.325
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_13_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.427	0.896	tNET	RR	1	R34C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_13_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_13_s1/CLK
1.325	-0.053	tHld		1	R34C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_13_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.896, 85.002%; tC2Q: 0.158, 14.998%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Path9

Path Summary:

Slack	11.102
Data Arrival Time	12.427
Data Required Time	1.325
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.427	0.896	tNET	RR	1	R34C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
1.325	-0.053	tHld		1	R34C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.896, 85.002%; tC2Q: 0.158, 14.998%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Path10

Path Summary:

Slack	11.102
Data Arrival Time	12.426
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.426	0.894	tNET	RR	1	R33C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.377	0.701	tNET	RR	1	R33C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
1.324	-0.053	tHld		1	R33C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.894, 84.985%; tC2Q: 0.158, 15.015%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path11

Path Summary:

Slack	11.102
Data Arrival Time	12.427
Data Required Time	1.325
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.427	0.896	tNET	RR	1	R34C41[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C41[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
1.325	-0.053	tHld		1	R34C41[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.896, 85.002%; tC2Q: 0.158, 14.998%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Path12

Path Summary:

Slack	11.102
Data Arrival Time	12.427
Data Required Time	1.325
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.427	0.896	tNET	RR	1	R34C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
1.325	-0.053	tHld		1	R34C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.896, 85.002%; tC2Q: 0.158, 14.998%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Path13

Path Summary:

Slack	11.102
Data Arrival Time	12.427
Data Required Time	1.325
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.427	0.896	tNET	RR	1	R34C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
1.325	-0.053	tHld		1	R34C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.896, 85.002%; tC2Q: 0.158, 14.998%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Path14

Path Summary:

Slack	11.102
Data Arrival Time	12.426
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.426	0.894	tNET	RR	1	R33C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.377	0.701	tNET	RR	1	R33C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLK
1.324	-0.053	tHld		1	R33C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.894, 84.985%; tC2Q: 0.158, 15.015%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path15

Path Summary:

Slack	11.102
Data Arrival Time	12.429
Data Required Time	1.327
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_12_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.429	0.898	tNET	RR	1	R36C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_12_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.380	0.705	tNET	RR	1	R36C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_12_s1/CLK
1.327	-0.053	tHld		1	R36C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_12_s1

Path Statistics:

Clock Skew	0.007
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.898, 85.038%; tC2Q: 0.158, 14.962%
Required Clock Path Delay	cell: 0.675, 48.940%; route: 0.705, 51.060%

Path16

Path Summary:

Slack	11.102
Data Arrival Time	12.429
Data Required Time	1.327
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_13_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.429	0.898	tNET	RR	1	R36C41[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_13_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.380	0.705	tNET	RR	1	R36C41[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_13_s1/CLK
1.327	-0.053	tHld		1	R36C41[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_13_s1

Path Statistics:

Clock Skew	0.007
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.898, 85.038%; tC2Q: 0.158, 14.962%
Required Clock Path Delay	cell: 0.675, 48.940%; route: 0.705, 51.060%

Path17

Path Summary:

Slack	11.102
Data Arrival Time	12.427
Data Required Time	1.325
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.427	0.896	tNET	RR	1	R34C57[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C57[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.325	-0.053	tHld		1	R34C57[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.896, 85.002%; tC2Q: 0.158, 14.998%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Path18

Path Summary:

Slack	11.102
Data Arrival Time	12.427
Data Required Time	1.325
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.427	0.896	tNET	RR	1	R34C57[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C57[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.325	-0.053	tHld		1	R34C57[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.896, 85.002%; tC2Q: 0.158, 14.998%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Path19

Path Summary:

Slack	11.102
Data Arrival Time	12.427
Data Required Time	1.325
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.427	0.896	tNET	RR	1	R34C53[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C53[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
1.325	-0.053	tHld		1	R34C53[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.896, 85.002%; tC2Q: 0.158, 14.998%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Path20

Path Summary:

Slack	11.102
Data Arrival Time	12.427
Data Required Time	1.325
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.427	0.896	tNET	RR	1	R34C53[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.378	0.702	tNET	RR	1	R34C53[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
1.325	-0.053	tHld		1	R34C53[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.896, 85.002%; tC2Q: 0.158, 14.998%
Required Clock Path Delay	cell: 0.675, 49.029%; route: 0.702, 50.971%

Path21

Path Summary:

Slack	11.102
Data Arrival Time	12.428
Data Required Time	1.326
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.428	0.897	tNET	RR	1	R35C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.379	0.704	tNET	RR	1	R35C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK
1.326	-0.053	tHld		1	R35C45[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1

Path Statistics:

Clock Skew	0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.897, 85.020%; tC2Q: 0.158, 14.980%
Required Clock Path Delay	cell: 0.675, 48.985%; route: 0.704, 51.015%

Path22

Path Summary:

Slack	11.102
Data Arrival Time	12.428
Data Required Time	1.326
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.428	0.897	tNET	RR	1	R35C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.379	0.704	tNET	RR	1	R35C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
1.326	-0.053	tHld		1	R35C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.897, 85.020%; tC2Q: 0.158, 14.980%
Required Clock Path Delay	cell: 0.675, 48.985%; route: 0.704, 51.015%

Path23

Path Summary:

Slack	11.102
Data Arrival Time	12.428
Data Required Time	1.326
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.428	0.897	tNET	RR	1	R35C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.379	0.704	tNET	RR	1	R35C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
1.326	-0.053	tHld		1	R35C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.897, 85.020%; tC2Q: 0.158, 14.980%
Required Clock Path Delay	cell: 0.675, 48.985%; route: 0.704, 51.015%

Path24

Path Summary:

Slack	11.102
Data Arrival Time	12.428
Data Required Time	1.326
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.428	0.897	tNET	RR	1	R35C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.379	0.704	tNET	RR	1	R35C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
1.326	-0.053	tHld		1	R35C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.897, 85.020%; tC2Q: 0.158, 14.980%
Required Clock Path Delay	cell: 0.675, 48.985%; route: 0.704, 51.015%

Path25

Path Summary:

Slack	11.102
Data Arrival Time	12.428
Data Required Time	1.326
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	2321	IOB29[A]	SYM_CLK_ibuf/O
11.373	0.696	tNET	FF	1	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.531	0.158	tC2Q	FR	93	R33C55[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.428	0.897	tNET	RR	1	R35C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	2321	IOB29[A]	SYM_CLK_ibuf/O
1.379	0.704	tNET	RR	1	R35C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.326	-0.053	tHld		1	R35C45[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.327%; route: 0.696, 50.673%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.897, 85.020%; tC2Q: 0.158, 14.980%
Required Clock Path Delay	cell: 0.675, 48.985%; route: 0.704, 51.015%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	7.356
Actual Width:	8.356
Required Width:	1.000
Type:	Low Pulse Width
Clock:	tck_pad
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_16_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			tck_pad
10.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
10.688	0.688	tINS	FF	gw_gao_inst_0/tck_ibuf/O
10.688	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
11.375	0.688	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
14.064	2.689	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_16_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			tck_pad
20.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
20.676	0.675	tINS	RR	gw_gao_inst_0/tck_ibuf/O
20.676	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.351	0.675	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
22.420	1.070	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_16_s/CLKB

MPW2

MPW Summary:

Slack:	7.356
Actual Width:	8.356
Required Width:	1.000
Type:	Low Pulse Width
Clock:	tck_pad
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			tck_pad
10.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
10.688	0.688	tINS	FF	gw_gao_inst_0/tck_ibuf/O
10.688	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
11.375	0.688	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
14.064	2.689	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			tck_pad
20.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
20.676	0.675	tINS	RR	gw_gao_inst_0/tck_ibuf/O
20.676	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.351	0.675	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
22.420	1.070	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/CLKB

MPW3

MPW Summary:

Slack:	7.362
Actual Width:	8.362
Required Width:	1.000
Type:	Low Pulse Width
Clock:	tck_pad
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			tck_pad
10.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
10.688	0.688	tINS	FF	gw_gao_inst_0/tck_ibuf/O
10.688	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
11.375	0.688	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
14.055	2.680	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			tck_pad
20.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
20.676	0.675	tINS	RR	gw_gao_inst_0/tck_ibuf/O
20.676	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.351	0.675	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
22.417	1.066	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKB

MPW4

MPW Summary:

Slack:	7.362
Actual Width:	8.362
Required Width:	1.000
Type:	Low Pulse Width
Clock:	tck_pad
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			tck_pad
10.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
10.688	0.688	tINS	FF	gw_gao_inst_0/tck_ibuf/O
10.688	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
11.375	0.688	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
14.055	2.680	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			tck_pad
20.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
20.676	0.675	tINS	RR	gw_gao_inst_0/tck_ibuf/O
20.676	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.351	0.675	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
22.417	1.066	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKB

MPW5

MPW Summary:

Slack:	7.362
Actual Width:	8.362
Required Width:	1.000
Type:	Low Pulse Width
Clock:	tck_pad
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			tck_pad
10.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
10.688	0.688	tINS	FF	gw_gao_inst_0/tck_ibuf/O
10.688	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
11.375	0.688	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
14.055	2.680	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			tck_pad
20.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
20.676	0.675	tINS	RR	gw_gao_inst_0/tck_ibuf/O
20.676	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.351	0.675	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
22.417	1.066	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/CLKB

MPW6

MPW Summary:

Slack:	7.362
Actual Width:	8.362
Required Width:	1.000
Type:	Low Pulse Width
Clock:	tck_pad
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_11_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			tck_pad
10.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
10.688	0.688	tINS	FF	gw_gao_inst_0/tck_ibuf/O
10.688	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
11.375	0.688	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
14.055	2.680	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_11_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			tck_pad
20.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
20.676	0.675	tINS	RR	gw_gao_inst_0/tck_ibuf/O
20.676	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.351	0.675	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
22.417	1.066	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_11_s/CLKB

MPW7

MPW Summary:

Slack:	7.362
Actual Width:	8.362
Required Width:	1.000
Type:	Low Pulse Width
Clock:	tck_pad
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			tck_pad
10.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
10.688	0.688	tINS	FF	gw_gao_inst_0/tck_ibuf/O
10.688	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
11.375	0.688	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
14.055	2.680	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			tck_pad
20.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
20.676	0.675	tINS	RR	gw_gao_inst_0/tck_ibuf/O
20.676	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.351	0.675	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
22.417	1.066	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s/CLKB

MPW8

MPW Summary:

Slack:	7.362
Actual Width:	8.362
Required Width:	1.000
Type:	Low Pulse Width
Clock:	tck_pad
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			tck_pad
10.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
10.688	0.688	tINS	FF	gw_gao_inst_0/tck_ibuf/O
10.688	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
11.375	0.688	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
14.055	2.680	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			tck_pad
20.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
20.676	0.675	tINS	RR	gw_gao_inst_0/tck_ibuf/O
20.676	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.351	0.675	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
22.417	1.066	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s/CLKB

MPW9

MPW Summary:

Slack:	7.362
Actual Width:	8.362
Required Width:	1.000
Type:	Low Pulse Width
Clock:	tck_pad
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_26_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			tck_pad
10.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
10.688	0.688	tINS	FF	gw_gao_inst_0/tck_ibuf/O
10.688	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
11.375	0.688	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
14.055	2.680	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_26_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			tck_pad
20.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
20.676	0.675	tINS	RR	gw_gao_inst_0/tck_ibuf/O
20.676	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.351	0.675	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
22.417	1.066	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_26_s/CLKB

MPW10

MPW Summary:

Slack:	7.362
Actual Width:	8.362
Required Width:	1.000
Type:	Low Pulse Width
Clock:	tck_pad
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_30_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			tck_pad
10.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
10.688	0.688	tINS	FF	gw_gao_inst_0/tck_ibuf/O
10.688	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
11.375	0.688	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
14.055	2.680	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_30_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			tck_pad
20.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
20.676	0.675	tINS	RR	gw_gao_inst_0/tck_ibuf/O
20.676	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
21.351	0.675	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
22.417	1.066	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_30_s/CLKB

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
2321	SYM_CLK_d	5.710	1.975
834	drom_addr[10]	8.278	2.862
603	drom_addr[9]	9.937	2.884
457	drom_addr[11]	6.714	2.802
416	drom_addr[13]	6.325	2.743
407	drom_addr[12]	5.710	3.296
305	gw_gao_inst_0/control0[0]	11.734	2.717
268	drom_addr[8]	7.272	3.137
165	drom_addr[7]	8.489	2.429
131	u_PDM2PCM_Top/u_pdm2pcm/series_sync0	14.460	2.702

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C7	100.00%
R2C9	100.00%
R2C10	100.00%
R2C42	100.00%
R3C16	100.00%
R13C56	100.00%
R25C51	100.00%
R25C45	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk1 -period 20 -waveform {0 10} [get_ports {SYM_CLK}]
TC_CLOCK	Actived	create_clock -name tck_pad -period 20 -waveform {0 10} [get_ports {tck_pad_i}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clk1}] -group [get_clocks {tck_pad}]