Synthesis Messages

Report Title	GowinSynthesis Report
Design File	D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\PSRAM_HS\psram_hs_2ch\PSRAM_TOP.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\PSRAM_HS\psram_hs_2ch\psram_code.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.12.02 (64-bit)
Part Number	GW1NR-LV9LQ144PC6/I5
Device	GW1NR-9
Device Version	C
Created Time	Wed Mar 4 09:39:23 2026
Legal Announcement	Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	PSRAM_Memory_Interface_HS_Top
Synthesis Process	Running parser: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.359s, Peak memory usage = 81.551MB Running netlist conversion: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 81.551MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.249s, Peak memory usage = 81.551MB Optimizing Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.155s, Peak memory usage = 81.551MB Optimizing Phase 2: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.291s, Peak memory usage = 81.551MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.177s, Peak memory usage = 81.551MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 81.551MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 81.551MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 81.551MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.282s, Peak memory usage = 81.551MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 81.551MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 81.551MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 110.074MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.567s, Peak memory usage = 110.074MB Generate output files: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.171s, Peak memory usage = 110.074MB
Total Time and Memory Usage	CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 110.074MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	193
Embedded Port	26
I/O Buf	218
IBUF	122
OBUF	77
IOBUF	18
ELVDS_OBUF	1
Register	1028
DFF	2
DFFSE	12
DFFRE	2
DFFP	8
DFFPE	6
DFFC	661
DFFCE	337
LUT	1555
LUT2	352
LUT3	504
LUT4	699
ALU	101
ALU	101
INV	11
INV	11
IOLOGIC	62
IDES4	18
OSER4	23
IODELAY	21
BSRAM	4
SDPB	2
SDPX9B	2
CLOCK	2
CLKDIV	1
DHCEN	1

Resource Utilization Summary

Resource	Usage	Utilization
Logic	1667(1566 LUT, 101 ALU) / 8640	20%
Register	1028 / 6921	15%
--Register as Latch	0 / 6921	0%
--Register as FF	1028 / 6921	15%
BSRAM	4 / 26	16%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Fall	Source	Master	Object
1	memory_clk	Base	20.000	50.000	10.000			memory_clk_ibuf/I
2	clk	Base	20.000	50.000	10.000			clk_ibuf/I
3	clkdiv/CLKOUT.default_gen_clk	Generated	40.000	25.000	20.000	memory_clk_ibuf/I	memory_clk	clkdiv/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	90.087(MHz)	6	TOP
2	clkdiv/CLKOUT.default_gen_clk	25.000(MHz)	66.408(MHz)	9	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	8.532
Data Arrival Time	2.144
Data Required Time	10.676
From	u_psram_sync/cs_memsync_4_s0
To	u_dhcen_clk_x2
Launch Clk	clk[R]
Latch Clk	memory_clk[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	31	clk_ibuf/O
0.726	0.726	tNET	RR	1	u_psram_sync/cs_memsync_4_s0/CLK
1.184	0.458	tC2Q	RF	7	u_psram_sync/cs_memsync_4_s0/Q
2.144	0.960	tNET	FF	1	u_dhcen_clk_x2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				memory_clk
10.000	0.000	tCL	FF	1	memory_clk_ibuf/I
10.000	0.000	tINS	FF	1	memory_clk_ibuf/O
10.960	0.960	tNET	FF	3	u_dhcen_clk_x2/CLKIN
10.930	-0.030	tUnc			u_dhcen_clk_x2
10.676	-0.254	tSu		1	u_dhcen_clk_x2

Path Statistics:

Clock Skew:	0.234
Setup Relationship:	10.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.960, 67.685%; tC2Q: 0.458, 32.315%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:

Slack	8.900
Data Arrival Time	11.426
Data Required Time	20.326
From	u_psram_sync/lock_cnt_1_s3
To	u_psram_sync/lock_cnt_15_s4
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	31	clk_ibuf/O
0.726	0.726	tNET	RR	1	u_psram_sync/lock_cnt_1_s3/CLK
1.184	0.458	tC2Q	RF	6	u_psram_sync/lock_cnt_1_s3/Q
2.144	0.960	tNET	FF	1	u_psram_sync/n47_s2/I1
3.243	1.099	tINS	FF	4	u_psram_sync/n47_s2/F
4.203	0.960	tNET	FF	1	u_psram_sync/n44_s2/I3
4.829	0.626	tINS	FF	8	u_psram_sync/n44_s2/F
5.789	0.960	tNET	FF	1	u_psram_sync/n37_s2/I1
6.888	1.099	tINS	FF	2	u_psram_sync/n37_s2/F
7.848	0.960	tNET	FF	1	u_psram_sync/n36_s5/I3
8.474	0.626	tINS	FF	1	u_psram_sync/n36_s5/F
9.434	0.960	tNET	FF	1	u_psram_sync/n36_s6/I0
10.466	1.032	tINS	FF	1	u_psram_sync/n36_s6/F
11.426	0.960	tNET	FF	1	u_psram_sync/lock_cnt_15_s4/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	31	clk_ibuf/O
20.726	0.726	tNET	RR	1	u_psram_sync/lock_cnt_15_s4/CLK
20.326	-0.400	tSu		1	u_psram_sync/lock_cnt_15_s4

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	6
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.482, 41.887%; route: 5.760, 53.830%; tC2Q: 0.458, 4.283%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:

Slack	9.110
Data Arrival Time	11.216
Data Required Time	20.326
From	u_psram_sync/lock_cnt_1_s3
To	u_psram_sync/lock_cnt_12_s3
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	31	clk_ibuf/O
0.726	0.726	tNET	RR	1	u_psram_sync/lock_cnt_1_s3/CLK
1.184	0.458	tC2Q	RF	6	u_psram_sync/lock_cnt_1_s3/Q
2.144	0.960	tNET	FF	1	u_psram_sync/n47_s2/I1
3.243	1.099	tINS	FF	4	u_psram_sync/n47_s2/F
4.203	0.960	tNET	FF	1	u_psram_sync/n44_s2/I3
4.829	0.626	tINS	FF	8	u_psram_sync/n44_s2/F
5.789	0.960	tNET	FF	1	u_psram_sync/n39_s2/I1
6.888	1.099	tINS	FF	1	u_psram_sync/n39_s2/F
7.848	0.960	tNET	FF	1	u_psram_sync/n39_s6/I2
8.670	0.822	tINS	FF	1	u_psram_sync/n39_s6/F
9.630	0.960	tNET	FF	1	u_psram_sync/n39_s7/I3
10.256	0.626	tINS	FF	1	u_psram_sync/n39_s7/F
11.216	0.960	tNET	FF	1	u_psram_sync/lock_cnt_12_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	31	clk_ibuf/O
20.726	0.726	tNET	RR	1	u_psram_sync/lock_cnt_12_s3/CLK
20.326	-0.400	tSu		1	u_psram_sync/lock_cnt_12_s3

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	6
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.272, 40.723%; route: 5.760, 54.908%; tC2Q: 0.458, 4.369%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:

Slack	9.110
Data Arrival Time	11.216
Data Required Time	20.326
From	u_psram_sync/lock_cnt_1_s3
To	u_psram_sync/lock_cnt_14_s3
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	31	clk_ibuf/O
0.726	0.726	tNET	RR	1	u_psram_sync/lock_cnt_1_s3/CLK
1.184	0.458	tC2Q	RF	6	u_psram_sync/lock_cnt_1_s3/Q
2.144	0.960	tNET	FF	1	u_psram_sync/n47_s2/I1
3.243	1.099	tINS	FF	4	u_psram_sync/n47_s2/F
4.203	0.960	tNET	FF	1	u_psram_sync/n44_s2/I3
4.829	0.626	tINS	FF	8	u_psram_sync/n44_s2/F
5.789	0.960	tNET	FF	1	u_psram_sync/n37_s2/I1
6.888	1.099	tINS	FF	2	u_psram_sync/n37_s2/F
7.848	0.960	tNET	FF	1	u_psram_sync/n37_s6/I2
8.670	0.822	tINS	FF	1	u_psram_sync/n37_s6/F
9.630	0.960	tNET	FF	1	u_psram_sync/n37_s7/I3
10.256	0.626	tINS	FF	1	u_psram_sync/n37_s7/F
11.216	0.960	tNET	FF	1	u_psram_sync/lock_cnt_14_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	31	clk_ibuf/O
20.726	0.726	tNET	RR	1	u_psram_sync/lock_cnt_14_s3/CLK
20.326	-0.400	tSu		1	u_psram_sync/lock_cnt_14_s3

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	6
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.272, 40.723%; route: 5.760, 54.908%; tC2Q: 0.458, 4.369%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:

Slack	9.387
Data Arrival Time	10.939
Data Required Time	20.326
From	u_psram_sync/lock_cnt_1_s3
To	u_psram_sync/lock_cnt_9_s3
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	31	clk_ibuf/O
0.726	0.726	tNET	RR	1	u_psram_sync/lock_cnt_1_s3/CLK
1.184	0.458	tC2Q	RF	6	u_psram_sync/lock_cnt_1_s3/Q
2.144	0.960	tNET	FF	1	u_psram_sync/n47_s2/I1
3.243	1.099	tINS	FF	4	u_psram_sync/n47_s2/F
4.203	0.960	tNET	FF	1	u_psram_sync/n44_s2/I3
4.829	0.626	tINS	FF	8	u_psram_sync/n44_s2/F
5.789	0.960	tNET	FF	1	u_psram_sync/n42_s2/I2
6.611	0.822	tINS	FF	1	u_psram_sync/n42_s2/F
7.571	0.960	tNET	FF	1	u_psram_sync/n42_s6/I2
8.393	0.822	tINS	FF	1	u_psram_sync/n42_s6/F
9.353	0.960	tNET	FF	1	u_psram_sync/n42_s7/I3
9.979	0.626	tINS	FF	1	u_psram_sync/n42_s7/F
10.939	0.960	tNET	FF	1	u_psram_sync/lock_cnt_9_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	31	clk_ibuf/O
20.726	0.726	tNET	RR	1	u_psram_sync/lock_cnt_9_s3/CLK
20.326	-0.400	tSu		1	u_psram_sync/lock_cnt_9_s3

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	6
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 3.995, 39.116%; route: 5.760, 56.396%; tC2Q: 0.458, 4.488%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%