Project Settings Project Name psram_board_test Device Name rev_1: GOWIN-GW1NR : GW1NR_9C Implementation Name rev_1 Top Module [auto] Pipelining 1 Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 Disable Sequential Optimizations 0 Clock Conversion 1 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 10 100 0 - 00m:04s - 2021/3/10 9:34:31 (premap) Complete 6 0 0 0m:02s 0m:02s 244MB 2021/3/10 9:34:36 (fpga_mapper) Complete 13 11 0 0m:06s 0m:06s 246MB 2021/3/10 9:34:43 Multi-srs Generator Complete 00m:01s 2021/3/10 9:34:33 Area Summary I/O ports (io_port) 380 Non I/O Register bits (non_io_reg) 1011 (15%) I/O Register bits (total_io_reg) 0 Ultra Rams 0 Block Rams (v_ram) 0 (26) Block Multipliers (dsp_used) 0 (10) LUTs (total_luts) 1732 (20%) Timing Summary Clock Name Req Freq Est Freq Slack PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d 134.8 MHz 114.6 MHz -1.309 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock 124.8 MHz 106.1 MHz -1.413 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2_inferred_clock 100.0 MHz NA NA PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2p_inferred_clock 100.0 MHz NA NA _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[0] 0.1 MHz NA NA _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[1] 0.1 MHz NA NA _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[0] 0.1 MHz NA NA _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[1] 0.1 MHz NA NA System 848.2 MHz 721.0 MHz -0.208 Optimizations Summary Combined Clock Conversion 4 / 4