#Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020 #install: D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\SynplifyPro #OS: Windows 8 6.2 #Hostname: JN-IP-SHANGYAN # Wed Mar 10 09:34:27 2021 #Implementation: rev_1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode @I::"D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\datasheet\PROJECT\3_10\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\GW1NR9-MG100\project\src\psram_syn_top.v" (library work) @I::"D:\datasheet\PROJECT\3_10\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\GW1NR9-MG100\project\src\psram_test.v" (library work) @I::"D:\datasheet\PROJECT\3_10\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\GW1NR9-MG100\project\src\gowin_rpll\gowin_rpll.v" (library work) @I::"D:\datasheet\PROJECT\3_10\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\GW1NR9-MG100\project\src\psram_memory_interface_hs_2ch_v2\psram_memory_interface_hs_2ch_v2.v" (library work) @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3381) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3382) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3381) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3396) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3382) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3397) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3381) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3396) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3411) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3382) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3397) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3412) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3381) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3396) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3411) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3426) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3382) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3397) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3412) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3427) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3381) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3396) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3411) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3426) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3441) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3382) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3397) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3412) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3427) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3442) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3381) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3396) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3411) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3426) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3441) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3456) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3382) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3397) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3412) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3427) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3442) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3457) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3381) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3396) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3411) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3426) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3441) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3456) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3471) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3382) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3397) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3412) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3427) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3442) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3457) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(3472) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5430) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5431) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5430) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5445) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5431) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5446) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5430) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5445) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5460) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5431) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5446) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5461) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5430) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5445) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5460) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5475) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5431) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5446) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5461) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5476) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5430) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5445) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5460) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5475) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5490) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5431) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5446) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5461) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5476) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5491) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5430) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5445) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5460) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5475) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5490) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5505) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5431) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5446) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5461) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5476) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5491) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5506) | Duplicate defparam TXCLK_POL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5430) | Duplicate defparam HWL found ! Previously declared here. @W:CG1347 : psram_memory_interface_hs_2ch_v2.v(5445) | Duplicate defparam HWL found ! Previously declared here. Only the first 100 messages of id 'CG1347' are reported. To see all messages use 'report_messages -log D:\datasheet\PROJECT\3_10\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\GW1NR9-MG100\project\impl\synthesize\rev_1\synlog\psram_board_test_compiler.srr -id CG1347' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG1347} -count unlimited' in the Tcl shell. @N:CG1306 : psram_syn_top.v(107) | Loading library file D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\IDE\data\hardware_core\gw1n\prim_syn.v into library work @I::"D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\IDE\data\hardware_core\gw1n\prim_syn.v" (library work) Verilog syntax check successful! Selecting top level module PSRAM_Memory_Interface_HS_2CH_V2_Top @N:CG364 : gw1n.v(84) | Synthesizing module LUT2 in library work. Running optimization stage 1 on LUT2 ....... @N:CG364 : gw1n.v(2357) | Synthesizing module DHCEN in library work. Running optimization stage 1 on DHCEN ....... @N:CG364 : gw1n.v(2288) | Synthesizing module CLKDIV in library work. Running optimization stage 1 on CLKDIV ....... @N:CG364 : gw1n.v(302) | Synthesizing module INV in library work. Running optimization stage 1 on INV ....... Running optimization stage 1 on LUT4 ....... Running optimization stage 1 on LUT3 ....... Running optimization stage 1 on DFFC ....... Running optimization stage 1 on DFFCE ....... Running optimization stage 1 on DFFP ....... Running optimization stage 1 on VCC ....... Running optimization stage 1 on GND ....... Running optimization stage 1 on \~psram_sync.PSRAM_Memory_Interface_HS_2CH_V2_Top ....... Running optimization stage 1 on IOBUF ....... Running optimization stage 1 on OBUF ....... Running optimization stage 1 on IODELAY ....... Running optimization stage 1 on RAM16SDP4 ....... Running optimization stage 1 on OSER4 ....... Running optimization stage 1 on IDES4 ....... Running optimization stage 1 on \~psram_lane.PSRAM_Memory_Interface_HS_2CH_V2_Top ....... Running optimization stage 1 on \~psram_lane.PSRAM_Memory_Interface_HS_2CH_V2_Top_0 ....... Running optimization stage 1 on \~psram_wd.PSRAM_Memory_Interface_HS_2CH_V2_Top ....... Running optimization stage 1 on DFFPE ....... Running optimization stage 1 on ALU ....... Running optimization stage 1 on \~psram_init.PSRAM_Memory_Interface_HS_2CH_V2_Top ....... Running optimization stage 1 on \~psram_memory_interface.PSRAM_Memory_Interface_HS_2CH_V2_Top ....... Running optimization stage 1 on \~psram_lane.PSRAM_Memory_Interface_HS_2CH_V2_Top_1 ....... Running optimization stage 1 on \~psram_lane.PSRAM_Memory_Interface_HS_2CH_V2_Top_2 ....... Running optimization stage 1 on \~psram_wd.PSRAM_Memory_Interface_HS_2CH_V2_Top_0 ....... Running optimization stage 1 on \~psram_init.PSRAM_Memory_Interface_HS_2CH_V2_Top_0 ....... Running optimization stage 1 on \~psram_memory_interface.PSRAM_Memory_Interface_HS_2CH_V2_Top_0 ....... @N:CG364 : gw1n.v(2169) | Synthesizing module GSR in library work. Running optimization stage 1 on GSR ....... @N:CG364 : psram_memory_interface_hs_2ch_v2.v(26024) | Synthesizing module PSRAM_Memory_Interface_HS_2CH_V2_Top in library work. Running optimization stage 1 on PSRAM_Memory_Interface_HS_2CH_V2_Top ....... Running optimization stage 2 on PSRAM_Memory_Interface_HS_2CH_V2_Top ....... Running optimization stage 2 on GSR ....... Running optimization stage 2 on \~psram_memory_interface.PSRAM_Memory_Interface_HS_2CH_V2_Top_0 ....... Running optimization stage 2 on \~psram_init.PSRAM_Memory_Interface_HS_2CH_V2_Top_0 ....... Running optimization stage 2 on \~psram_wd.PSRAM_Memory_Interface_HS_2CH_V2_Top_0 ....... Running optimization stage 2 on \~psram_lane.PSRAM_Memory_Interface_HS_2CH_V2_Top_2 ....... Running optimization stage 2 on \~psram_lane.PSRAM_Memory_Interface_HS_2CH_V2_Top_1 ....... Running optimization stage 2 on \~psram_memory_interface.PSRAM_Memory_Interface_HS_2CH_V2_Top ....... Running optimization stage 2 on \~psram_init.PSRAM_Memory_Interface_HS_2CH_V2_Top ....... Running optimization stage 2 on ALU ....... Running optimization stage 2 on DFFPE ....... Running optimization stage 2 on \~psram_wd.PSRAM_Memory_Interface_HS_2CH_V2_Top ....... Running optimization stage 2 on \~psram_lane.PSRAM_Memory_Interface_HS_2CH_V2_Top_0 ....... Running optimization stage 2 on \~psram_lane.PSRAM_Memory_Interface_HS_2CH_V2_Top ....... Running optimization stage 2 on IDES4 ....... Running optimization stage 2 on OSER4 ....... Running optimization stage 2 on RAM16SDP4 ....... Running optimization stage 2 on IODELAY ....... Running optimization stage 2 on OBUF ....... Running optimization stage 2 on IOBUF ....... Running optimization stage 2 on \~psram_sync.PSRAM_Memory_Interface_HS_2CH_V2_Top ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on DFFP ....... Running optimization stage 2 on DFFCE ....... Running optimization stage 2 on DFFC ....... Running optimization stage 2 on LUT3 ....... Running optimization stage 2 on LUT4 ....... Running optimization stage 2 on INV ....... Running optimization stage 2 on CLKDIV ....... Running optimization stage 2 on DHCEN ....... Running optimization stage 2 on LUT2 ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 124MB peak: 124MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime Process completed successfully. # Wed Mar 10 09:34:30 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Mar 10 09:34:31 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: psram_board_test_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 33MB peak: 33MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime Process completed successfully. # Wed Mar 10 09:34:31 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 106MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Mar 10 09:34:33 2021 ###########################################################] Premap Report # Wed Mar 10 09:34:34 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 10:25:53, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) @A:MF827 : | No constraint file specified. Linked File: psram_board_test_scck.rpt See clock summary report "D:\datasheet\PROJECT\3_10\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\GW1NR9-MG100\project\impl\synthesize\rev_1\psram_board_test_scck.rpt" @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 156MB peak: 158MB) Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 240MB peak: 240MB) @N:MF578 : | Incompatible asynchronous control logic preventing generated clock conversion. Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 241MB peak: 241MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 241MB peak: 241MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 241MB peak: 241MB) Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 241MB peak: 242MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ 0 - System 100.0 MHz 10.000 system system_clkgroup 0 0 - PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock 197.3 MHz 5.069 inferred Autoconstr_clkgroup_0 1096 1 . _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[0] 197.3 MHz 5.069 derived (from PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock) Autoconstr_clkgroup_0 8 1 . _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[1] 197.3 MHz 5.069 derived (from PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock) Autoconstr_clkgroup_0 8 1 . _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[0] 197.3 MHz 5.069 derived (from PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock) Autoconstr_clkgroup_0 8 1 . _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[1] 197.3 MHz 5.069 derived (from PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock) Autoconstr_clkgroup_0 8 0 - PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2_inferred_clock 100.0 MHz 10.000 inferred Autoconstr_clkgroup_1 72 0 - PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d 208.3 MHz 4.801 inferred Autoconstr_clkgroup_3 31 0 - PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2p_inferred_clock 100.0 MHz 10.000 inferred Autoconstr_clkgroup_2 8 ========================================================================================================================================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System 0 - - - - PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock 1096 clkdiv.CLKOUT(CLKDIV) u_psram_top1.rd_data_d_63_s0.CLK u_psram_top1.u_psram_wd.\\data_lane_gen\[1\]\.u_psram_lane.\\iserdes_gen\[0\]\.u_ides4.PCLK - _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[0] 8 u_psram_top1.u_psram_init.VALUE_0_s1.Q(DFFCE) u_psram_top1.u_psram_wd.\\dq_iodelay_gen0\[0\]\.\[0\]\.iodelay.VALUE - - _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[1] 8 u_psram_top1.u_psram_init.VALUE_1_s1.Q(DFFCE) u_psram_top1.u_psram_wd.\\dq_iodelay_gen0\[1\]\.\[0\]\.iodelay.VALUE - - _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[0] 8 u_psram_top0.u_psram_init.VALUE_0_s1.Q(DFFCE) u_psram_top0.u_psram_wd.\\dq_iodelay_gen0\[0\]\.\[0\]\.iodelay.VALUE - - _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[1] 8 u_psram_top0.u_psram_init.VALUE_1_s1.Q(DFFCE) u_psram_top0.u_psram_wd.\\dq_iodelay_gen0\[1\]\.\[0\]\.iodelay.VALUE - - PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2_inferred_clock 72 u_dhcen_clk_x2.CLKOUT(DHCEN) u_psram_top1.u_psram_wd.\\data_lane_gen\[1\]\.u_psram_lane.mask_oser4.FCLK - - PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d 31 clk_d(port) u_psram_sync.lock_syn_0_s0.CLK - - PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2p_inferred_clock 8 u_dhcen_clk_x2p.CLKOUT(DHCEN) u_psram_top1.u_psram_wd.\\data_lane_gen\[1\]\.u_psram_lane.\\genclkpos\.u_ck_gen.FCLK - - ======================================================================================================================================================================================================================================================================================================================================================= ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 4 non-gated/non-generated clock tree(s) driving 1175 clock pin(s) of sequential element(s) 4 gated/generated clock tree(s) driving 32 clock pin(s) of sequential element(s) 0 instances converted, 32 sequential instances remain driven by gated/generated clocks =============================== Non-Gated/Non-Generated Clocks =============================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------------- ClockId_0_0 clkdiv.CLKOUT CLKDIV 1064 ENCRYPTED ClockId_0_1 u_dhcen_clk_x2p.CLKOUT DHCEN 8 ENCRYPTED ClockId_0_2 u_dhcen_clk_x2.CLKOUT DHCEN 72 ENCRYPTED ClockId_0_11 clk_d port 31 ENCRYPTED ============================================================================================== ============================================================= Gated/Generated Clocks ============================================================= Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation -------------------------------------------------------------------------------------------------------------------------------------------------- ClockId_0_3 ENCRYPTED DFFCE 8 ENCRYPTED Derived clock on input (not legal for GCC) ClockId_0_5 ENCRYPTED DFFCE 8 ENCRYPTED Derived clock on input (not legal for GCC) ClockId_0_7 ENCRYPTED DFFCE 8 ENCRYPTED Derived clock on input (not legal for GCC) ClockId_0_9 ENCRYPTED DFFCE 8 ENCRYPTED Derived clock on input (not legal for GCC) ================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\datasheet\PROJECT\3_10\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\GW1NR9-MG100\project\impl\synthesize\rev_1\psram_board_test.sap. Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 242MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 242MB) Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 242MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 163MB peak: 244MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Wed Mar 10 09:34:37 2021 ###########################################################] Map & Optimize Report # Wed Mar 10 09:34:37 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 10:25:53, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 125MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 137MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 137MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 137MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 234MB peak: 234MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 243MB peak: 243MB) Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 244MB peak: 244MB) Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 244MB peak: 244MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 244MB peak: 244MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 244MB peak: 244MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 244MB peak: 244MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 244MB peak: 244MB) Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 244MB peak: 244MB) Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 244MB peak: 245MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:02s -3.30ns 1732 / 0 2 0h:00m:02s -3.30ns 1732 / 0 3 0h:00m:02s -3.30ns 1732 / 0 4 0h:00m:02s -3.30ns 1732 / 0 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 245MB peak: 245MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. @W:MT453 : | clock period is too long for clock PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d, changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns. @W:MT453 : | clock period is too long for clock _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[0], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns. @W:MT453 : | clock period is too long for clock _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[1], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns. @W:MT453 : | clock period is too long for clock _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[0], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns. @W:MT453 : | clock period is too long for clock _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[1], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns. Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 245MB peak: 245MB) Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 162MB peak: 245MB) Writing Analyst data base D:\datasheet\PROJECT\3_10\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\GW1NR9-MG100\project\impl\synthesize\rev_1\synwork\psram_board_test_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 244MB peak: 245MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 245MB peak: 246MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 245MB peak: 246MB) Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 241MB peak: 246MB) @W:MT246 : psram_memory_interface_hs_2ch_v2.v(26109) | Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : psram_memory_interface_hs_2ch_v2.v(26104) | Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock with period 8.01ns. Please declare a user-defined clock on net clk_outz. @W:MT420 : | Found inferred clock PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2_inferred_clock with period 10.00ns. Please declare a user-defined clock on net clk_x2. @W:MT420 : | Found inferred clock PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2p_inferred_clock with period 10.00ns. Please declare a user-defined clock on net clk_x2p. @W:MT420 : | Found inferred clock PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d with period 7.42ns. Please declare a user-defined clock on port clk_d. @N:MT615 : | Found clock _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[0] with period 20000.00ns @N:MT615 : | Found clock _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[1] with period 20000.00ns @N:MT615 : | Found clock _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[0] with period 20000.00ns @N:MT615 : | Found clock _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[1] with period 20000.00ns ##### START OF TIMING REPORT #####[ # Timing report written on Wed Mar 10 09:34:43 2021 # Top view: PSRAM_Memory_Interface_HS_2CH_V2_Top Requested Frequency: 0.1 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.413 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d 134.8 MHz 114.6 MHz 7.416 8.725 -1.309 inferred Autoconstr_clkgroup_3 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock 124.8 MHz 106.1 MHz 8.010 9.423 -1.413 inferred Autoconstr_clkgroup_0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Autoconstr_clkgroup_1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2p_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Autoconstr_clkgroup_2 _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[0] 0.1 MHz NA 20000.000 NA NA derived (from PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock) Autoconstr_clkgroup_0 _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[1] 0.1 MHz NA 20000.000 NA NA derived (from PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock) Autoconstr_clkgroup_0 _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[0] 0.1 MHz NA 20000.000 NA NA derived (from PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock) Autoconstr_clkgroup_0 _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[1] 0.1 MHz NA 20000.000 NA NA derived (from PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock) Autoconstr_clkgroup_0 System 848.2 MHz 721.0 MHz 1.179 1.387 -0.208 system system_clkgroup =========================================================================================================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 1.179 -0.208 | No paths - | No paths - | No paths - System PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock | 8.010 0.848 | No paths - | No paths - | No paths - PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock | 8.010 -1.413 | No paths - | No paths - | No paths - PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2_inferred_clock | Diff grp - | No paths - | No paths - | No paths - PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d System | 7.416 3.908 | No paths - | No paths - | No paths - PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock | Diff grp - | No paths - | No paths - | No paths - PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d | 7.416 -1.309 | No paths - | No paths - | No paths - ================================================================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------ u_psram_sync.cs_memsync_5_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC Q cs_memsync_0[5] 0.367 -1.309 u_psram_sync.cs_memsync_3_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC Q cs_memsync[3] 0.367 -1.242 u_psram_sync.cs_memsync_2_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC Q cs_memsync_0[2] 0.367 -1.032 u_psram_sync.cs_memsync_0_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC Q O_psram_reset_n[0] 0.367 -1.026 u_psram_sync.cs_memsync_4_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC Q stop 0.367 -0.836 u_psram_sync.count_2_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC Q count[2] 0.367 -0.747 u_psram_sync.cs_memsync_1_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFP Q cs_memsync_0[1] 0.367 -0.688 u_psram_sync.flag_0_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC Q flag[0] 0.367 -0.680 u_psram_sync.count_1_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC Q count[1] 0.367 -0.478 u_psram_sync.count_0_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC Q count[0] 0.367 -0.201 ========================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------- u_psram_sync.flag_0_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC D n359_10 7.283 -1.309 u_psram_sync.cs_memsync_1_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFP D n326_16 7.283 -1.026 u_psram_sync.flag_1_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC D n348_9 7.283 -1.026 u_psram_sync.cs_memsync_0_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC D n337_16 7.283 -0.816 u_psram_sync.count_1_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC D n388_5 7.283 -0.814 u_psram_sync.cs_memsync_2_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC D n315_16 7.283 -0.688 u_psram_sync.count_2_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC D n387_5 7.283 -0.618 u_psram_sync.cs_memsync_3_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC D n304_16 7.283 -0.424 u_psram_sync.cs_memsync_4_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFC D n293_16 7.283 0.202 u_psram_sync.lock_cnt_9_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d DFFCE D n42_5 7.283 0.556 ================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 7.416 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.283 - Propagation time: 8.592 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.309 Number of logic level(s): 4 Starting point: u_psram_sync.cs_memsync_5_s0 / Q Ending point: u_psram_sync.flag_0_s0 / D The start point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d [rising] (rise=0.000 fall=3.708 period=7.416) on pin CLK The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d [rising] (rise=0.000 fall=3.708 period=7.416) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- u_psram_sync.cs_memsync_5_s0 DFFC Q Out 0.367 0.367 r - cs_memsync_0[5] Net - - 1.021 - 6 u_psram_sync.n359_s10 LUT4 I1 In - 1.388 r - u_psram_sync.n359_s10 LUT4 F Out 1.099 2.487 f - n359_14 Net - - 1.021 - 4 u_psram_sync.n348_s9 LUT2 I1 In - 3.508 f - u_psram_sync.n348_s9 LUT2 F Out 1.099 4.607 f - n348_13 Net - - 1.021 - 2 u_psram_sync.n359_s8 LUT4 I1 In - 5.628 f - u_psram_sync.n359_s8 LUT4 F Out 1.099 6.727 f - n359_12 Net - - 0.766 - 1 u_psram_sync.n359_s6 LUT4 I1 In - 7.493 f - u_psram_sync.n359_s6 LUT4 F Out 1.099 8.592 f - n359_10 Net - - 0.000 - 1 u_psram_sync.flag_0_s0 DFFC D In - 8.592 f - =========================================================================================== Total path delay (propagation time + setup) of 8.725 is 4.896(56.1%) logic and 3.829(43.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 7.416 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.283 - Propagation time: 8.525 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.242 Number of logic level(s): 4 Starting point: u_psram_sync.cs_memsync_3_s0 / Q Ending point: u_psram_sync.flag_0_s0 / D The start point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d [rising] (rise=0.000 fall=3.708 period=7.416) on pin CLK The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d [rising] (rise=0.000 fall=3.708 period=7.416) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- u_psram_sync.cs_memsync_3_s0 DFFC Q Out 0.367 0.367 r - cs_memsync[3] Net - - 1.021 - 10 u_psram_sync.n359_s10 LUT4 I0 In - 1.388 r - u_psram_sync.n359_s10 LUT4 F Out 1.032 2.420 f - n359_14 Net - - 1.021 - 4 u_psram_sync.n348_s9 LUT2 I1 In - 3.441 f - u_psram_sync.n348_s9 LUT2 F Out 1.099 4.540 f - n348_13 Net - - 1.021 - 2 u_psram_sync.n359_s8 LUT4 I1 In - 5.561 f - u_psram_sync.n359_s8 LUT4 F Out 1.099 6.660 f - n359_12 Net - - 0.766 - 1 u_psram_sync.n359_s6 LUT4 I1 In - 7.426 f - u_psram_sync.n359_s6 LUT4 F Out 1.099 8.525 f - n359_10 Net - - 0.000 - 1 u_psram_sync.flag_0_s0 DFFC D In - 8.525 f - =========================================================================================== Total path delay (propagation time + setup) of 8.658 is 4.829(55.8%) logic and 3.829(44.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 7.416 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.283 - Propagation time: 8.315 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.032 Number of logic level(s): 4 Starting point: u_psram_sync.cs_memsync_2_s0 / Q Ending point: u_psram_sync.flag_0_s0 / D The start point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d [rising] (rise=0.000 fall=3.708 period=7.416) on pin CLK The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d [rising] (rise=0.000 fall=3.708 period=7.416) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- u_psram_sync.cs_memsync_2_s0 DFFC Q Out 0.367 0.367 r - cs_memsync_0[2] Net - - 1.021 - 6 u_psram_sync.n359_s10 LUT4 I2 In - 1.388 r - u_psram_sync.n359_s10 LUT4 F Out 0.822 2.210 f - n359_14 Net - - 1.021 - 4 u_psram_sync.n348_s9 LUT2 I1 In - 3.231 f - u_psram_sync.n348_s9 LUT2 F Out 1.099 4.330 f - n348_13 Net - - 1.021 - 2 u_psram_sync.n359_s8 LUT4 I1 In - 5.351 f - u_psram_sync.n359_s8 LUT4 F Out 1.099 6.450 f - n359_12 Net - - 0.766 - 1 u_psram_sync.n359_s6 LUT4 I1 In - 7.216 f - u_psram_sync.n359_s6 LUT4 F Out 1.099 8.315 f - n359_10 Net - - 0.000 - 1 u_psram_sync.flag_0_s0 DFFC D In - 8.315 f - =========================================================================================== Total path delay (propagation time + setup) of 8.448 is 4.619(54.7%) logic and 3.829(45.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 7.416 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.283 - Propagation time: 8.309 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.026 Number of logic level(s): 4 Starting point: u_psram_sync.cs_memsync_0_s0 / Q Ending point: u_psram_sync.cs_memsync_1_s0 / D The start point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d [rising] (rise=0.000 fall=3.708 period=7.416) on pin CLK The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d [rising] (rise=0.000 fall=3.708 period=7.416) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- u_psram_sync.cs_memsync_0_s0 DFFC Q Out 0.367 0.367 r - O_psram_reset_n[0] Net - - 1.082 - 11 u_psram_sync.n359_s11 LUT4 I1 In - 1.449 r - u_psram_sync.n359_s11 LUT4 F Out 1.099 2.548 f - n359_15 Net - - 1.021 - 4 u_psram_sync.n304_s13 LUT3 I1 In - 3.569 f - u_psram_sync.n304_s13 LUT3 F Out 1.099 4.668 f - n304_17 Net - - 1.021 - 4 u_psram_sync.n326_s13 LUT4 I2 In - 5.689 f - u_psram_sync.n326_s13 LUT4 F Out 0.822 6.511 f - n326_17 Net - - 0.766 - 1 u_psram_sync.n326_s12 LUT3 I0 In - 7.277 f - u_psram_sync.n326_s12 LUT3 F Out 1.032 8.309 f - n326_16 Net - - 0.000 - 1 u_psram_sync.cs_memsync_1_s0 DFFP D In - 8.309 f - =========================================================================================== Total path delay (propagation time + setup) of 8.442 is 4.552(53.9%) logic and 3.890(46.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 7.416 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.283 - Propagation time: 8.309 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.026 Number of logic level(s): 4 Starting point: u_psram_sync.cs_memsync_0_s0 / Q Ending point: u_psram_sync.flag_1_s0 / D The start point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d [rising] (rise=0.000 fall=3.708 period=7.416) on pin CLK The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d [rising] (rise=0.000 fall=3.708 period=7.416) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- u_psram_sync.cs_memsync_0_s0 DFFC Q Out 0.367 0.367 r - O_psram_reset_n[0] Net - - 1.082 - 11 u_psram_sync.n359_s11 LUT4 I1 In - 1.449 r - u_psram_sync.n359_s11 LUT4 F Out 1.099 2.548 f - n359_15 Net - - 1.021 - 4 u_psram_sync.n359_s9 LUT4 I0 In - 3.569 f - u_psram_sync.n359_s9 LUT4 F Out 1.032 4.601 f - n359_13 Net - - 1.021 - 3 u_psram_sync.n348_s7 LUT4 I1 In - 5.622 f - u_psram_sync.n348_s7 LUT4 F Out 1.099 6.721 f - n348_11 Net - - 0.766 - 1 u_psram_sync.n348_s5 LUT3 I2 In - 7.487 f - u_psram_sync.n348_s5 LUT3 F Out 0.822 8.309 f - n348_9 Net - - 0.000 - 1 u_psram_sync.flag_1_s0 DFFC D In - 8.309 f - =========================================================================================== Total path delay (propagation time + setup) of 8.442 is 4.552(53.9%) logic and 3.890(46.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- u_psram_top1.rd_data_d_19_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFC Q rd_data_d[19] 0.367 -1.413 u_psram_top0.rd_data_d_21_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFC Q rd_data_d[21] 0.367 -1.413 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.wr_ptr_2_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE Q wr_ptr[2] 0.367 -1.346 u_psram_top0.u_psram_init.\\read_calibration\[0\]\.wr_ptr_2_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE Q wr_ptr[2] 0.367 -1.346 u_psram_top0.rd_data_d_27_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFC Q rd_data_d[27] 0.367 -1.346 u_psram_top1.rd_data_d_27_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFC Q rd_data_d[27] 0.367 -1.346 u_psram_top1.u_psram_init.\\read_calibration\[1\]\.wr_ptr_2_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE Q wr_ptr_0[2] 0.367 -1.279 u_psram_top0.u_psram_init.\\read_calibration\[1\]\.wr_ptr_2_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE Q wr_ptr_0[2] 0.367 -1.279 u_psram_top1.rd_data_d_23_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFC Q rd_data_d[23] 0.367 -1.225 u_psram_top1.rd_data_d_22_s0 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFC Q rd_data_d[22] 0.367 -1.158 ========================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_0_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE CE check_cnt_5_8 7.877 -1.413 u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_0_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE CE check_cnt_5_8 7.877 -1.413 u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_1_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE CE check_cnt_5_8 7.877 -1.413 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_1_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE CE check_cnt_5_8 7.877 -1.413 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_2_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE CE check_cnt_5_8 7.877 -1.413 u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_2_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE CE check_cnt_5_8 7.877 -1.413 u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_3_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE CE check_cnt_5_8 7.877 -1.413 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_3_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE CE check_cnt_5_8 7.877 -1.413 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_4_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE CE check_cnt_5_8 7.877 -1.413 u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_4_s1 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock DFFCE CE check_cnt_5_8 7.877 -1.413 ============================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.010 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.877 - Propagation time: 9.290 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.413 Number of logic level(s): 4 Starting point: u_psram_top1.rd_data_d_19_s0 / Q Ending point: u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_0_s1 / CE The start point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------- u_psram_top1.rd_data_d_19_s0 DFFC Q Out 0.367 0.367 r - rd_data_d[19] Net - - 1.021 - 2 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s17 LUT4 I1 In - 1.388 r - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s17 LUT4 F Out 1.099 2.487 f - check_cnt_5_22 Net - - 1.021 - 2 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s11 LUT3 I0 In - 3.508 f - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s11 LUT3 F Out 1.032 4.540 f - check_cnt_5_16 Net - - 0.766 - 1 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s5 LUT3 I1 In - 5.306 f - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s5 LUT3 F Out 1.099 6.405 f - check_cnt_5_10 Net - - 0.766 - 1 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s3 LUT4 I1 In - 7.170 f - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s3 LUT4 F Out 1.099 8.269 f - check_cnt_5_8 Net - - 1.021 - 6 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_0_s1 DFFCE CE In - 9.290 f - ================================================================================================================================== Total path delay (propagation time + setup) of 9.423 is 4.829(51.2%) logic and 4.594(48.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 8.010 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.877 - Propagation time: 9.290 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.413 Number of logic level(s): 4 Starting point: u_psram_top0.rd_data_d_21_s0 / Q Ending point: u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_0_s1 / CE The start point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------- u_psram_top0.rd_data_d_21_s0 DFFC Q Out 0.367 0.367 r - rd_data_d[21] Net - - 1.021 - 2 u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s15 LUT3 I1 In - 1.388 r - u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s15 LUT3 F Out 1.099 2.487 f - check_cnt_5_20_0 Net - - 1.021 - 2 u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s8 LUT4 I1 In - 3.508 f - u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s8 LUT4 F Out 1.099 4.607 f - check_cnt_5_13 Net - - 0.766 - 1 u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s4 LUT4 I1 In - 5.373 f - u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s4 LUT4 F Out 1.099 6.472 f - check_cnt_5_9 Net - - 0.766 - 1 u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s3 LUT4 I0 In - 7.237 f - u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s3 LUT4 F Out 1.032 8.269 f - check_cnt_5_8 Net - - 1.021 - 6 u_psram_top0.u_psram_init.\\read_calibration\[0\]\.check_cnt_0_s1 DFFCE CE In - 9.290 f - ================================================================================================================================== Total path delay (propagation time + setup) of 9.423 is 4.829(51.2%) logic and 4.594(48.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 8.010 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.877 - Propagation time: 9.290 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.413 Number of logic level(s): 4 Starting point: u_psram_top1.rd_data_d_19_s0 / Q Ending point: u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s1 / CE The start point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------- u_psram_top1.rd_data_d_19_s0 DFFC Q Out 0.367 0.367 r - rd_data_d[19] Net - - 1.021 - 2 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s17 LUT4 I1 In - 1.388 r - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s17 LUT4 F Out 1.099 2.487 f - check_cnt_5_22 Net - - 1.021 - 2 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s11 LUT3 I0 In - 3.508 f - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s11 LUT3 F Out 1.032 4.540 f - check_cnt_5_16 Net - - 0.766 - 1 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s5 LUT3 I1 In - 5.306 f - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s5 LUT3 F Out 1.099 6.405 f - check_cnt_5_10 Net - - 0.766 - 1 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s3 LUT4 I1 In - 7.170 f - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s3 LUT4 F Out 1.099 8.269 f - check_cnt_5_8 Net - - 1.021 - 6 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s1 DFFCE CE In - 9.290 f - ================================================================================================================================== Total path delay (propagation time + setup) of 9.423 is 4.829(51.2%) logic and 4.594(48.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 8.010 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.877 - Propagation time: 9.290 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.413 Number of logic level(s): 4 Starting point: u_psram_top1.rd_data_d_19_s0 / Q Ending point: u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_4_s1 / CE The start point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------- u_psram_top1.rd_data_d_19_s0 DFFC Q Out 0.367 0.367 r - rd_data_d[19] Net - - 1.021 - 2 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s17 LUT4 I1 In - 1.388 r - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s17 LUT4 F Out 1.099 2.487 f - check_cnt_5_22 Net - - 1.021 - 2 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s11 LUT3 I0 In - 3.508 f - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s11 LUT3 F Out 1.032 4.540 f - check_cnt_5_16 Net - - 0.766 - 1 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s5 LUT3 I1 In - 5.306 f - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s5 LUT3 F Out 1.099 6.405 f - check_cnt_5_10 Net - - 0.766 - 1 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s3 LUT4 I1 In - 7.170 f - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s3 LUT4 F Out 1.099 8.269 f - check_cnt_5_8 Net - - 1.021 - 6 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_4_s1 DFFCE CE In - 9.290 f - ================================================================================================================================== Total path delay (propagation time + setup) of 9.423 is 4.829(51.2%) logic and 4.594(48.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 8.010 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.877 - Propagation time: 9.290 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.413 Number of logic level(s): 4 Starting point: u_psram_top1.rd_data_d_19_s0 / Q Ending point: u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_3_s1 / CE The start point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------- u_psram_top1.rd_data_d_19_s0 DFFC Q Out 0.367 0.367 r - rd_data_d[19] Net - - 1.021 - 2 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s17 LUT4 I1 In - 1.388 r - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s17 LUT4 F Out 1.099 2.487 f - check_cnt_5_22 Net - - 1.021 - 2 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s11 LUT3 I0 In - 3.508 f - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s11 LUT3 F Out 1.032 4.540 f - check_cnt_5_16 Net - - 0.766 - 1 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s5 LUT3 I1 In - 5.306 f - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s5 LUT3 F Out 1.099 6.405 f - check_cnt_5_10 Net - - 0.766 - 1 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s3 LUT4 I1 In - 7.170 f - u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_5_s3 LUT4 F Out 1.099 8.269 f - check_cnt_5_8 Net - - 1.021 - 6 u_psram_top1.u_psram_init.\\read_calibration\[0\]\.check_cnt_3_s1 DFFCE CE In - 9.290 f - ================================================================================================================================== Total path delay (propagation time + setup) of 9.423 is 4.829(51.2%) logic and 4.594(48.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------- u_dhcen_clk_x2 System DHCEN CLKOUT clk_x2_i 0.000 -0.208 clkdiv System CLKDIV CLKOUT clk_out_i 0.000 0.848 ======================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------- clkdiv System CLKDIV HCLKIN clk_x2_i 1.179 -0.208 u_psram_top0.rd_data_d_0_s0 System DFFC D n297_7 7.877 0.848 u_psram_top1.rd_data_d_0_s0 System DFFC D n297_7 7.877 0.848 u_psram_top0.rd_data_d_1_s0 System DFFC D n296_7 7.877 0.848 u_psram_top1.rd_data_d_1_s0 System DFFC D n296_7 7.877 0.848 u_psram_top0.rd_data_d_2_s0 System DFFC D n295_7 7.877 0.848 u_psram_top1.rd_data_d_2_s0 System DFFC D n295_7 7.877 0.848 u_psram_top1.rd_data_d_3_s0 System DFFC D n294_7 7.877 0.848 u_psram_top0.rd_data_d_3_s0 System DFFC D n294_7 7.877 0.848 u_psram_top0.rd_data_d_4_s0 System DFFC D n293_7 7.877 0.848 ==================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1.179 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1.179 - Propagation time: 1.387 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.208 Number of logic level(s): 0 Starting point: u_dhcen_clk_x2 / CLKOUT Ending point: clkdiv / HCLKIN The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------- u_dhcen_clk_x2 DHCEN CLKOUT Out 0.000 0.000 r - clk_x2_i Net - - 1.387 - 73 clkdiv CLKDIV HCLKIN In - 1.387 r - ================================================================================= Total path delay (propagation time + setup) of 1.387 is 0.000(0.0%) logic and 1.387(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 8.010 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.877 - Propagation time: 7.029 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 0.848 Number of logic level(s): 2 Starting point: clkdiv / CLKOUT Ending point: u_psram_top0.rd_data_d_8_s0 / D The start point is clocked by System [rising] The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------- clkdiv CLKDIV CLKOUT Out 0.000 0.000 r - clk_out_i Net - - 4.497 - 1097 u_psram_top0.u_psram_wd.\\data_lane_gen\[1\]\.u_psram_lane.\\iserdes_gen\[0\]\.u_ides4 IDES4 PCLK In - 4.497 r - u_psram_top0.u_psram_wd.\\data_lane_gen\[1\]\.u_psram_lane.\\iserdes_gen\[0\]\.u_ides4 IDES4 Q3 Out 0.479 4.976 r - rdbk_data_d0_0[32] Net - - 1.021 - 1 u_psram_top0.n289_s2 LUT3 I0 In - 5.997 r - u_psram_top0.n289_s2 LUT3 F Out 1.032 7.029 f - n289_7 Net - - 0.000 - 1 u_psram_top0.rd_data_d_8_s0 DFFC D In - 7.029 f - ========================================================================================================================================================= Total path delay (propagation time + setup) of 7.162 is 1.644(23.0%) logic and 5.518(77.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 8.010 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.877 - Propagation time: 7.029 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 0.848 Number of logic level(s): 2 Starting point: clkdiv / CLKOUT Ending point: u_psram_top0.rd_data_d_9_s0 / D The start point is clocked by System [rising] The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------- clkdiv CLKDIV CLKOUT Out 0.000 0.000 r - clk_out_i Net - - 4.497 - 1097 u_psram_top0.u_psram_wd.\\data_lane_gen\[1\]\.u_psram_lane.\\iserdes_gen\[1\]\.u_ides4 IDES4 PCLK In - 4.497 r - u_psram_top0.u_psram_wd.\\data_lane_gen\[1\]\.u_psram_lane.\\iserdes_gen\[1\]\.u_ides4 IDES4 Q3 Out 0.479 4.976 r - rdbk_data_d0_0[33] Net - - 1.021 - 1 u_psram_top0.n288_s2 LUT3 I0 In - 5.997 r - u_psram_top0.n288_s2 LUT3 F Out 1.032 7.029 f - n288_7 Net - - 0.000 - 1 u_psram_top0.rd_data_d_9_s0 DFFC D In - 7.029 f - ========================================================================================================================================================= Total path delay (propagation time + setup) of 7.162 is 1.644(23.0%) logic and 5.518(77.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 8.010 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.877 - Propagation time: 7.029 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 0.848 Number of logic level(s): 2 Starting point: clkdiv / CLKOUT Ending point: u_psram_top0.rd_data_d_10_s0 / D The start point is clocked by System [rising] The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------- clkdiv CLKDIV CLKOUT Out 0.000 0.000 r - clk_out_i Net - - 4.497 - 1097 u_psram_top0.u_psram_wd.\\data_lane_gen\[1\]\.u_psram_lane.\\iserdes_gen\[2\]\.u_ides4 IDES4 PCLK In - 4.497 r - u_psram_top0.u_psram_wd.\\data_lane_gen\[1\]\.u_psram_lane.\\iserdes_gen\[2\]\.u_ides4 IDES4 Q3 Out 0.479 4.976 r - rdbk_data_d0_0[34] Net - - 1.021 - 1 u_psram_top0.n287_s2 LUT3 I0 In - 5.997 r - u_psram_top0.n287_s2 LUT3 F Out 1.032 7.029 f - n287_7 Net - - 0.000 - 1 u_psram_top0.rd_data_d_10_s0 DFFC D In - 7.029 f - ========================================================================================================================================================= Total path delay (propagation time + setup) of 7.162 is 1.644(23.0%) logic and 5.518(77.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 8.010 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.877 - Propagation time: 7.029 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 0.848 Number of logic level(s): 2 Starting point: clkdiv / CLKOUT Ending point: u_psram_top0.rd_data_d_11_s0 / D The start point is clocked by System [rising] The end point is clocked by PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock [rising] (rise=0.000 fall=4.005 period=8.010) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------- clkdiv CLKDIV CLKOUT Out 0.000 0.000 r - clk_out_i Net - - 4.497 - 1097 u_psram_top0.u_psram_wd.\\data_lane_gen\[1\]\.u_psram_lane.\\iserdes_gen\[3\]\.u_ides4 IDES4 PCLK In - 4.497 r - u_psram_top0.u_psram_wd.\\data_lane_gen\[1\]\.u_psram_lane.\\iserdes_gen\[3\]\.u_ides4 IDES4 Q3 Out 0.479 4.976 r - rdbk_data_d0_0[35] Net - - 1.021 - 1 u_psram_top0.n286_s2 LUT3 I0 In - 5.997 r - u_psram_top0.n286_s2 LUT3 F Out 1.032 7.029 f - n286_7 Net - - 0.000 - 1 u_psram_top0.rd_data_d_11_s0 DFFC D In - 7.029 f - ========================================================================================================================================================= Total path delay (propagation time + setup) of 7.162 is 1.644(23.0%) logic and 5.518(77.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 243MB peak: 246MB) Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 243MB peak: 246MB) --------------------------------------- Resource Usage Report for PSRAM_Memory_Interface_HS_2CH_V2_Top Mapping to part: gw1nr_9cmbga100p-6 Cell usage: ALU 52 uses CLKDIV 1 use DFFC 600 uses DFFCE 395 uses DFFP 4 uses DFFPE 12 uses DHCEN 2 uses GSR 1 use IDES4 32 uses INV 9 uses IODELAY 32 uses OSER4 48 uses RAM16SDP4 36 uses LUT2 563 uses LUT3 607 uses LUT4 562 uses I/O ports: 380 I/O primitives: 380 IBUF 195 uses IOBUF 36 uses OBUF 149 uses I/O Register bits: 0 Register bits not including I/Os: 1011 of 6480 (15%) Total load per clock: PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock: 1096 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2_inferred_clock: 72 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2p_inferred_clock: 8 PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d: 31 _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[0]: 8 _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[1]: 8 _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[0]: 8 _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[1]: 8 @S |Mapping Summary: Total LUTs: 1732 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 86MB peak: 246MB) Process took 0h:00m:06s realtime, 0h:00m:06s cputime # Wed Mar 10 09:34:43 2021 ###########################################################]