@W: MT453 |clock period is too long for clock PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d, changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns. 
@W: MT453 |clock period is too long for clock _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[0], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns. 
@W: MT453 |clock period is too long for clock _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_|VALUE_Z_1_derived_clock[1], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns. 
@W: MT453 |clock period is too long for clock _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[0], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns. 
@W: MT453 |clock period is too long for clock _~psram_init_PSRAM_Memory_Interface_HS_2CH_V2_Top_0_|VALUE_Z_1_derived_clock[1], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns. 
@W: MT246 :"d:\datasheet\project\3_10\gowin_psram_memory_interface_hs_2ch_refdesign\gw1nr9-mg100\project\src\psram_memory_interface_hs_2ch_v2\psram_memory_interface_hs_2ch_v2.v":26109:9:26109:14|Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"d:\datasheet\project\3_10\gowin_psram_memory_interface_hs_2ch_refdesign\gw1nr9-mg100\project\src\psram_memory_interface_hs_2ch_v2\psram_memory_interface_hs_2ch_v2.v":26104:8:26104:22|Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_out_inferred_clock with period 8.01ns. Please declare a user-defined clock on net clk_outz.
@W: MT420 |Found inferred clock PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2_inferred_clock with period 10.00ns. Please declare a user-defined clock on net clk_x2.
@W: MT420 |Found inferred clock PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_x2p_inferred_clock with period 10.00ns. Please declare a user-defined clock on net clk_x2p.
@W: MT420 |Found inferred clock PSRAM_Memory_Interface_HS_2CH_V2_Top|clk_d with period 7.42ns. Please declare a user-defined clock on port clk_d.
