Timing Messages

Report Title Timing Analysis Report
Design File E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\project\impl\gwsynthesis\psram_board_test.vg
Physical Constraints File E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\project\src\psram.cst
Timing Constraint File E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\project\src\psram.sdc
Tool Version V1.9.12.02 (64-bit)
Part Number GW1NR-LV9LQ144PC6/I5
Device GW1NR-9
Device Version C
Created Time Mon Mar 9 10:46:14 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C6/I5
Hold Delay Model Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed 5015
Numbers of Endpoints Analyzed 5098
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk Base 20.000 50.000 0.000 10.000 clk
2 clk_x1 Base 12.048 83.001 0.000 6.024 clk_x1
3 clk_x2 Base 6.024 166.003 0.000 3.012 memory_clk
4 tck_pad_i Base 50.000 20.000 0.000 25.000 tck_ibuf/I
5 your_instance_name/rpll_inst/CLKOUTP.default_gen_clk Generated 6.038 165.625 0.000 3.019 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTP
6 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk Generated 12.075 82.812 0.000 6.038 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTD
7 your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk Generated 18.113 55.208 0.000 9.057 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 105.270(MHz) 6 TOP
2 clk_x1 83.001(MHz) 83.130(MHz) 6 TOP
3 tck_pad_i 20.000(MHz) 72.971(MHz) 4 TOP

No timing paths to get frequency of clk_x2!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0
clk_x1 Setup 0.000 0
clk_x1 Hold 0.000 0
clk_x2 Setup 0.000 0
clk_x2 Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.019 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/addr_10_s0/D clk_x1:[R] clk_x1:[R] 12.048 0.000 11.629
2 0.019 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/addr_19_s0/D clk_x1:[R] clk_x1:[R] 12.048 0.000 11.629
3 0.019 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/addr_20_s0/D clk_x1:[R] clk_x1:[R] 12.048 0.000 11.629
4 0.093 u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4/Q u_test1/addr_13_s0/D clk_x1:[R] clk_x1:[R] 12.048 0.000 11.555
5 0.166 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/addr_11_s0/D clk_x1:[R] clk_x1:[R] 12.048 0.000 11.482
6 0.168 u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4/Q u_test1/addr_14_s0/D clk_x1:[R] clk_x1:[R] 12.048 0.000 11.480
7 0.185 u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4/Q u_test1/addr_8_s0/D clk_x1:[R] clk_x1:[R] 12.048 0.000 11.463
8 0.215 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/addr_15_s0/D clk_x1:[R] clk_x1:[R] 12.048 0.000 11.433
9 0.219 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/addr_7_s0/D clk_x1:[R] clk_x1:[R] 12.048 0.000 11.429
10 0.241 u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_1_s1/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1/D clk_x1:[R] clk_x1:[R] 12.048 0.000 11.407
11 0.269 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/wr_data_add_10_s1/CE clk_x1:[R] clk_x1:[R] 12.048 0.000 11.736
12 0.269 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/wr_data_add_20_s1/CE clk_x1:[R] clk_x1:[R] 12.048 0.000 11.736
13 0.269 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/wr_data_add_23_s1/CE clk_x1:[R] clk_x1:[R] 12.048 0.000 11.736
14 0.269 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/wr_data_add_24_s1/CE clk_x1:[R] clk_x1:[R] 12.048 0.000 11.736
15 0.269 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/wr_data_add_25_s1/CE clk_x1:[R] clk_x1:[R] 12.048 0.000 11.736
16 0.269 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/wr_data_add_27_s1/CE clk_x1:[R] clk_x1:[R] 12.048 0.000 11.736
17 0.269 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/wr_data_add_29_s1/CE clk_x1:[R] clk_x1:[R] 12.048 0.000 11.736
18 0.269 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/wr_data_add_30_s1/CE clk_x1:[R] clk_x1:[R] 12.048 0.000 11.736
19 0.269 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/wr_data_add_31_s1/CE clk_x1:[R] clk_x1:[R] 12.048 0.000 11.736
20 0.278 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/wr_data_add_18_s1/CE clk_x1:[R] clk_x1:[R] 12.048 0.000 11.727
21 0.296 u_test0/cmd_en_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1/CE clk_x1:[R] clk_x1:[R] 12.048 0.000 11.708
22 0.296 u_test0/cmd_en_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1/CE clk_x1:[R] clk_x1:[R] 12.048 0.000 11.708
23 0.296 u_test0/cmd_en_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1/CE clk_x1:[R] clk_x1:[R] 12.048 0.000 11.708
24 0.429 u_PSRAM_TOP/u_psram_top1/u_psram_init/config_done_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[7].dq_oser4/TX0 clk_x1:[R] clk_x1:[R] 12.048 0.000 11.574
25 0.475 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q u_test0/wr_data_13_s3/D clk_x1:[R] clk_x1:[R] 12.048 0.000 11.173

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.479 u_PSRAM_TOP/u_psram_top0/rd_data_d_28_s0/Q u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[28] clk_x1:[R] clk_x1:[R] 0.000 0.000 0.565
2 0.479 u_PSRAM_TOP/u_psram_top0/rd_data_d_24_s0/Q u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[24] clk_x1:[R] clk_x1:[R] 0.000 0.000 0.565
3 0.479 u_PSRAM_TOP/u_psram_top0/rd_data_d_20_s0/Q u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[20] clk_x1:[R] clk_x1:[R] 0.000 0.000 0.565
4 0.479 u_PSRAM_TOP/u_psram_top0/rd_data_d_11_s0/Q u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[11] clk_x1:[R] clk_x1:[R] 0.000 0.000 0.565
5 0.479 u_PSRAM_TOP/u_psram_top0/rd_data_d_10_s0/Q u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[10] clk_x1:[R] clk_x1:[R] 0.000 0.000 0.565
6 0.512 u_PSRAM_TOP/u_psram_top0/rd_data_d_25_s0/Q u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[25] clk_x1:[R] clk_x1:[R] 0.000 0.000 0.598
7 0.512 u_PSRAM_TOP/u_psram_top0/rd_data_d_14_s0/Q u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[14] clk_x1:[R] clk_x1:[R] 0.000 0.000 0.598
8 0.567 u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/ms_t_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_7_s0/CE clk_x1:[R] clk_x1:[R] 0.000 0.000 0.579
9 0.567 u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/ms_t_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_8_s0/CE clk_x1:[R] clk_x1:[R] 0.000 0.000 0.579
10 0.567 u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/ms_t_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_9_s0/CE clk_x1:[R] clk_x1:[R] 0.000 0.000 0.579
11 0.570 u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0/Q u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.570
12 0.570 u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/Q u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.570
13 0.570 u_la0_top/internal_reg_force_triger_syn_0_s0/Q u_la0_top/internal_reg_force_triger_syn_1_s0/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.570
14 0.570 u_la0_top/rst_ao_syn_s0/Q u_la0_top/rst_ao_s0/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.570
15 0.571 u_la0_top/data_register_30_s0/Q u_la0_top/data_register_29_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.571
16 0.571 u_icon_top/input_shift_reg_1_s0/Q u_icon_top/module_id_reg_1_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.571
17 0.571 u_icon_top/enable_reg_2_s0/Q u_icon_top/enable_reg_1_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.571
18 0.572 u_la0_top/data_register_6_s0/Q u_la0_top/capture_mem_addr_max_6_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.572
19 0.572 u_la0_top/data_register_2_s0/Q u_la0_top/data_register_1_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.572
20 0.572 u_la0_top/data_register_28_s0/Q u_la0_top/data_register_27_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.572
21 0.572 u_la0_top/data_register_32_s0/Q u_la0_top/data_register_31_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.572
22 0.573 u_la0_top/data_register_7_s0/Q u_la0_top/capture_mem_addr_max_7_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.573
23 0.573 u_la0_top/data_register_3_s0/Q u_la0_top/data_register_2_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.573
24 0.573 u_la0_top/data_register_7_s0/Q u_la0_top/data_register_6_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.573
25 0.573 u_la0_top/data_register_34_s0/Q u_la0_top/data_register_33_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.573

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s1.ST_WAIT_s5/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
2 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4/PRESET clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
3 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dq_setn_0_s4/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
4 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/left_s4/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
5 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.IDLE_s1/PRESET clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
6 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s1.ST_IDLE_s1/PRESET clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
7 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.WAIT_ADJ_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
8 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.JUD_DATA_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
9 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.RIGHT_SHIFT_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
10 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.WAIT_S1_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
11 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_value_0_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
12 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_setn_0_s1/PRESET clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
13 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/req_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
14 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dq_value_0_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
15 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/error_0_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
16 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/error_1_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
17 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
18 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_1_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
19 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_2_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
20 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_3_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
21 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_4_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
22 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_5_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
23 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
24 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_data_r_3_s0/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578
25 8.426 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_r_s0/CLEAR clk_x1:[R] clk_x1:[R] 12.048 0.000 3.578

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.833 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_0_s3/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.845
2 0.842 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.854
3 0.842 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.854
4 0.842 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.854
5 0.842 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.854
6 0.842 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.854
7 0.902 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.915
8 0.902 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.915
9 0.905 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_start_dly_0_s0/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.917
10 0.905 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_start_syn_0_s0/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.917
11 0.906 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.919
12 0.906 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.919
13 0.906 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.919
14 0.906 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_0/trig_dly_1_s0/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.919
15 0.906 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET clk_x1:[R] clk_x1:[R] 0.000 0.000 0.919
16 0.906 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.919
17 0.906 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 0.919
18 1.103 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_4_s1/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 1.115
19 1.103 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_5_s1/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 1.115
20 1.103 u_la0_top/rst_ao_s0/Q u_la0_top/start_reg_s0/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 1.115
21 1.103 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_start_syn_1_s0/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 1.115
22 1.142 u_la0_top/rst_ao_s0/Q u_la0_top/capture_end_dly_s0/PRESET clk_x1:[R] clk_x1:[R] 0.000 0.000 1.155
23 1.166 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 1.179
24 1.166 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 1.179
25 1.167 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR clk_x1:[R] clk_x1:[R] 0.000 0.000 1.179

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 3.890 5.140 1.250 Low Pulse Width clk_x1 cnt_24_s0
2 3.890 5.140 1.250 Low Pulse Width clk_x1 cnt_23_s0
3 3.890 5.140 1.250 Low Pulse Width clk_x1 cnt_22_s0
4 3.890 5.140 1.250 Low Pulse Width clk_x1 cnt_19_s0
5 3.890 5.140 1.250 Low Pulse Width clk_x1 cnt_17_s0
6 3.890 5.140 1.250 Low Pulse Width clk_x1 cnt_16_s0
7 3.890 5.140 1.250 Low Pulse Width clk_x1 u_PSRAM_TOP/u_psram_top0/rdbk_data_19_s0
8 3.890 5.140 1.250 Low Pulse Width clk_x1 u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_r_4_s0
9 3.890 5.140 1.250 Low Pulse Width clk_x1 u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/cnt_s_10_s0
10 3.890 5.140 1.250 Low Pulse Width clk_x1 u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/s_t_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.019
Data Arrival Time 14.271
Data Required Time 14.290
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/addr_10_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R22C37[2][B] u_test0/wr_data_31_s8/I0
12.106 0.626 tINS FF 14 R22C37[2][B] u_test0/wr_data_31_s8/F
13.449 1.343 tNET FF 1 R20C39[1][B] u_test0/n935_s0/I0
14.271 0.822 tINS FF 1 R20C39[1][B] u_test0/n935_s0/F
14.271 0.000 tNET FF 1 R20C39[1][B] u_test0/addr_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R20C39[1][B] u_test0/addr_10_s0/CLK
14.290 -0.400 tSu 1 R20C39[1][B] u_test0/addr_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 4.272, 36.735%; route: 6.899, 59.324%; tC2Q: 0.458, 3.941%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path2

Path Summary:

Slack 0.019
Data Arrival Time 14.271
Data Required Time 14.290
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/addr_19_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R22C37[2][B] u_test0/wr_data_31_s8/I0
12.106 0.626 tINS FF 14 R22C37[2][B] u_test0/wr_data_31_s8/F
13.449 1.343 tNET FF 1 R22C41[2][A] u_test0/n926_s0/I0
14.271 0.822 tINS FF 1 R22C41[2][A] u_test0/n926_s0/F
14.271 0.000 tNET FF 1 R22C41[2][A] u_test0/addr_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R22C41[2][A] u_test0/addr_19_s0/CLK
14.290 -0.400 tSu 1 R22C41[2][A] u_test0/addr_19_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 4.272, 36.735%; route: 6.899, 59.324%; tC2Q: 0.458, 3.941%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path3

Path Summary:

Slack 0.019
Data Arrival Time 14.271
Data Required Time 14.290
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/addr_20_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R22C37[2][B] u_test0/wr_data_31_s8/I0
12.106 0.626 tINS FF 14 R22C37[2][B] u_test0/wr_data_31_s8/F
13.449 1.343 tNET FF 1 R22C41[2][B] u_test0/n925_s0/I0
14.271 0.822 tINS FF 1 R22C41[2][B] u_test0/n925_s0/F
14.271 0.000 tNET FF 1 R22C41[2][B] u_test0/addr_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R22C41[2][B] u_test0/addr_20_s0/CLK
14.290 -0.400 tSu 1 R22C41[2][B] u_test0/addr_20_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 4.272, 36.735%; route: 6.899, 59.324%; tC2Q: 0.458, 3.941%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path4

Path Summary:

Slack 0.093
Data Arrival Time 14.197
Data Required Time 14.290
From u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4
To u_test1/addr_13_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R22C30[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R22C30[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4/Q
3.907 0.807 tNET FF 1 R20C30[3][B] u_PSRAM_TOP/u_psram_top1/cmd_rdy1_d_s/I1
5.006 1.099 tINS FF 7 R20C30[3][B] u_PSRAM_TOP/u_psram_top1/cmd_rdy1_d_s/F
7.125 2.119 tNET FF 1 R12C37[3][B] u_test1/wr_data_31_s4/I0
8.224 1.099 tINS FF 54 R12C37[3][B] u_test1/wr_data_31_s4/F
10.250 2.026 tNET FF 1 R9C39[1][B] u_test1/wr_data_31_s8/I1
11.349 1.099 tINS FF 14 R9C39[1][B] u_test1/wr_data_31_s8/F
13.165 1.816 tNET FF 1 R6C40[1][A] u_test1/n932_s0/I0
14.197 1.032 tINS FF 1 R6C40[1][A] u_test1/n932_s0/F
14.197 0.000 tNET FF 1 R6C40[1][A] u_test1/addr_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R6C40[1][A] u_test1/addr_13_s0/CLK
14.290 -0.400 tSu 1 R6C40[1][A] u_test1/addr_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 4.329, 37.465%; route: 6.767, 58.568%; tC2Q: 0.458, 3.967%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path5

Path Summary:

Slack 0.166
Data Arrival Time 14.124
Data Required Time 14.290
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/addr_11_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R22C37[2][B] u_test0/wr_data_31_s8/I0
12.106 0.626 tINS FF 14 R22C37[2][B] u_test0/wr_data_31_s8/F
13.092 0.986 tNET FF 1 R20C39[0][B] u_test0/n934_s0/I0
14.124 1.032 tINS FF 1 R20C39[0][B] u_test0/n934_s0/F
14.124 0.000 tNET FF 1 R20C39[0][B] u_test0/addr_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R20C39[0][B] u_test0/addr_11_s0/CLK
14.290 -0.400 tSu 1 R20C39[0][B] u_test0/addr_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 4.482, 39.035%; route: 6.542, 56.973%; tC2Q: 0.458, 3.992%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path6

Path Summary:

Slack 0.168
Data Arrival Time 14.121
Data Required Time 14.290
From u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4
To u_test1/addr_14_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R22C30[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R22C30[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4/Q
3.907 0.807 tNET FF 1 R20C30[3][B] u_PSRAM_TOP/u_psram_top1/cmd_rdy1_d_s/I1
5.006 1.099 tINS FF 7 R20C30[3][B] u_PSRAM_TOP/u_psram_top1/cmd_rdy1_d_s/F
7.125 2.119 tNET FF 1 R12C37[3][B] u_test1/wr_data_31_s4/I0
8.224 1.099 tINS FF 54 R12C37[3][B] u_test1/wr_data_31_s4/F
10.250 2.026 tNET FF 1 R9C39[1][B] u_test1/wr_data_31_s8/I1
11.349 1.099 tINS FF 14 R9C39[1][B] u_test1/wr_data_31_s8/F
13.495 2.147 tNET FF 1 R6C40[2][A] u_test1/n931_s0/I0
14.121 0.626 tINS FF 1 R6C40[2][A] u_test1/n931_s0/F
14.121 0.000 tNET FF 1 R6C40[2][A] u_test1/addr_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R6C40[2][A] u_test1/addr_14_s0/CLK
14.290 -0.400 tSu 1 R6C40[2][A] u_test1/addr_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.923, 34.174%; route: 7.098, 61.834%; tC2Q: 0.458, 3.993%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path7

Path Summary:

Slack 0.185
Data Arrival Time 14.105
Data Required Time 14.290
From u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4
To u_test1/addr_8_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R22C30[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R22C30[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4/Q
3.907 0.807 tNET FF 1 R20C30[3][B] u_PSRAM_TOP/u_psram_top1/cmd_rdy1_d_s/I1
5.006 1.099 tINS FF 7 R20C30[3][B] u_PSRAM_TOP/u_psram_top1/cmd_rdy1_d_s/F
7.125 2.119 tNET FF 1 R12C37[3][B] u_test1/wr_data_31_s4/I0
8.224 1.099 tINS FF 54 R12C37[3][B] u_test1/wr_data_31_s4/F
10.250 2.026 tNET FF 1 R9C39[1][B] u_test1/wr_data_31_s8/I1
11.349 1.099 tINS FF 14 R9C39[1][B] u_test1/wr_data_31_s8/F
13.006 1.658 tNET FF 1 R7C40[1][B] u_test1/n937_s0/I0
14.105 1.099 tINS FF 1 R7C40[1][B] u_test1/n937_s0/F
14.105 0.000 tNET FF 1 R7C40[1][B] u_test1/addr_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R7C40[1][B] u_test1/addr_8_s0/CLK
14.290 -0.400 tSu 1 R7C40[1][B] u_test1/addr_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 4.396, 38.348%; route: 6.609, 57.654%; tC2Q: 0.458, 3.998%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path8

Path Summary:

Slack 0.215
Data Arrival Time 14.075
Data Required Time 14.290
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/addr_15_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R22C37[2][B] u_test0/wr_data_31_s8/I0
12.106 0.626 tINS FF 14 R22C37[2][B] u_test0/wr_data_31_s8/F
13.449 1.343 tNET FF 1 R20C39[2][B] u_test0/n930_s0/I0
14.075 0.626 tINS FF 1 R20C39[2][B] u_test0/n930_s0/F
14.075 0.000 tNET FF 1 R20C39[2][B] u_test0/addr_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R20C39[2][B] u_test0/addr_15_s0/CLK
14.290 -0.400 tSu 1 R20C39[2][B] u_test0/addr_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 4.076, 35.650%; route: 6.899, 60.341%; tC2Q: 0.458, 4.009%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path9

Path Summary:

Slack 0.219
Data Arrival Time 14.071
Data Required Time 14.290
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/addr_7_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R22C37[2][B] u_test0/wr_data_31_s8/I0
12.106 0.626 tINS FF 14 R22C37[2][B] u_test0/wr_data_31_s8/F
13.445 1.338 tNET FF 1 R21C39[2][A] u_test0/n938_s0/I0
14.071 0.626 tINS FF 1 R21C39[2][A] u_test0/n938_s0/F
14.071 0.000 tNET FF 1 R21C39[2][A] u_test0/addr_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R21C39[2][A] u_test0/addr_7_s0/CLK
14.290 -0.400 tSu 1 R21C39[2][A] u_test0/addr_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 4.076, 35.664%; route: 6.894, 60.325%; tC2Q: 0.458, 4.010%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path10

Path Summary:

Slack 0.241
Data Arrival Time 14.049
Data Required Time 14.290
From u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_1_s1
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R18C30[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_1_s1/CLK
3.100 0.458 tC2Q RF 8 R18C30[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_1_s1/Q
4.889 1.789 tNET FF 2 R16C27[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s15/I1
5.439 0.550 tINS FR 1 R16C27[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s15/COUT
5.439 0.000 tNET RR 2 R16C27[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s16/CIN
5.496 0.057 tINS RF 1 R16C27[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s16/COUT
5.496 0.000 tNET FF 2 R16C27[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s17/CIN
5.550 0.054 tINS FR 1 R16C27[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s17/COUT
6.497 0.947 tNET RR 1 R16C28[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s21/I0
7.319 0.822 tINS RF 1 R16C28[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s21/F
7.809 0.490 tNET FF 1 R16C30[3][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s19/I1
8.611 0.802 tINS FR 5 R16C30[3][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s19/F
9.044 0.433 tNET RR 1 R17C30[0][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n730_s7/I3
10.143 1.099 tINS RF 1 R17C30[0][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n730_s7/F
10.148 0.005 tNET FF 1 R17C30[0][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n730_s4/I1
10.774 0.626 tINS FF 7 R17C30[0][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n730_s4/F
11.601 0.826 tNET FF 1 R18C31[2][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n729_s9/I2
12.423 0.822 tINS FF 1 R18C31[2][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n729_s9/F
13.227 0.804 tNET FF 1 R17C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n729_s5/I3
14.049 0.822 tINS FF 1 R17C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n729_s5/F
14.049 0.000 tNET FF 1 R17C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R17C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1/CLK
14.290 -0.400 tSu 1 R17C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 5.654, 49.566%; route: 5.295, 46.416%; tC2Q: 0.458, 4.018%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path11

Path Summary:

Slack 0.269
Data Arrival Time 14.378
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/wr_data_add_10_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R23C38[3][A] u_test0/wr_data_add_31_s4/I2
12.105 0.625 tINS FR 31 R23C38[3][A] u_test0/wr_data_add_31_s4/F
14.378 2.272 tNET RR 1 R23C34[0][B] u_test0/wr_data_add_10_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R23C34[0][B] u_test0/wr_data_add_10_s1/CLK
14.647 -0.043 tSu 1 R23C34[0][B] u_test0/wr_data_add_10_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.449, 29.389%; route: 7.829, 66.706%; tC2Q: 0.458, 3.905%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path12

Path Summary:

Slack 0.269
Data Arrival Time 14.378
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/wr_data_add_20_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R23C38[3][A] u_test0/wr_data_add_31_s4/I2
12.105 0.625 tINS FR 31 R23C38[3][A] u_test0/wr_data_add_31_s4/F
14.378 2.272 tNET RR 1 R23C34[2][B] u_test0/wr_data_add_20_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R23C34[2][B] u_test0/wr_data_add_20_s1/CLK
14.647 -0.043 tSu 1 R23C34[2][B] u_test0/wr_data_add_20_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.449, 29.389%; route: 7.829, 66.706%; tC2Q: 0.458, 3.905%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path13

Path Summary:

Slack 0.269
Data Arrival Time 14.378
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/wr_data_add_23_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R23C38[3][A] u_test0/wr_data_add_31_s4/I2
12.105 0.625 tINS FR 31 R23C38[3][A] u_test0/wr_data_add_31_s4/F
14.378 2.272 tNET RR 1 R23C34[1][B] u_test0/wr_data_add_23_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R23C34[1][B] u_test0/wr_data_add_23_s1/CLK
14.647 -0.043 tSu 1 R23C34[1][B] u_test0/wr_data_add_23_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.449, 29.389%; route: 7.829, 66.706%; tC2Q: 0.458, 3.905%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path14

Path Summary:

Slack 0.269
Data Arrival Time 14.378
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/wr_data_add_24_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R23C38[3][A] u_test0/wr_data_add_31_s4/I2
12.105 0.625 tINS FR 31 R23C38[3][A] u_test0/wr_data_add_31_s4/F
14.378 2.272 tNET RR 1 R23C34[1][A] u_test0/wr_data_add_24_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R23C34[1][A] u_test0/wr_data_add_24_s1/CLK
14.647 -0.043 tSu 1 R23C34[1][A] u_test0/wr_data_add_24_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.449, 29.389%; route: 7.829, 66.706%; tC2Q: 0.458, 3.905%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path15

Path Summary:

Slack 0.269
Data Arrival Time 14.378
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/wr_data_add_25_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R23C38[3][A] u_test0/wr_data_add_31_s4/I2
12.105 0.625 tINS FR 31 R23C38[3][A] u_test0/wr_data_add_31_s4/F
14.378 2.272 tNET RR 1 R23C34[2][A] u_test0/wr_data_add_25_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R23C34[2][A] u_test0/wr_data_add_25_s1/CLK
14.647 -0.043 tSu 1 R23C34[2][A] u_test0/wr_data_add_25_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.449, 29.389%; route: 7.829, 66.706%; tC2Q: 0.458, 3.905%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path16

Path Summary:

Slack 0.269
Data Arrival Time 14.378
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/wr_data_add_27_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R23C38[3][A] u_test0/wr_data_add_31_s4/I2
12.105 0.625 tINS FR 31 R23C38[3][A] u_test0/wr_data_add_31_s4/F
14.378 2.272 tNET RR 1 R23C33[1][A] u_test0/wr_data_add_27_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R23C33[1][A] u_test0/wr_data_add_27_s1/CLK
14.647 -0.043 tSu 1 R23C33[1][A] u_test0/wr_data_add_27_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.449, 29.389%; route: 7.829, 66.706%; tC2Q: 0.458, 3.905%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path17

Path Summary:

Slack 0.269
Data Arrival Time 14.378
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/wr_data_add_29_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R23C38[3][A] u_test0/wr_data_add_31_s4/I2
12.105 0.625 tINS FR 31 R23C38[3][A] u_test0/wr_data_add_31_s4/F
14.378 2.272 tNET RR 1 R23C33[2][A] u_test0/wr_data_add_29_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R23C33[2][A] u_test0/wr_data_add_29_s1/CLK
14.647 -0.043 tSu 1 R23C33[2][A] u_test0/wr_data_add_29_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.449, 29.389%; route: 7.829, 66.706%; tC2Q: 0.458, 3.905%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path18

Path Summary:

Slack 0.269
Data Arrival Time 14.378
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/wr_data_add_30_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R23C38[3][A] u_test0/wr_data_add_31_s4/I2
12.105 0.625 tINS FR 31 R23C38[3][A] u_test0/wr_data_add_31_s4/F
14.378 2.272 tNET RR 1 R23C33[2][B] u_test0/wr_data_add_30_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R23C33[2][B] u_test0/wr_data_add_30_s1/CLK
14.647 -0.043 tSu 1 R23C33[2][B] u_test0/wr_data_add_30_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.449, 29.389%; route: 7.829, 66.706%; tC2Q: 0.458, 3.905%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path19

Path Summary:

Slack 0.269
Data Arrival Time 14.378
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/wr_data_add_31_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R23C38[3][A] u_test0/wr_data_add_31_s4/I2
12.105 0.625 tINS FR 31 R23C38[3][A] u_test0/wr_data_add_31_s4/F
14.378 2.272 tNET RR 1 R23C33[0][A] u_test0/wr_data_add_31_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R23C33[0][A] u_test0/wr_data_add_31_s1/CLK
14.647 -0.043 tSu 1 R23C33[0][A] u_test0/wr_data_add_31_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.449, 29.389%; route: 7.829, 66.706%; tC2Q: 0.458, 3.905%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path20

Path Summary:

Slack 0.278
Data Arrival Time 14.369
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/wr_data_add_18_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
11.480 1.316 tNET FF 1 R23C38[3][A] u_test0/wr_data_add_31_s4/I2
12.105 0.625 tINS FR 31 R23C38[3][A] u_test0/wr_data_add_31_s4/F
14.369 2.263 tNET RR 1 R24C36[1][A] u_test0/wr_data_add_18_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R24C36[1][A] u_test0/wr_data_add_18_s1/CLK
14.647 -0.043 tSu 1 R24C36[1][A] u_test0/wr_data_add_18_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.449, 29.412%; route: 7.819, 66.680%; tC2Q: 0.458, 3.908%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path21

Path Summary:

Slack 0.296
Data Arrival Time 14.350
Data Required Time 14.647
From u_test0/cmd_en_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R20C39[2][A] u_test0/cmd_en_s0/CLK
3.100 0.458 tC2Q RF 5 R20C39[2][A] u_test0/cmd_en_s0/Q
7.164 4.064 tNET FF 1 R8C16[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/n2066_s0/I1
7.986 0.822 tINS FF 27 R8C16[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/n2066_s0/F
9.954 1.968 tNET FF 1 R9C14[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_en_s0/I3
10.776 0.822 tINS FF 12 R9C14[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_en_s0/F
11.608 0.832 tNET FF 1 R8C13[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
12.410 0.802 tINS FR 4 R8C13[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
12.837 0.427 tNET RR 1 R8C14[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s8/I2
13.639 0.802 tINS RR 3 R8C14[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s8/F
14.350 0.711 tNET RR 1 R6C14[1][A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R6C14[1][A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1/CLK
14.647 -0.043 tSu 1 R6C14[1][A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.248, 27.741%; route: 8.002, 68.345%; tC2Q: 0.458, 3.915%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path22

Path Summary:

Slack 0.296
Data Arrival Time 14.350
Data Required Time 14.647
From u_test0/cmd_en_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R20C39[2][A] u_test0/cmd_en_s0/CLK
3.100 0.458 tC2Q RF 5 R20C39[2][A] u_test0/cmd_en_s0/Q
7.164 4.064 tNET FF 1 R8C16[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/n2066_s0/I1
7.986 0.822 tINS FF 27 R8C16[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/n2066_s0/F
9.954 1.968 tNET FF 1 R9C14[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_en_s0/I3
10.776 0.822 tINS FF 12 R9C14[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_en_s0/F
11.608 0.832 tNET FF 1 R8C13[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
12.410 0.802 tINS FR 4 R8C13[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
12.837 0.427 tNET RR 1 R8C14[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s8/I2
13.639 0.802 tINS RR 3 R8C14[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s8/F
14.350 0.711 tNET RR 1 R6C14[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R6C14[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1/CLK
14.647 -0.043 tSu 1 R6C14[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.248, 27.741%; route: 8.002, 68.345%; tC2Q: 0.458, 3.915%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path23

Path Summary:

Slack 0.296
Data Arrival Time 14.350
Data Required Time 14.647
From u_test0/cmd_en_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R20C39[2][A] u_test0/cmd_en_s0/CLK
3.100 0.458 tC2Q RF 5 R20C39[2][A] u_test0/cmd_en_s0/Q
7.164 4.064 tNET FF 1 R8C16[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/n2066_s0/I1
7.986 0.822 tINS FF 27 R8C16[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/n2066_s0/F
9.954 1.968 tNET FF 1 R9C14[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_en_s0/I3
10.776 0.822 tINS FF 12 R9C14[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_en_s0/F
11.608 0.832 tNET FF 1 R8C13[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
12.410 0.802 tINS FR 4 R8C13[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
12.837 0.427 tNET RR 1 R8C14[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s8/I2
13.639 0.802 tINS RR 3 R8C14[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s8/F
14.350 0.711 tNET RR 1 R6C14[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R6C14[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1/CLK
14.647 -0.043 tSu 1 R6C14[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.248, 27.741%; route: 8.002, 68.345%; tC2Q: 0.458, 3.915%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path24

Path Summary:

Slack 0.429
Data Arrival Time 14.216
Data Required Time 14.645
From u_PSRAM_TOP/u_psram_top1/u_psram_init/config_done_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[7].dq_oser4
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R24C21[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/config_done_s0/CLK
3.100 0.458 tC2Q RF 35 R24C21[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/config_done_s0/Q
7.205 4.105 tNET FF 1 R20C12[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n1452_s1/I3
8.237 1.032 tINS FF 9 R20C12[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n1452_s1/F
9.537 1.300 tNET FF 1 R18C10[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n1451_s1/I3
10.636 1.099 tINS FF 8 R18C10[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n1451_s1/F
14.216 3.580 tNET FF 1 IOL27[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[7].dq_oser4/TX0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 IOL27[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[7].dq_oser4/PCLK
14.645 -0.045 tSu 1 IOL27[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[7].dq_oser4

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 2.131, 18.411%; route: 8.985, 77.629%; tC2Q: 0.458, 3.960%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path25

Path Summary:

Slack 0.475
Data Arrival Time 13.815
Data Required Time 14.290
From u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4
To u_test0/wr_data_13_s3
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100 0.458 tC2Q RF 5 R13C19[1][A] u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/adj_done_s4/Q
3.923 0.822 tNET FF 1 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1
5.022 1.099 tINS FF 7 R15C19[1][B] u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F
8.434 3.412 tNET FF 1 R21C40[1][B] u_test0/n484_s2/I0
9.060 0.626 tINS FF 1 R21C40[1][B] u_test0/n484_s2/F
9.065 0.005 tNET FF 1 R21C40[2][A] u_test0/wr_data_31_s5/I0
10.164 1.099 tINS FF 68 R21C40[2][A] u_test0/wr_data_31_s5/F
12.993 2.829 tNET FF 1 R24C39[0][A] u_test0/n728_s3/I3
13.815 0.822 tINS FF 1 R24C39[0][A] u_test0/n728_s3/F
13.815 0.000 tNET FF 1 R24C39[0][A] u_test0/wr_data_13_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R24C39[0][A] u_test0/wr_data_13_s3/CLK
14.290 -0.400 tSu 1 R24C39[0][A] u_test0/wr_data_13_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 3.646, 32.633%; route: 7.068, 63.264%; tC2Q: 0.458, 4.102%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.479
Data Arrival Time 2.326
Data Required Time 1.848
From u_PSRAM_TOP/u_psram_top0/rd_data_d_28_s0
To u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R9C25[0][B] u_PSRAM_TOP/u_psram_top0/rd_data_d_28_s0/CLK
2.095 0.333 tC2Q RF 1 R9C25[0][B] u_PSRAM_TOP/u_psram_top0/rd_data_d_28_s0/Q
2.326 0.231 tNET FF 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[28]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
1.848 0.086 tHld 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.231, 40.960%; tC2Q: 0.333, 59.040%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path2

Path Summary:

Slack 0.479
Data Arrival Time 2.326
Data Required Time 1.848
From u_PSRAM_TOP/u_psram_top0/rd_data_d_24_s0
To u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R9C25[2][B] u_PSRAM_TOP/u_psram_top0/rd_data_d_24_s0/CLK
2.095 0.333 tC2Q RF 1 R9C25[2][B] u_PSRAM_TOP/u_psram_top0/rd_data_d_24_s0/Q
2.326 0.231 tNET FF 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[24]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
1.848 0.086 tHld 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.231, 40.960%; tC2Q: 0.333, 59.040%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path3

Path Summary:

Slack 0.479
Data Arrival Time 2.326
Data Required Time 1.848
From u_PSRAM_TOP/u_psram_top0/rd_data_d_20_s0
To u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R11C24[0][B] u_PSRAM_TOP/u_psram_top0/rd_data_d_20_s0/CLK
2.095 0.333 tC2Q RF 1 R11C24[0][B] u_PSRAM_TOP/u_psram_top0/rd_data_d_20_s0/Q
2.326 0.231 tNET FF 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[20]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
1.848 0.086 tHld 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.231, 40.960%; tC2Q: 0.333, 59.040%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path4

Path Summary:

Slack 0.479
Data Arrival Time 2.326
Data Required Time 1.848
From u_PSRAM_TOP/u_psram_top0/rd_data_d_11_s0
To u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R9C24[0][B] u_PSRAM_TOP/u_psram_top0/rd_data_d_11_s0/CLK
2.095 0.333 tC2Q RF 1 R9C24[0][B] u_PSRAM_TOP/u_psram_top0/rd_data_d_11_s0/Q
2.326 0.231 tNET FF 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[11]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
1.848 0.086 tHld 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.231, 40.960%; tC2Q: 0.333, 59.040%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path5

Path Summary:

Slack 0.479
Data Arrival Time 2.326
Data Required Time 1.848
From u_PSRAM_TOP/u_psram_top0/rd_data_d_10_s0
To u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R9C24[2][A] u_PSRAM_TOP/u_psram_top0/rd_data_d_10_s0/CLK
2.095 0.333 tC2Q RF 1 R9C24[2][A] u_PSRAM_TOP/u_psram_top0/rd_data_d_10_s0/Q
2.326 0.231 tNET FF 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
1.848 0.086 tHld 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.231, 40.960%; tC2Q: 0.333, 59.040%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path6

Path Summary:

Slack 0.512
Data Arrival Time 2.360
Data Required Time 1.848
From u_PSRAM_TOP/u_psram_top0/rd_data_d_25_s0
To u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R9C25[1][B] u_PSRAM_TOP/u_psram_top0/rd_data_d_25_s0/CLK
2.095 0.333 tC2Q RR 1 R9C25[1][B] u_PSRAM_TOP/u_psram_top0/rd_data_d_25_s0/Q
2.360 0.265 tNET RR 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[25]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
1.848 0.086 tHld 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.265, 44.283%; tC2Q: 0.333, 55.717%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path7

Path Summary:

Slack 0.512
Data Arrival Time 2.360
Data Required Time 1.848
From u_PSRAM_TOP/u_psram_top0/rd_data_d_14_s0
To u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R12C24[0][A] u_PSRAM_TOP/u_psram_top0/rd_data_d_14_s0/CLK
2.095 0.333 tC2Q RR 1 R12C24[0][A] u_PSRAM_TOP/u_psram_top0/rd_data_d_14_s0/Q
2.360 0.265 tNET RR 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[14]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
1.848 0.086 tHld 1 BSRAM_R10[6] u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.265, 44.283%; tC2Q: 0.333, 55.717%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path8

Path Summary:

Slack 0.567
Data Arrival Time 2.341
Data Required Time 1.774
From u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/ms_t_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_7_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R23C27[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/ms_t_s0/CLK
2.095 0.333 tC2Q RR 14 R23C27[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/ms_t_s0/Q
2.341 0.246 tNET RR 1 R23C27[0][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_7_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R23C27[0][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_7_s0/CLK
1.774 0.012 tHld 1 R23C27[0][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.246, 42.477%; tC2Q: 0.333, 57.523%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path9

Path Summary:

Slack 0.567
Data Arrival Time 2.341
Data Required Time 1.774
From u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/ms_t_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_8_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R23C27[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/ms_t_s0/CLK
2.095 0.333 tC2Q RR 14 R23C27[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/ms_t_s0/Q
2.341 0.246 tNET RR 1 R23C27[0][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_8_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R23C27[0][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_8_s0/CLK
1.774 0.012 tHld 1 R23C27[0][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.246, 42.477%; tC2Q: 0.333, 57.523%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path10

Path Summary:

Slack 0.567
Data Arrival Time 2.341
Data Required Time 1.774
From u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/ms_t_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_9_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R23C27[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/ms_t_s0/CLK
2.095 0.333 tC2Q RR 14 R23C27[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/ms_t_s0/Q
2.341 0.246 tNET RR 1 R23C27[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_9_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R23C27[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_9_s0/CLK
1.774 0.012 tHld 1 R23C27[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/cnt_s_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.246, 42.477%; tC2Q: 0.333, 57.523%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path11

Path Summary:

Slack 0.570
Data Arrival Time 2.331
Data Required Time 1.762
From u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0
To u_la0_top/u_ao_mem_ctrl/data_reg_0_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R11C8[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0/CLK
2.095 0.333 tC2Q RR 1 R11C8[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0/Q
2.331 0.236 tNET RR 1 R11C8[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R11C8[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK
1.762 0.000 tHld 1 R11C8[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path12

Path Summary:

Slack 0.570
Data Arrival Time 2.331
Data Required Time 1.762
From u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0
To u_la0_top/u_ao_mem_ctrl/data_reg_3_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R9C10[0][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/CLK
2.095 0.333 tC2Q RR 1 R9C10[0][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/Q
2.331 0.236 tNET RR 1 R9C10[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R9C10[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/CLK
1.762 0.000 tHld 1 R9C10[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path13

Path Summary:

Slack 0.570
Data Arrival Time 2.331
Data Required Time 1.762
From u_la0_top/internal_reg_force_triger_syn_0_s0
To u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R2C3[0][A] u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
2.095 0.333 tC2Q RR 1 R2C3[0][A] u_la0_top/internal_reg_force_triger_syn_0_s0/Q
2.331 0.236 tNET RR 1 R2C3[0][B] u_la0_top/internal_reg_force_triger_syn_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R2C3[0][B] u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
1.762 0.000 tHld 1 R2C3[0][B] u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path14

Path Summary:

Slack 0.570
Data Arrival Time 2.331
Data Required Time 1.762
From u_la0_top/rst_ao_syn_s0
To u_la0_top/rst_ao_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][A] u_la0_top/rst_ao_syn_s0/CLK
2.095 0.333 tC2Q RR 1 R5C5[2][A] u_la0_top/rst_ao_syn_s0/Q
2.331 0.236 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
1.762 0.000 tHld 1 R5C5[2][B] u_la0_top/rst_ao_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path15

Path Summary:

Slack 0.571
Data Arrival Time 7.085
Data Required Time 6.514
From u_la0_top/data_register_30_s0
To u_la0_top/data_register_29_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_30_s0/CLK
6.847 0.333 tC2Q RR 3 u_la0_top/data_register_30_s0/Q
7.085 0.238 tNET RR 1 u_la0_top/data_register_29_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_29_s0/CLK
6.514 0.000 tHld 1 u_la0_top/data_register_29_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%

Path16

Path Summary:

Slack 0.571
Data Arrival Time 7.085
Data Required Time 6.514
From u_icon_top/input_shift_reg_1_s0
To u_icon_top/module_id_reg_1_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_icon_top/input_shift_reg_1_s0/CLK
6.847 0.333 tC2Q RR 2 u_icon_top/input_shift_reg_1_s0/Q
7.085 0.238 tNET RR 1 u_icon_top/module_id_reg_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_icon_top/module_id_reg_1_s0/CLK
6.514 0.000 tHld 1 u_icon_top/module_id_reg_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%

Path17

Path Summary:

Slack 0.571
Data Arrival Time 7.085
Data Required Time 6.514
From u_icon_top/enable_reg_2_s0
To u_icon_top/enable_reg_1_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_icon_top/enable_reg_2_s0/CLK
6.847 0.333 tC2Q RR 3 u_icon_top/enable_reg_2_s0/Q
7.085 0.238 tNET RR 1 u_icon_top/enable_reg_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_icon_top/enable_reg_1_s0/CLK
6.514 0.000 tHld 1 u_icon_top/enable_reg_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%

Path18

Path Summary:

Slack 0.572
Data Arrival Time 7.086
Data Required Time 6.514
From u_la0_top/data_register_6_s0
To u_la0_top/capture_mem_addr_max_6_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_6_s0/CLK
6.847 0.333 tC2Q RR 5 u_la0_top/data_register_6_s0/Q
7.086 0.239 tNET RR 1 u_la0_top/capture_mem_addr_max_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/capture_mem_addr_max_6_s0/CLK
6.514 0.000 tHld 1 u_la0_top/capture_mem_addr_max_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%

Path19

Path Summary:

Slack 0.572
Data Arrival Time 7.086
Data Required Time 6.514
From u_la0_top/data_register_2_s0
To u_la0_top/data_register_1_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_2_s0/CLK
6.847 0.333 tC2Q RR 6 u_la0_top/data_register_2_s0/Q
7.086 0.239 tNET RR 1 u_la0_top/data_register_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_1_s0/CLK
6.514 0.000 tHld 1 u_la0_top/data_register_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%

Path20

Path Summary:

Slack 0.572
Data Arrival Time 7.086
Data Required Time 6.514
From u_la0_top/data_register_28_s0
To u_la0_top/data_register_27_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_28_s0/CLK
6.847 0.333 tC2Q RR 3 u_la0_top/data_register_28_s0/Q
7.086 0.239 tNET RR 1 u_la0_top/data_register_27_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_27_s0/CLK
6.514 0.000 tHld 1 u_la0_top/data_register_27_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%

Path21

Path Summary:

Slack 0.572
Data Arrival Time 7.086
Data Required Time 6.514
From u_la0_top/data_register_32_s0
To u_la0_top/data_register_31_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_32_s0/CLK
6.847 0.333 tC2Q RR 3 u_la0_top/data_register_32_s0/Q
7.086 0.239 tNET RR 1 u_la0_top/data_register_31_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_31_s0/CLK
6.514 0.000 tHld 1 u_la0_top/data_register_31_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%

Path22

Path Summary:

Slack 0.573
Data Arrival Time 7.087
Data Required Time 6.514
From u_la0_top/data_register_7_s0
To u_la0_top/capture_mem_addr_max_7_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_7_s0/CLK
6.847 0.333 tC2Q RR 5 u_la0_top/data_register_7_s0/Q
7.087 0.240 tNET RR 1 u_la0_top/capture_mem_addr_max_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/capture_mem_addr_max_7_s0/CLK
6.514 0.000 tHld 1 u_la0_top/capture_mem_addr_max_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.240, 41.854%; tC2Q: 0.333, 58.146%
Required Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%

Path23

Path Summary:

Slack 0.573
Data Arrival Time 7.087
Data Required Time 6.514
From u_la0_top/data_register_3_s0
To u_la0_top/data_register_2_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_3_s0/CLK
6.847 0.333 tC2Q RR 6 u_la0_top/data_register_3_s0/Q
7.087 0.240 tNET RR 1 u_la0_top/data_register_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_2_s0/CLK
6.514 0.000 tHld 1 u_la0_top/data_register_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.240, 41.854%; tC2Q: 0.333, 58.146%
Required Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%

Path24

Path Summary:

Slack 0.573
Data Arrival Time 7.087
Data Required Time 6.514
From u_la0_top/data_register_7_s0
To u_la0_top/data_register_6_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_7_s0/CLK
6.847 0.333 tC2Q RR 5 u_la0_top/data_register_7_s0/Q
7.087 0.240 tNET RR 1 u_la0_top/data_register_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_6_s0/CLK
6.514 0.000 tHld 1 u_la0_top/data_register_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.240, 41.854%; tC2Q: 0.333, 58.146%
Required Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%

Path25

Path Summary:

Slack 0.573
Data Arrival Time 7.087
Data Required Time 6.514
From u_la0_top/data_register_34_s0
To u_la0_top/data_register_33_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_34_s0/CLK
6.847 0.333 tC2Q RR 4 u_la0_top/data_register_34_s0/Q
7.087 0.240 tNET RR 1 u_la0_top/data_register_33_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 tck_ibuf/I
3.126 3.126 tINS RR 1 tck_ibuf/O
3.126 0.000 tNET RR 1 u_gw_jtag/tck_pad_i
3.971 0.844 tINS RR 209 u_gw_jtag/tck_o
6.514 2.543 tNET RR 1 u_la0_top/data_register_33_s0/CLK
6.514 0.000 tHld 1 u_la0_top/data_register_33_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.240, 41.854%; tC2Q: 0.333, 58.146%
Required Clock Path Delay cell: 3.971, 60.960%; route: 2.543, 39.040%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s1.ST_WAIT_s5
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R21C30[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s1.ST_WAIT_s5/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R21C30[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s1.ST_WAIT_s5/CLK
14.647 -0.043 tSu 1 R21C30[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s1.ST_WAIT_s5

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path2

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R22C30[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R22C30[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4/CLK
14.647 -0.043 tSu 1 R22C30[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_s4

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path3

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dq_setn_0_s4
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R18C29[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dq_setn_0_s4/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R18C29[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dq_setn_0_s4/CLK
14.647 -0.043 tSu 1 R18C29[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dq_setn_0_s4

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path4

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/left_s4
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R21C32[0][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/left_s4/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R21C32[0][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/left_s4/CLK
14.647 -0.043 tSu 1 R21C32[0][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/left_s4

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path5

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.IDLE_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R22C31[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.IDLE_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R22C31[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.IDLE_s1/CLK
14.647 -0.043 tSu 1 R22C31[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.IDLE_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path6

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s1.ST_IDLE_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R22C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s1.ST_IDLE_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R22C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s1.ST_IDLE_s1/CLK
14.647 -0.043 tSu 1 R22C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s1.ST_IDLE_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path7

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.WAIT_ADJ_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R23C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.WAIT_ADJ_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R23C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.WAIT_ADJ_s1/CLK
14.647 -0.043 tSu 1 R23C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.WAIT_ADJ_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path8

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.JUD_DATA_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R21C31[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.JUD_DATA_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R21C31[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.JUD_DATA_s1/CLK
14.647 -0.043 tSu 1 R21C31[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.JUD_DATA_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path9

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.RIGHT_SHIFT_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R18C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.RIGHT_SHIFT_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R18C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.RIGHT_SHIFT_s1/CLK
14.647 -0.043 tSu 1 R18C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.RIGHT_SHIFT_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path10

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.WAIT_S1_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R21C31[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.WAIT_S1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R21C31[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.WAIT_S1_s1/CLK
14.647 -0.043 tSu 1 R21C31[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/c_s0.WAIT_S1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path11

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_value_0_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R16C31[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_value_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R16C31[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_value_0_s1/CLK
14.647 -0.043 tSu 1 R16C31[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_value_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path12

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_setn_0_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R18C29[0][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_setn_0_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R18C29[0][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_setn_0_s1/CLK
14.647 -0.043 tSu 1 R18C29[0][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_setn_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path13

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/req_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R21C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/req_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R21C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/req_s1/CLK
14.647 -0.043 tSu 1 R21C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/req_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path14

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dq_value_0_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R17C29[0][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dq_value_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R17C29[0][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dq_value_0_s1/CLK
14.647 -0.043 tSu 1 R17C29[0][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dq_value_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path15

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/error_0_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R22C31[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/error_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R22C31[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/error_0_s1/CLK
14.647 -0.043 tSu 1 R22C31[1][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/error_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path16

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/error_1_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R22C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/error_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R22C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/error_1_s1/CLK
14.647 -0.043 tSu 1 R22C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/error_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path17

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R18C30[2][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R18C30[2][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1/CLK
14.647 -0.043 tSu 1 R18C30[2][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path18

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_1_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R18C30[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R18C30[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_1_s1/CLK
14.647 -0.043 tSu 1 R18C30[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path19

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_2_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R18C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R18C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_2_s1/CLK
14.647 -0.043 tSu 1 R18C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path20

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_3_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R17C29[2][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R17C29[2][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_3_s1/CLK
14.647 -0.043 tSu 1 R17C29[2][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path21

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_4_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R17C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R17C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_4_s1/CLK
14.647 -0.043 tSu 1 R17C30[2][A] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path22

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_5_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R17C30[2][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R17C30[2][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_5_s1/CLK
14.647 -0.043 tSu 1 R17C30[2][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path23

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R17C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R17C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1/CLK
14.647 -0.043 tSu 1 R17C31[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path24

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_data_r_3_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R24C30[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_data_r_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R24C30[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_data_r_3_s0/CLK
14.647 -0.043 tSu 1 R24C30[1][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/dqs_data_r_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Path25

Path Summary:

Slack 8.426
Data Arrival Time 6.220
Data Required Time 14.647
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_r_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
2.642 2.642 tNET RR 1 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
3.100 0.458 tC2Q RF 236 R23C21[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
6.220 3.120 tNET FF 1 R23C31[0][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_r_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.048 12.048 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
14.690 2.642 tNET RR 1 R23C31[0][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_r_s0/CLK
14.647 -0.043 tSu 1 R23C31[0][B] u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/adj_done_r_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.048
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.120, 87.191%; tC2Q: 0.458, 12.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.642, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.833
Data Arrival Time 2.607
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_0_s3
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.607 0.512 tNET RR 1 R3C5[0][A] u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R3C5[0][A] u_la0_top/capture_window_sel_0_s3/CLK
1.774 0.012 tHld 1 R3C5[0][A] u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.512, 60.575%; tC2Q: 0.333, 39.425%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path2

Path Summary:

Slack 0.842
Data Arrival Time 2.616
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.616 0.521 tNET RR 1 R5C7[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C7[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
1.774 0.012 tHld 1 R5C7[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.521, 60.975%; tC2Q: 0.333, 39.025%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path3

Path Summary:

Slack 0.842
Data Arrival Time 2.616
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.616 0.521 tNET RR 1 R5C7[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C7[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
1.774 0.012 tHld 1 R5C7[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.521, 60.975%; tC2Q: 0.333, 39.025%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path4

Path Summary:

Slack 0.842
Data Arrival Time 2.616
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.616 0.521 tNET RR 1 R5C7[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C7[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
1.774 0.012 tHld 1 R5C7[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.521, 60.975%; tC2Q: 0.333, 39.025%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path5

Path Summary:

Slack 0.842
Data Arrival Time 2.616
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.616 0.521 tNET RR 1 R5C7[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C7[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
1.774 0.012 tHld 1 R5C7[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.521, 60.975%; tC2Q: 0.333, 39.025%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path6

Path Summary:

Slack 0.842
Data Arrival Time 2.616
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.616 0.521 tNET RR 1 R5C7[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C7[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
1.774 0.012 tHld 1 R5C7[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.521, 60.975%; tC2Q: 0.333, 39.025%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path7

Path Summary:

Slack 0.902
Data Arrival Time 2.676
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.676 0.582 tNET RR 1 R6C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R6C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
1.774 0.012 tHld 1 R6C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.582, 63.566%; tC2Q: 0.333, 36.434%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path8

Path Summary:

Slack 0.902
Data Arrival Time 2.676
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.676 0.582 tNET RR 1 R6C6[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R6C6[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
1.774 0.012 tHld 1 R6C6[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.582, 63.566%; tC2Q: 0.333, 36.434%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path9

Path Summary:

Slack 0.905
Data Arrival Time 2.679
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_start_dly_0_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.679 0.584 tNET RR 1 R4C7[0][A] u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R4C7[0][A] u_la0_top/internal_reg_start_dly_0_s0/CLK
1.774 0.012 tHld 1 R4C7[0][A] u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.584, 63.657%; tC2Q: 0.333, 36.343%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path10

Path Summary:

Slack 0.905
Data Arrival Time 2.679
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_start_syn_0_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.679 0.584 tNET RR 1 R4C7[0][B] u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R4C7[0][B] u_la0_top/internal_reg_start_syn_0_s0/CLK
1.774 0.012 tHld 1 R4C7[0][B] u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.584, 63.657%; tC2Q: 0.333, 36.343%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path11

Path Summary:

Slack 0.906
Data Arrival Time 2.680
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.680 0.585 tNET RR 1 R8C5[1][A] u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R8C5[1][A] u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
1.774 0.012 tHld 1 R8C5[1][A] u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.585, 63.715%; tC2Q: 0.333, 36.285%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path12

Path Summary:

Slack 0.906
Data Arrival Time 2.680
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.680 0.585 tNET RR 1 R8C5[1][B] u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R8C5[1][B] u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
1.774 0.012 tHld 1 R8C5[1][B] u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.585, 63.715%; tC2Q: 0.333, 36.285%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path13

Path Summary:

Slack 0.906
Data Arrival Time 2.680
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_0/trig_dly_0_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.680 0.585 tNET RR 1 R8C5[2][B] u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R8C5[2][B] u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK
1.774 0.012 tHld 1 R8C5[2][B] u_la0_top/u_ao_match_0/trig_dly_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.585, 63.715%; tC2Q: 0.333, 36.285%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path14

Path Summary:

Slack 0.906
Data Arrival Time 2.680
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_0/trig_dly_1_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.680 0.585 tNET RR 1 R8C5[2][A] u_la0_top/u_ao_match_0/trig_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R8C5[2][A] u_la0_top/u_ao_match_0/trig_dly_1_s0/CLK
1.774 0.012 tHld 1 R8C5[2][A] u_la0_top/u_ao_match_0/trig_dly_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.585, 63.715%; tC2Q: 0.333, 36.285%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path15

Path Summary:

Slack 0.906
Data Arrival Time 2.680
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.680 0.585 tNET RR 1 R7C5[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R7C5[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
1.774 0.012 tHld 1 R7C5[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.585, 63.715%; tC2Q: 0.333, 36.285%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path16

Path Summary:

Slack 0.906
Data Arrival Time 2.680
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.680 0.585 tNET RR 1 R7C5[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R7C5[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
1.774 0.012 tHld 1 R7C5[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.585, 63.715%; tC2Q: 0.333, 36.285%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path17

Path Summary:

Slack 0.906
Data Arrival Time 2.680
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.680 0.585 tNET RR 1 R7C5[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R7C5[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
1.774 0.012 tHld 1 R7C5[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.585, 63.715%; tC2Q: 0.333, 36.285%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path18

Path Summary:

Slack 1.103
Data Arrival Time 2.877
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_4_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.877 0.782 tNET RR 1 R3C7[0][B] u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R3C7[0][B] u_la0_top/capture_window_sel_4_s1/CLK
1.774 0.012 tHld 1 R3C7[0][B] u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.782, 70.117%; tC2Q: 0.333, 29.883%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path19

Path Summary:

Slack 1.103
Data Arrival Time 2.877
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_5_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.877 0.782 tNET RR 1 R3C7[0][A] u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R3C7[0][A] u_la0_top/capture_window_sel_5_s1/CLK
1.774 0.012 tHld 1 R3C7[0][A] u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.782, 70.117%; tC2Q: 0.333, 29.883%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path20

Path Summary:

Slack 1.103
Data Arrival Time 2.877
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/start_reg_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.877 0.782 tNET RR 1 R3C7[2][B] u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R3C7[2][B] u_la0_top/start_reg_s0/CLK
1.774 0.012 tHld 1 R3C7[2][B] u_la0_top/start_reg_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.782, 70.117%; tC2Q: 0.333, 29.883%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path21

Path Summary:

Slack 1.103
Data Arrival Time 2.877
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_start_syn_1_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.877 0.782 tNET RR 1 R3C7[2][A] u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R3C7[2][A] u_la0_top/internal_reg_start_syn_1_s0/CLK
1.774 0.012 tHld 1 R3C7[2][A] u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.782, 70.117%; tC2Q: 0.333, 29.883%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path22

Path Summary:

Slack 1.142
Data Arrival Time 2.916
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/capture_end_dly_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.916 0.822 tNET RR 1 R4C4[1][B] u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R4C4[1][B] u_la0_top/capture_end_dly_s0/CLK
1.774 0.012 tHld 1 R4C4[1][B] u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.822, 71.137%; tC2Q: 0.333, 28.863%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path23

Path Summary:

Slack 1.166
Data Arrival Time 2.940
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.940 0.845 tNET RR 1 R8C4[0][B] u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R8C4[0][B] u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
1.774 0.012 tHld 1 R8C4[0][B] u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.845, 71.719%; tC2Q: 0.333, 28.281%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path24

Path Summary:

Slack 1.166
Data Arrival Time 2.940
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_0/trig_dly_in_1_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.940 0.845 tNET RR 1 R8C4[0][A] u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R8C4[0][A] u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK
1.774 0.012 tHld 1 R8C4[0][A] u_la0_top/u_ao_match_0/trig_dly_in_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.845, 71.719%; tC2Q: 0.333, 28.281%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Path25

Path Summary:

Slack 1.167
Data Arrival Time 2.941
Data Required Time 1.774
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R5C5[2][B] u_la0_top/rst_ao_s0/CLK
2.095 0.333 tC2Q RR 57 R5C5[2][B] u_la0_top/rst_ao_s0/Q
2.941 0.846 tNET RR 1 R4C2[2][B] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1646 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
1.762 1.762 tNET RR 1 R4C2[2][B] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
1.774 0.012 tHld 1 R4C2[2][B] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.846, 71.739%; tC2Q: 0.333, 28.261%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.762, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 3.890
Actual Width: 5.140
Required Width: 1.250
Type: Low Pulse Width
Clock: clk_x1
Objects: cnt_24_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.024 0.000 active clock edge time
6.024 0.000 clk_x1
6.024 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
8.669 2.645 tNET FF cnt_24_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.048 0.000 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
13.810 1.762 tNET RR cnt_24_s0/CLK

MPW2

MPW Summary:

Slack: 3.890
Actual Width: 5.140
Required Width: 1.250
Type: Low Pulse Width
Clock: clk_x1
Objects: cnt_23_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.024 0.000 active clock edge time
6.024 0.000 clk_x1
6.024 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
8.669 2.645 tNET FF cnt_23_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.048 0.000 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
13.810 1.762 tNET RR cnt_23_s0/CLK

MPW3

MPW Summary:

Slack: 3.890
Actual Width: 5.140
Required Width: 1.250
Type: Low Pulse Width
Clock: clk_x1
Objects: cnt_22_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.024 0.000 active clock edge time
6.024 0.000 clk_x1
6.024 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
8.669 2.645 tNET FF cnt_22_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.048 0.000 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
13.810 1.762 tNET RR cnt_22_s0/CLK

MPW4

MPW Summary:

Slack: 3.890
Actual Width: 5.140
Required Width: 1.250
Type: Low Pulse Width
Clock: clk_x1
Objects: cnt_19_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.024 0.000 active clock edge time
6.024 0.000 clk_x1
6.024 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
8.669 2.645 tNET FF cnt_19_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.048 0.000 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
13.810 1.762 tNET RR cnt_19_s0/CLK

MPW5

MPW Summary:

Slack: 3.890
Actual Width: 5.140
Required Width: 1.250
Type: Low Pulse Width
Clock: clk_x1
Objects: cnt_17_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.024 0.000 active clock edge time
6.024 0.000 clk_x1
6.024 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
8.669 2.645 tNET FF cnt_17_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.048 0.000 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
13.810 1.762 tNET RR cnt_17_s0/CLK

MPW6

MPW Summary:

Slack: 3.890
Actual Width: 5.140
Required Width: 1.250
Type: Low Pulse Width
Clock: clk_x1
Objects: cnt_16_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.024 0.000 active clock edge time
6.024 0.000 clk_x1
6.024 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
8.669 2.645 tNET FF cnt_16_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.048 0.000 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
13.810 1.762 tNET RR cnt_16_s0/CLK

MPW7

MPW Summary:

Slack: 3.890
Actual Width: 5.140
Required Width: 1.250
Type: Low Pulse Width
Clock: clk_x1
Objects: u_PSRAM_TOP/u_psram_top0/rdbk_data_19_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.024 0.000 active clock edge time
6.024 0.000 clk_x1
6.024 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
8.669 2.645 tNET FF u_PSRAM_TOP/u_psram_top0/rdbk_data_19_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.048 0.000 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
13.810 1.762 tNET RR u_PSRAM_TOP/u_psram_top0/rdbk_data_19_s0/CLK

MPW8

MPW Summary:

Slack: 3.890
Actual Width: 5.140
Required Width: 1.250
Type: Low Pulse Width
Clock: clk_x1
Objects: u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_r_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.024 0.000 active clock edge time
6.024 0.000 clk_x1
6.024 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
8.669 2.645 tNET FF u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_r_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.048 0.000 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
13.810 1.762 tNET RR u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_r_4_s0/CLK

MPW9

MPW Summary:

Slack: 3.890
Actual Width: 5.140
Required Width: 1.250
Type: Low Pulse Width
Clock: clk_x1
Objects: u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/cnt_s_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.024 0.000 active clock edge time
6.024 0.000 clk_x1
6.024 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
8.669 2.645 tNET FF u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/cnt_s_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.048 0.000 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
13.810 1.762 tNET RR u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/cnt_s_10_s0/CLK

MPW10

MPW Summary:

Slack: 3.890
Actual Width: 5.140
Required Width: 1.250
Type: Low Pulse Width
Clock: clk_x1
Objects: u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/s_t_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.024 0.000 active clock edge time
6.024 0.000 clk_x1
6.024 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
8.669 2.645 tNET FF u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/s_t_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.048 0.000 active clock edge time
12.048 0.000 clk_x1
12.048 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
13.810 1.762 tNET RR u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/s_t_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
1646 clk_x1 0.019 2.645
555 n18_6_3 15.019 3.927
236 init_calib0_d 2.042 2.648
236 init_calib1_d 0.671 3.945
68 u_test0/wr_data_31_7 0.019 2.829
68 u_test1/wr_data_31_7 0.404 3.141
66 u_PSRAM_TOP/u_psram_top0/rd_data_valid_d0[0] 7.138 4.052
66 u_PSRAM_TOP/u_psram_top1/rd_data_valid_d0[0] 5.778 4.590
60 u_test0/curr_state.CYC_DONE_WAITE 5.723 3.316
60 u_test1/curr_state.CYC_DONE_WAITE 6.348 3.660

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R10C17 55.56%
R10C20 52.78%
R18C19 45.83%
R10C18 43.06%
R14C26 43.06%
R7C39 41.67%
R10C16 41.67%
R14C22 41.67%
R14C24 41.67%
R6C30 40.28%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK Actived create_clock -name clk_x1 -period 12.048 -waveform {0 6.024} [get_nets {clk_x1}]
TC_CLOCK Actived create_clock -name clk_x2 -period 6.024 -waveform {0 3.012} [get_nets {memory_clk}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {clk_x1}] -group [get_clocks {clk_x2}]