Power Messages
| Report Title | Power Analysis Report |
| Design File | E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\project\impl\gwsynthesis\psram_board_test.vg |
| Physical Constraints File | E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\project\src\psram.cst |
| Timing Constraints File | E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\project\src\psram.sdc |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW1NR-LV9LQ144PC6/I5 |
| Device | GW1NR-9 |
| Device Version | C |
| Created Time | Mon Mar 9 10:46:14 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved. |
Configure Information:
| Grade | Commercial |
| Process | Typical |
| Ambient Temperature | 25.000 |
| Use Custom Theta JA | false |
| Heat Sink | None |
| Air Flow | LFM_0 |
| Use Custom Theta SA | false |
| Board Thermal Model | None |
| Use Custom Theta JB | false |
| Related Vcd File | |
| Related Saif File | |
| Filter Glitches | false |
| Default IO Toggle Rate | 0.125 |
| Default Remain Toggle Rate | 0.125 |
Power Summary
Power Information:
| Total Power (mW) | 58.771 |
| Quiescent Power (mW) | 24.881 |
| Dynamic Power (mW) | 33.889 |
| Psram Power (mW) | 86.000 |
Thermal Information:
| Junction Temperature | 26.659 |
| Theta JA | 29.000 |
| Max Allowed Ambient Temperature | 83.341 |
Supply Information:
| Voltage Source | Voltage | Dynamic Current(mA) | Quiescent Current(mA) | Power(mW) |
|---|---|---|---|---|
| VCC | 1.200 | 25.645 | 3.499 | 34.973 |
| VCCX | 3.300 | 0.576 | 5.000 | 18.400 |
| VCCIO18 | 1.800 | 0.460 | 1.596 | 3.701 |
| VCCIO33 | 3.300 | 0.118 | 0.397 | 1.697 |
Power Details
Power By Block Type:
| Block Type | Total Power(mW) | Static Power(mW) | Average Toggle Rate(millions of transitions/sec) |
|---|---|---|---|
| Logic | 0.882 | NA | 10.205 |
| IO | 9.176 | 5.305 | 19.613 |
| BSRAM | 14.303 | NA | NA |
| PLL | 4.620 | NA | NA |
| DLL | 10.199 | NA | NA |
Power By Hierarchy:
| Hierarchy Entity | Total Power(mW) | Block Dynamic Power(mW) |
|---|---|---|
| psram_syn_top | 30.004 | 30.004(29.991) |
| psram_syn_top/bt/ | 0.022 | 0.022(0.000) |
| psram_syn_top/u_PSRAM_TOP/ | 25.077 | 25.077(14.877) |
| psram_syn_top/u_PSRAM_TOP/u_psram_sync/ | 0.012 | 0.012(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top0/ | 7.434 | 7.434(7.392) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/ | 3.528 | 3.528(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_Temp_Auto_Adj/ | 0.078 | 0.078(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_init/ | 0.077 | 0.077(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/ | 3.709 | 3.709(3.686) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/ | 3.686 | 3.686(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top1/ | 7.431 | 7.431(7.388) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top1/matched_rvld[0].u_matched_rvld_fifo/ | 3.528 | 3.528(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/ | 0.074 | 0.074(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_init/ | 0.077 | 0.077(0.000) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/ | 3.709 | 3.709(3.686) |
| psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/ | 3.686 | 3.686(0.000) |
| psram_syn_top/u_test0/ | 0.136 | 0.136(0.000) |
| psram_syn_top/u_test1/ | 0.136 | 0.136(0.000) |
| psram_syn_top/your_instance_name/ | 4.620 | 4.620(0.000) |
Power By Clock Domain:
| Clock Domain | Clock Frequency(Mhz) | Total Dynamic Power(mW) |
|---|---|---|
| clk_x1 | 83.001 | 15.151 |
| clk | 50.000 | 4.657 |
| clk_x2 | 166.003 | 10.210 |
| NO CLOCK DOMAIN | 0.000 | 0.000 |