Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\project\src\gowin_rpll\gowin_rpll.v E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\project\src\key_debounce.v E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\project\src\psram_memory_interface_hs\psram_memory_interface_hs.v E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\project\src\psram_syn_top.v E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\project\src\psram_test.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW1NR-LV9LQ144PC6/I5 |
| Device | GW1NR-9 |
| Device Version | C |
| Created Time | Wed Mar 4 09:42:12 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | psram_syn_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.483s, Peak memory usage = 421.957MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.119s, Peak memory usage = 421.957MB Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.149s, Peak memory usage = 421.957MB Optimizing Phase 2: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.18s, Peak memory usage = 421.957MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.108s, Peak memory usage = 421.957MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 421.957MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 421.957MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 421.957MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 421.957MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 421.957MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 421.957MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 421.957MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.359s, Peak memory usage = 421.957MB Generate output files: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.257s, Peak memory usage = 421.957MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 421.957MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 32 |
| I/O Buf | 31 |
| IBUF | 2 |
| OBUF | 10 |
| IOBUF | 18 |
| ELVDS_OBUF | 1 |
| Register | 1574 |
| DFF | 4 |
| DFFE | 1 |
| DFFSE | 12 |
| DFFR | 20 |
| DFFRE | 2 |
| DFFP | 12 |
| DFFPE | 6 |
| DFFC | 897 |
| DFFCE | 620 |
| LUT | 2333 |
| LUT2 | 457 |
| LUT3 | 667 |
| LUT4 | 1209 |
| ALU | 182 |
| ALU | 182 |
| INV | 18 |
| INV | 18 |
| IOLOGIC | 62 |
| IDES4 | 18 |
| OSER4 | 23 |
| IODELAY | 21 |
| BSRAM | 4 |
| SDPB | 2 |
| SDPX9B | 2 |
| CLOCK | 3 |
| CLKDIV | 1 |
| DHCEN | 1 |
| rPLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2533(2351 LUT, 182 ALU) / 8640 | 30% |
| Register | 1574 / 6843 | 24% |
| --Register as Latch | 0 / 6843 | 0% |
| --Register as FF | 1574 / 6843 | 24% |
| BSRAM | 4 / 26 | 16% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | Generated | 6.038 | 165.625 | 0.000 | 3.019 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUT |
| 3 | your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.038 | 165.625 | 0.000 | 3.019 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTP |
| 4 | your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | Generated | 12.075 | 82.812 | 0.000 | 6.038 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD |
| 5 | your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 18.113 | 55.208 | 0.000 | 9.057 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD3 |
| 6 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | Generated | 12.075 | 82.812 | 0.000 | 6.038 | your_instance_name/rpll_inst/CLKOUT | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | u_PSRAM_TOP/clkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 90.087(MHz) | 6 | TOP |
| 2 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | 82.812(MHz) | 66.408(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -3.290 |
| Data Arrival Time | 16.388 |
| Data Required Time | 13.098 |
| From | u_PSRAM_TOP/u_dll |
| To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/step_0_s1 |
| Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.038 | 6.038 | active clock edge time | |||
| 6.038 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
| 6.764 | 0.726 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
| 7.490 | 0.726 | tNET | RR | 3 | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
| 7.738 | 0.248 | tINS | RR | 43 | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
| 8.464 | 0.726 | tNET | RR | 8 | u_PSRAM_TOP/u_dll/CLKIN |
| 9.030 | 0.566 | tINS | RF | 2 | u_PSRAM_TOP/u_dll/STEP[0] |
| 9.990 | 0.960 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s19/I1 |
| 11.035 | 1.045 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s19/COUT |
| 11.035 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s20/CIN |
| 11.092 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s20/COUT |
| 11.092 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s21/CIN |
| 11.149 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s21/COUT |
| 11.149 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s22/CIN |
| 11.206 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s22/COUT |
| 11.206 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s23/CIN |
| 11.263 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s23/COUT |
| 11.263 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s24/CIN |
| 11.320 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s24/COUT |
| 11.320 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s25/CIN |
| 11.377 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n209_s25/COUT |
| 12.337 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n275_s2/I1 |
| 13.436 | 1.099 | tINS | FF | 9 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n275_s2/F |
| 14.396 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n219_s3/I0 |
| 15.428 | 1.032 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n219_s3/F |
| 16.388 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/step_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.075 | 12.075 | active clock edge time | |||
| 12.075 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
| 12.802 | 0.727 | tCL | RR | 1569 | u_PSRAM_TOP/clkdiv/CLKOUT |
| 13.528 | 0.726 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/step_0_s1/CLK |
| 13.498 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/step_0_s1 | ||
| 13.098 | -0.400 | tSu | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/step_0_s1 |
| Clock Skew: | -0.247 |
| Setup Relationship: | 6.038 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.248, 25.476%; route: 0.726, 74.524% |
| Arrival Data Path Delay: | cell: 4.084, 47.215%; route: 3.840, 44.392%; tC2Q: 0.726, 8.393% |
| Required Clock Path Delay: | cell: 0.248, 25.476%; route: 0.726, 74.524% |
Path 2
Path Summary:| Slack | -3.013 |
| Data Arrival Time | 16.111 |
| Data Required Time | 13.098 |
| From | u_PSRAM_TOP/u_dll |
| To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_0_s1 |
| Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.038 | 6.038 | active clock edge time | |||
| 6.038 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
| 6.764 | 0.726 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
| 7.490 | 0.726 | tNET | RR | 3 | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
| 7.738 | 0.248 | tINS | RR | 43 | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
| 8.464 | 0.726 | tNET | RR | 8 | u_PSRAM_TOP/u_dll/CLKIN |
| 9.030 | 0.566 | tINS | RF | 2 | u_PSRAM_TOP/u_dll/STEP[0] |
| 9.990 | 0.960 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s19/I1 |
| 11.035 | 1.045 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s19/COUT |
| 11.035 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s20/CIN |
| 11.092 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s20/COUT |
| 11.092 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s21/CIN |
| 11.149 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s21/COUT |
| 11.149 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s22/CIN |
| 11.206 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s22/COUT |
| 11.206 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s23/CIN |
| 11.263 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s23/COUT |
| 11.263 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s24/CIN |
| 11.320 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s24/COUT |
| 11.320 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s25/CIN |
| 11.377 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n209_s25/COUT |
| 12.337 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n273_s2/I2 |
| 13.159 | 0.822 | tINS | FF | 9 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n273_s2/F |
| 14.119 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n219_s3/I0 |
| 15.151 | 1.032 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n219_s3/F |
| 16.111 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.075 | 12.075 | active clock edge time | |||
| 12.075 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
| 12.802 | 0.727 | tCL | RR | 1569 | u_PSRAM_TOP/clkdiv/CLKOUT |
| 13.528 | 0.726 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_0_s1/CLK |
| 13.498 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_0_s1 | ||
| 13.098 | -0.400 | tSu | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_0_s1 |
| Clock Skew: | -0.247 |
| Setup Relationship: | 6.038 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.248, 25.476%; route: 0.726, 74.524% |
| Arrival Data Path Delay: | cell: 3.807, 45.469%; route: 3.840, 45.861%; tC2Q: 0.726, 8.670% |
| Required Clock Path Delay: | cell: 0.248, 25.476%; route: 0.726, 74.524% |
Path 3
Path Summary:| Slack | -2.983 |
| Data Arrival Time | 16.111 |
| Data Required Time | 13.128 |
| From | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1 |
| To | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1 |
| Launch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 1569 | u_PSRAM_TOP/clkdiv/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1/CLK |
| 1.911 | 0.458 | tC2Q | RF | 9 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1/Q |
| 2.871 | 0.960 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s14/I1 |
| 3.916 | 1.045 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s14/COUT |
| 3.916 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s15/CIN |
| 3.973 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s15/COUT |
| 3.973 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s16/CIN |
| 4.030 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s16/COUT |
| 4.030 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s17/CIN |
| 4.087 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s17/COUT |
| 5.047 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s21/I0 |
| 6.079 | 1.032 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s21/F |
| 7.039 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s19/I1 |
| 8.138 | 1.099 | tINS | FF | 5 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s19/F |
| 9.098 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n730_s7/I3 |
| 9.724 | 0.626 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n730_s7/F |
| 10.684 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n730_s4/I1 |
| 11.783 | 1.099 | tINS | FF | 7 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n730_s4/F |
| 12.743 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n729_s9/I2 |
| 13.565 | 0.822 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n729_s9/F |
| 14.525 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n729_s5/I3 |
| 15.151 | 0.626 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n729_s5/F |
| 16.111 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.075 | 12.075 | active clock edge time | |||
| 12.075 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
| 12.802 | 0.727 | tCL | RR | 1569 | u_PSRAM_TOP/clkdiv/CLKOUT |
| 13.528 | 0.726 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1/CLK |
| 13.128 | -0.400 | tSu | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_6_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 12.075 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 6.520, 44.480%; route: 7.680, 52.393%; tC2Q: 0.458, 3.127% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:| Slack | -2.080 |
| Data Arrival Time | 15.208 |
| Data Required Time | 13.128 |
| From | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1 |
| To | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_1_s1 |
| Launch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 1569 | u_PSRAM_TOP/clkdiv/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1/CLK |
| 1.911 | 0.458 | tC2Q | RF | 9 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1/Q |
| 2.871 | 0.960 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s14/I1 |
| 3.916 | 1.045 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s14/COUT |
| 3.916 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s15/CIN |
| 3.973 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s15/COUT |
| 3.973 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s16/CIN |
| 4.030 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s16/COUT |
| 4.030 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s17/CIN |
| 4.087 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s17/COUT |
| 5.047 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s21/I0 |
| 6.079 | 1.032 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s21/F |
| 7.039 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s19/I1 |
| 8.138 | 1.099 | tINS | FF | 5 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s19/F |
| 9.098 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n729_s10/I1 |
| 10.197 | 1.099 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n729_s10/F |
| 11.157 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n730_s5/I0 |
| 12.189 | 1.032 | tINS | FF | 6 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n730_s5/F |
| 13.149 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n734_s3/I1 |
| 14.248 | 1.099 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n734_s3/F |
| 15.208 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.075 | 12.075 | active clock edge time | |||
| 12.075 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
| 12.802 | 0.727 | tCL | RR | 1569 | u_PSRAM_TOP/clkdiv/CLKOUT |
| 13.528 | 0.726 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_1_s1/CLK |
| 13.128 | -0.400 | tSu | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 12.075 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 6.577, 47.814%; route: 6.720, 48.854%; tC2Q: 0.458, 3.332% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:| Slack | -2.080 |
| Data Arrival Time | 15.208 |
| Data Required Time | 13.128 |
| From | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1 |
| To | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_2_s1 |
| Launch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 1569 | u_PSRAM_TOP/clkdiv/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1/CLK |
| 1.911 | 0.458 | tC2Q | RF | 9 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_0_s1/Q |
| 2.871 | 0.960 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s14/I1 |
| 3.916 | 1.045 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s14/COUT |
| 3.916 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s15/CIN |
| 3.973 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s15/COUT |
| 3.973 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s16/CIN |
| 4.030 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s16/COUT |
| 4.030 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s17/CIN |
| 4.087 | 0.057 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n500_s17/COUT |
| 5.047 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s21/I0 |
| 6.079 | 1.032 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s21/F |
| 7.039 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s19/I1 |
| 8.138 | 1.099 | tINS | FF | 5 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n750_s19/F |
| 9.098 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n729_s10/I1 |
| 10.197 | 1.099 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n729_s10/F |
| 11.157 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n730_s5/I0 |
| 12.189 | 1.032 | tINS | FF | 6 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n730_s5/F |
| 13.149 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n733_s3/I1 |
| 14.248 | 1.099 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/n733_s3/F |
| 15.208 | 0.960 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.075 | 12.075 | active clock edge time | |||
| 12.075 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
| 12.802 | 0.727 | tCL | RR | 1569 | u_PSRAM_TOP/clkdiv/CLKOUT |
| 13.528 | 0.726 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_2_s1/CLK |
| 13.128 | -0.400 | tSu | 1 | u_PSRAM_TOP/u_psram_top1/u_Temp_Auto_Adj/[0].cnt_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 12.075 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 6.577, 47.814%; route: 6.720, 48.854%; tC2Q: 0.458, 3.332% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |