Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\gw_jtag.v
E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign(3)\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\project\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.01 (64-bit)
Part Number GW1NR-LV9LQ144PC6/I5
Device GW1NR-9
Device Version C
Created Time Tue Jan 6 10:26:57 2026
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.241s, Peak memory usage = 65.801MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 65.801MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 65.801MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 65.801MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 65.801MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 65.801MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 65.801MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 65.801MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 65.801MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 65.801MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 65.801MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 65.801MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 96.434MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 96.434MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 96.434MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 96.434MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 11
I/O Buf 11
    IBUF 10
    OBUF 1
Register 284
    DFF 19
    DFFR 1
    DFFP 3
    DFFPE 33
    DFFC 29
    DFFCE 199
LUT 389
    LUT2 63
    LUT3 70
    LUT4 256
MUX 1
    MUX16 1
ALU 13
    ALU 13
INV 4
    INV 4
BSRAM 1
    SDPB 1
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 414(401 LUT, 13 ALU) / 8640 5%
Register 284 / 6843 5%
  --Register as Latch 0 / 6843 0%
  --Register as FF 284 / 6843 5%
BSRAM 1 / 26 4%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk_x1 Base 20.000 50.000 0.000 10.000 clk_x1_ibuf/I
2 u_icon_top/n19_6 Base 20.000 50.000 0.000 10.000 u_icon_top/n19_s2/F

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_x1 50.000(MHz) 102.983(MHz) 5 TOP
2 u_icon_top/n19_6 50.000(MHz) 549.954(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 10.290
Data Arrival Time 10.036
Data Required Time 20.326
From u_la0_top/capture_window_sel_0_s3
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 77 clk_x1_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/capture_window_sel_0_s3/CLK
1.184 0.458 tC2Q RF 14 u_la0_top/capture_window_sel_0_s3/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s15/I1
3.243 1.099 tINS FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s15/F
4.203 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s13/I1
5.302 1.099 tINS FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s13/F
6.262 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s11/I0
7.294 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s11/F
8.254 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/I2
9.076 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/F
10.036 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 77 clk_x1_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.052, 43.522%; route: 4.800, 51.555%; tC2Q: 0.458, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:
Slack 10.290
Data Arrival Time 10.036
Data Required Time 20.326
From u_la0_top/capture_window_sel_0_s3
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 77 clk_x1_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/capture_window_sel_0_s3/CLK
1.184 0.458 tC2Q RF 14 u_la0_top/capture_window_sel_0_s3/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/I1
3.243 1.099 tINS FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/F
4.203 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I0
5.235 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F
6.195 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s13/I1
7.294 1.099 tINS FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s13/F
8.254 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I2
9.076 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F
10.036 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 77 clk_x1_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.052, 43.522%; route: 4.800, 51.555%; tC2Q: 0.458, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:
Slack 10.419
Data Arrival Time 9.907
Data Required Time 20.326
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 77 clk_x1_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.184 0.458 tC2Q RF 6 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n240_s2/I1
3.243 1.099 tINS FF 4 u_la0_top/u_ao_mem_ctrl/n240_s2/F
4.203 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n239_s2/I1
5.302 1.099 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n239_s2/F
6.262 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n236_s2/I3
6.888 0.626 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n236_s2/F
7.848 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n236_s1/I1
8.947 1.099 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n236_s1/F
9.907 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 77 clk_x1_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 3.923, 42.728%; route: 4.800, 52.280%; tC2Q: 0.458, 4.992%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:
Slack 10.424
Data Arrival Time 9.902
Data Required Time 20.326
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 77 clk_x1_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.184 0.458 tC2Q RF 5 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n235_s8/I0
3.176 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n235_s8/F
4.136 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n235_s6/I0
5.168 1.032 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n235_s6/F
6.128 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n235_s4/I0
7.160 1.032 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n235_s4/F
8.120 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n243_s1/I2
8.942 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n243_s1/F
9.902 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 77 clk_x1_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 3.918, 42.697%; route: 4.800, 52.308%; tC2Q: 0.458, 4.995%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:
Slack 10.500
Data Arrival Time 9.826
Data Required Time 20.326
From u_la0_top/capture_window_sel_2_s1
To u_la0_top/capture_window_sel_8_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 77 clk_x1_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/capture_window_sel_2_s1/CLK
1.184 0.458 tC2Q RF 10 u_la0_top/capture_window_sel_2_s1/Q
2.144 0.960 tNET FF 1 u_la0_top/n1254_s2/I1
3.243 1.099 tINS FF 3 u_la0_top/n1254_s2/F
4.203 0.960 tNET FF 1 u_la0_top/n1252_s2/I2
5.025 0.822 tINS FF 3 u_la0_top/n1252_s2/F
5.985 0.960 tNET FF 1 u_la0_top/n1250_s2/I2
6.807 0.822 tINS FF 2 u_la0_top/n1250_s2/F
7.767 0.960 tNET FF 1 u_la0_top/n1250_s1/I1
8.866 1.099 tINS FF 1 u_la0_top/n1250_s1/F
9.826 0.960 tNET FF 1 u_la0_top/capture_window_sel_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 77 clk_x1_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/capture_window_sel_8_s1/CLK
20.326 -0.400 tSu 1 u_la0_top/capture_window_sel_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 3.842, 42.218%; route: 4.800, 52.746%; tC2Q: 0.458, 5.036%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%