Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\PSRAM_HS\psram_hs_1ch\PSRAM_TOP.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\PSRAM_HS\psram_hs_1ch\psram_code.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW1NR-LV9LQ144PC6/I5 |
| Device | GW1NR-9 |
| Device Version | C |
| Created Time | Wed Mar 4 09:31:24 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | PSRAM_Memory_Interface_HS_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.305s, Peak memory usage = 78.172MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 78.172MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.245s, Peak memory usage = 78.172MB Optimizing Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.126s, Peak memory usage = 78.172MB Optimizing Phase 2: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.23s, Peak memory usage = 78.172MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 78.172MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 78.172MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 78.172MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 78.172MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.22s, Peak memory usage = 78.172MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 78.172MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 78.172MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 107.102MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.412s, Peak memory usage = 107.102MB Generate output files: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.119s, Peak memory usage = 107.102MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 107.102MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 167 |
| Embedded Port | 26 |
| I/O Buf | 192 |
| IBUF | 99 |
| OBUF | 74 |
| IOBUF | 18 |
| ELVDS_OBUF | 1 |
| Register | 701 |
| DFF | 1 |
| DFFSE | 12 |
| DFFRE | 2 |
| DFFP | 4 |
| DFFPE | 6 |
| DFFC | 426 |
| DFFCE | 250 |
| LUT | 1187 |
| LUT2 | 276 |
| LUT3 | 380 |
| LUT4 | 531 |
| ALU | 86 |
| ALU | 86 |
| INV | 7 |
| INV | 7 |
| IOLOGIC | 62 |
| IDES4 | 18 |
| OSER4 | 23 |
| IODELAY | 21 |
| BSRAM | 4 |
| SDPB | 2 |
| SDPX9B | 2 |
| CLOCK | 2 |
| CLKDIV | 1 |
| DHCEN | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1280(1194 LUT, 86 ALU) / 8640 | 15% |
| Register | 701 / 6921 | 11% |
| --Register as Latch | 0 / 6921 | 0% |
| --Register as FF | 701 / 6921 | 11% |
| BSRAM | 4 / 26 | 16% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | memory_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | memory_clk_ibuf/I | ||
| 2 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
| 3 | u_psram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | u_psram_top/clkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 104.370(MHz) | 5 | TOP |
| 2 | u_psram_top/clkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 72.055(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 8.532 |
| Data Arrival Time | 2.144 |
| Data Required Time | 10.676 |
| From | u_psram_top/u_psram_sync/cs_memsync_4_s0 |
| To | u_psram_top/u_dqce_clk_x2 |
| Launch Clk | clk[R] |
| Latch Clk | memory_clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_sync/cs_memsync_4_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 8 | u_psram_top/u_psram_sync/cs_memsync_4_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | u_psram_top/u_dqce_clk_x2/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | memory_clk | |||
| 10.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 10.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
| 10.960 | 0.960 | tNET | FF | 3 | u_psram_top/u_dqce_clk_x2/CLKIN |
| 10.930 | -0.030 | tUnc | u_psram_top/u_dqce_clk_x2 | ||
| 10.676 | -0.254 | tSu | 1 | u_psram_top/u_dqce_clk_x2 |
| Clock Skew: | 0.234 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.960, 67.685%; tC2Q: 0.458, 32.315% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:| Slack | 10.419 |
| Data Arrival Time | 9.907 |
| Data Required Time | 20.326 |
| From | u_psram_top/u_psram_sync/lock_cnt_1_s3 |
| To | u_psram_top/u_psram_sync/lock_cnt_9_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK |
| 1.184 | 0.458 | tC2Q | RF | 5 | u_psram_top/u_psram_sync/lock_cnt_1_s3/Q |
| 2.144 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n47_s2/I1 |
| 3.243 | 1.099 | tINS | FF | 4 | u_psram_top/u_psram_sync/n47_s2/F |
| 4.203 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n44_s2/I3 |
| 4.829 | 0.626 | tINS | FF | 4 | u_psram_top/u_psram_sync/n44_s2/F |
| 5.789 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n43_s2/I1 |
| 6.888 | 1.099 | tINS | FF | 5 | u_psram_top/u_psram_sync/n43_s2/F |
| 7.848 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n42_s1/I1 |
| 8.947 | 1.099 | tINS | FF | 1 | u_psram_top/u_psram_sync/n42_s1/F |
| 9.907 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/lock_cnt_9_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | |||
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_9_s1/CLK |
| 20.326 | -0.400 | tSu | 1 | u_psram_top/u_psram_sync/lock_cnt_9_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 3.923, 42.728%; route: 4.800, 52.280%; tC2Q: 0.458, 4.992% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:| Slack | 10.486 |
| Data Arrival Time | 9.840 |
| Data Required Time | 20.326 |
| From | u_psram_top/u_psram_sync/lock_cnt_1_s3 |
| To | u_psram_top/u_psram_sync/lock_cnt_10_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK |
| 1.184 | 0.458 | tC2Q | RF | 5 | u_psram_top/u_psram_sync/lock_cnt_1_s3/Q |
| 2.144 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n47_s2/I1 |
| 3.243 | 1.099 | tINS | FF | 4 | u_psram_top/u_psram_sync/n47_s2/F |
| 4.203 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n44_s2/I3 |
| 4.829 | 0.626 | tINS | FF | 4 | u_psram_top/u_psram_sync/n44_s2/F |
| 5.789 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n43_s2/I1 |
| 6.888 | 1.099 | tINS | FF | 5 | u_psram_top/u_psram_sync/n43_s2/F |
| 7.848 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n41_s1/I0 |
| 8.880 | 1.032 | tINS | FF | 1 | u_psram_top/u_psram_sync/n41_s1/F |
| 9.840 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/lock_cnt_10_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | |||
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_10_s1/CLK |
| 20.326 | -0.400 | tSu | 1 | u_psram_top/u_psram_sync/lock_cnt_10_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 3.856, 42.307%; route: 4.800, 52.664%; tC2Q: 0.458, 5.029% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:| Slack | 10.486 |
| Data Arrival Time | 9.840 |
| Data Required Time | 20.326 |
| From | u_psram_top/u_psram_sync/lock_cnt_1_s3 |
| To | u_psram_top/u_psram_sync/lock_cnt_11_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK |
| 1.184 | 0.458 | tC2Q | RF | 5 | u_psram_top/u_psram_sync/lock_cnt_1_s3/Q |
| 2.144 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n47_s2/I1 |
| 3.243 | 1.099 | tINS | FF | 4 | u_psram_top/u_psram_sync/n47_s2/F |
| 4.203 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n44_s2/I3 |
| 4.829 | 0.626 | tINS | FF | 4 | u_psram_top/u_psram_sync/n44_s2/F |
| 5.789 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n43_s2/I1 |
| 6.888 | 1.099 | tINS | FF | 5 | u_psram_top/u_psram_sync/n43_s2/F |
| 7.848 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n40_s1/I0 |
| 8.880 | 1.032 | tINS | FF | 1 | u_psram_top/u_psram_sync/n40_s1/F |
| 9.840 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/lock_cnt_11_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | |||
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_11_s1/CLK |
| 20.326 | -0.400 | tSu | 1 | u_psram_top/u_psram_sync/lock_cnt_11_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 3.856, 42.307%; route: 4.800, 52.664%; tC2Q: 0.458, 5.029% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:| Slack | 10.486 |
| Data Arrival Time | 9.840 |
| Data Required Time | 20.326 |
| From | u_psram_top/u_psram_sync/lock_cnt_1_s3 |
| To | u_psram_top/u_psram_sync/lock_cnt_12_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK |
| 1.184 | 0.458 | tC2Q | RF | 5 | u_psram_top/u_psram_sync/lock_cnt_1_s3/Q |
| 2.144 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n47_s2/I1 |
| 3.243 | 1.099 | tINS | FF | 4 | u_psram_top/u_psram_sync/n47_s2/F |
| 4.203 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n44_s2/I3 |
| 4.829 | 0.626 | tINS | FF | 4 | u_psram_top/u_psram_sync/n44_s2/F |
| 5.789 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n43_s2/I1 |
| 6.888 | 1.099 | tINS | FF | 5 | u_psram_top/u_psram_sync/n43_s2/F |
| 7.848 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/n39_s1/I0 |
| 8.880 | 1.032 | tINS | FF | 1 | u_psram_top/u_psram_sync/n39_s1/F |
| 9.840 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_sync/lock_cnt_12_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | |||
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_12_s1/CLK |
| 20.326 | -0.400 | tSu | 1 | u_psram_top/u_psram_sync/lock_cnt_12_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 3.856, 42.307%; route: 4.800, 52.664%; tC2Q: 0.458, 5.029% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |