Timing Messages

Report Title	Timing Analysis Report
Design File	E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_refDesign\project\impl\gwsynthesis\psram_board_test.vg
Physical Constraints File	E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_refDesign\project\src\psram.cst
Timing Constraint File	E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_refDesign\project\src\psram.sdc
Tool Version	V1.9.12.02 (64-bit)
Part Number	GW1NR-LV9LQ144PC6/I5
Device	GW1NR-9
Device Version	C
Created Time	Mon Mar 9 10:44:55 2026
Legal Announcement	Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	3711
Numbers of Endpoints Analyzed	3808
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk	Base	20.000	50.000	0.000	10.000			clk
2	clk_x1	Base	12.048	83.001	0.000	6.024			clk_x1
3	clk_x2	Base	6.024	166.003	0.000	3.012			memory_clk
4	tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_ibuf/I
5	your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Generated	6.038	165.625	0.000	3.019	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUTP
6	your_instance_name/rpll_inst/CLKOUTD.default_gen_clk	Generated	12.075	82.812	0.000	6.038	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUTD
7	your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Generated	18.113	55.208	0.000	9.057	clk_ibuf/I	clk	your_instance_name/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	129.938(MHz)	5	TOP
2	clk_x1	83.001(MHz)	87.750(MHz)	8	TOP
3	tck_pad_i	20.000(MHz)	69.450(MHz)	6	TOP

No timing paths to get frequency of clk_x2!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
clk_x1	Setup	0.000	0
clk_x1	Hold	0.000	0
clk_x2	Setup	0.000	0
clk_x2	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.652	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/Q	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_4_s1/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.996
2	0.652	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/Q	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_5_s1/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.996
3	1.033	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/Q	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_0_s1/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.615
4	1.033	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/Q	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_3_s1/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.615
5	1.132	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/Q	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_1_s1/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.516
6	1.132	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/Q	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_2_s1/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.516
7	1.240	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q	u_test/addr_add_w_7_s1/CE	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.764
8	1.240	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q	u_test/addr_add_w_8_s1/CE	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.764
9	1.240	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q	u_test/addr_add_w_9_s1/CE	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.764
10	1.282	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_0_s1/Q	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_5_s1/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.366
11	1.282	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_0_s1/Q	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_6_s1/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.366
12	1.289	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q	u_test/addr_add_w_12_s1/CE	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.716
13	1.289	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q	u_test/addr_add_w_13_s1/CE	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.716
14	1.289	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q	u_test/addr_add_w_14_s1/CE	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.716
15	1.298	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.706
16	1.320	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q	u_test/addr_15_s0/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.328
17	1.320	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q	u_test/addr_16_s0/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.328
18	1.322	u_test/rd_data_d_43_s0/Q	u_test/error_d1_s0/CE	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.683
19	1.365	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q	u_test/addr_add_w_8_s1/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.283
20	1.365	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q	u_test/addr_add_w_9_s1/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.283
21	1.443	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_0_s1/Q	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_1_s1/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.205
22	1.469	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q	u_test/addr_add_w_7_s1/D	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.179
23	1.486	u_psram_top/u_psram_top_0/u_psram_init/timer_cnt_5_s5/Q	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkneg.u_ck_gen/D2	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.517
24	1.486	u_psram_top/u_psram_top_0/u_psram_init/timer_cnt_5_s5/Q	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkneg.u_ck_gen/D0	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.517
25	1.486	u_psram_top/u_psram_top_0/u_psram_init/timer_cnt_5_s5/Q	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/D2	clk_x1:[R]	clk_x1:[R]	12.048	0.000	10.517

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.418	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_1_s5/Q	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s/ADB[6]	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.578
2	0.479	u_psram_top/u_psram_top_0/rd_data_d_36_s0/Q	u_psram_top/u_psram_top_0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[4]	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.565
3	0.479	u_psram_top/u_psram_top_0/rd_data_d_6_s0/Q	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[6]	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.565
4	0.479	u_psram_top/u_psram_top_0/rd_data_d_4_s0/Q	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[4]	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.565
5	0.479	u_psram_top/u_psram_top_0/rd_data_d_2_s0/Q	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[2]	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.565
6	0.570	u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/Q	u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.570
7	0.570	u_la0_top/internal_reg_start_syn_0_s0/Q	u_la0_top/internal_reg_start_syn_1_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.570
8	0.570	u_la0_top/internal_reg_force_triger_syn_0_s0/Q	u_la0_top/internal_reg_force_triger_syn_1_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.570
9	0.570	u_la0_top/rst_ao_syn_s0/Q	u_la0_top/rst_ao_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.570
10	0.571	u_la0_top/data_register_30_s0/Q	u_la0_top/internal_register_select_14_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.571
11	0.571	u_la0_top/data_register_18_s0/Q	u_la0_top/data_register_17_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.571
12	0.571	u_la0_top/data_register_29_s0/Q	u_la0_top/data_register_28_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.571
13	0.571	u_la0_top/data_register_36_s0/Q	u_la0_top/data_register_35_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.571
14	0.571	u_icon_top/input_shift_reg_3_s0/Q	u_icon_top/input_shift_reg_2_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.571
15	0.571	u_icon_top/enable_reg_1_s0/Q	u_icon_top/enable_reg_0_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.571
16	0.572	u_la0_top/data_register_28_s0/Q	u_la0_top/internal_register_select_12_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.572
17	0.572	u_la0_top/data_register_5_s0/Q	u_la0_top/data_register_4_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.572
18	0.572	u_la0_top/data_register_11_s0/Q	u_la0_top/data_register_10_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.572
19	0.572	u_la0_top/data_register_13_s0/Q	u_la0_top/data_register_12_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.572
20	0.572	u_la0_top/data_register_14_s0/Q	u_la0_top/data_register_13_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.572
21	0.572	u_la0_top/data_register_15_s0/Q	u_la0_top/data_register_14_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.572
22	0.572	u_la0_top/data_register_20_s0/Q	u_la0_top/data_register_19_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.572
23	0.572	u_la0_top/data_register_27_s0/Q	u_la0_top/data_register_26_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.572
24	0.572	u_la0_top/data_register_34_s0/Q	u_la0_top/data_register_33_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.572
25	0.573	u_la0_top/data_register_6_s0/Q	u_la0_top/data_register_5_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.573

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	8.241	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.764
2	8.241	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.764
3	8.241	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.764
4	8.241	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.764
5	8.241	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.764
6	8.241	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.764
7	8.246	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.759
8	8.246	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.759
9	8.246	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.759
10	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/check_data_0_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
11	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/check_data_1_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
12	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/check_data_3_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
13	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/check_data_4_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
14	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/check_data_6_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
15	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/check_data_10_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
16	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/check_data_13_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
17	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/check_data_15_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
18	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/check_data_18_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
19	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/check_data_20_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
20	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/check_data_23_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
21	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/check_data_30_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
22	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/wr_data_add_0_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
23	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/RD_DONE_s7/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
24	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/RD_CYC_CNT_0_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429
25	8.576	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q	u_test/WR_CYC_CNT_0_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	12.048	0.000	3.429

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.833	u_la0_top/rst_ao_s0/Q	u_la0_top/trigger_seq_start_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.846
2	0.833	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.846
3	0.833	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.846
4	0.878	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_0_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.891
5	0.878	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_0_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.891
6	0.878	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_1_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.891
7	0.897	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.910
8	0.897	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.910
9	0.897	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.910
10	0.911	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.924
11	0.911	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.924
12	0.911	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.924
13	0.919	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.931
14	0.919	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.931
15	0.919	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.931
16	0.919	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.931
17	1.132	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	1.145
18	1.171	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_2_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	1.184
19	1.171	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_3_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	1.184
20	1.171	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_7_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	1.184
21	1.171	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_8_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	1.184
22	1.171	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_2_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	1.184
23	1.171	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_3_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	1.184
24	1.179	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	1.191
25	1.418	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_end_dly_s0/PRESET	clk_x1:[R]	clk_x1:[R]	0.000	0.000	1.431

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.890	5.140	1.250	Low Pulse Width	clk_x1	u_psram_top/u_psram_top_0/rd_data_valid_d_1_s0
2	3.890	5.140	1.250	Low Pulse Width	clk_x1	u_psram_top/u_psram_top_0/rd_data_valid_d_0_s0
3	3.890	5.140	1.250	Low Pulse Width	clk_x1	u_psram_top/u_psram_top_0/rd_data_d_31_s0
4	3.890	5.140	1.250	Low Pulse Width	clk_x1	u_psram_top/u_psram_top_0/rd_data_d_28_s0
5	3.890	5.140	1.250	Low Pulse Width	clk_x1	u_psram_top/u_psram_top_0/rd_data_d_26_s0
6	3.890	5.140	1.250	Low Pulse Width	clk_x1	u_psram_top/u_psram_top_0/rd_data_d_25_s0
7	3.890	5.140	1.250	Low Pulse Width	clk_x1	u_psram_top/u_psram_top_0/rd_data_d_57_s0
8	3.890	5.140	1.250	Low Pulse Width	clk_x1	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_w_2_s0
9	3.890	5.140	1.250	Low Pulse Width	clk_x1	u_psram_top/u_psram_top_0/u_psram_init/wr_data_62_s1
10	3.890	5.140	1.250	Low Pulse Width	clk_x1	u_test/check_data_7_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.652
Data Arrival Time	13.638
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0
To	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_4_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R13C29[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/CLK
3.100	0.458	tC2Q	RF	1	R13C29[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/Q
3.903	0.803	tNET	FF	2	R11C29[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s16/I0
4.861	0.958	tINS	FF	1	R11C29[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s16/COUT
4.861	0.000	tNET	FF	2	R11C29[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s17/CIN
4.918	0.057	tINS	FF	1	R11C29[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s17/COUT
6.286	1.367	tNET	FF	1	R12C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s20/I0
7.318	1.032	tINS	FF	1	R12C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s20/F
7.808	0.490	tNET	FF	1	R14C30[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s18/I1
8.434	0.626	tINS	FF	4	R14C30[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s18/F
9.266	0.832	tNET	FF	1	R15C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n734_s10/I2
10.088	0.822	tINS	FF	2	R15C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n734_s10/F
10.897	0.809	tNET	FF	1	R14C30[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s6/I0
11.719	0.822	tINS	FF	6	R14C30[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s6/F
12.539	0.820	tNET	FF	1	R13C31[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n736_s3/I2
13.638	1.099	tINS	FF	1	R13C31[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n736_s3/F
13.638	0.000	tNET	FF	1	R13C31[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R13C31[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_4_s1/CLK
14.290	-0.400	tSu		1	R13C31[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 5.416, 49.255%; route: 5.122, 46.577%; tC2Q: 0.458, 4.168%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path2

Path Summary:

Slack	0.652
Data Arrival Time	13.638
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0
To	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_5_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R13C29[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/CLK
3.100	0.458	tC2Q	RF	1	R13C29[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/Q
3.903	0.803	tNET	FF	2	R11C29[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s16/I0
4.861	0.958	tINS	FF	1	R11C29[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s16/COUT
4.861	0.000	tNET	FF	2	R11C29[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s17/CIN
4.918	0.057	tINS	FF	1	R11C29[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s17/COUT
6.286	1.367	tNET	FF	1	R12C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s20/I0
7.318	1.032	tINS	FF	1	R12C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s20/F
7.808	0.490	tNET	FF	1	R14C30[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s18/I1
8.434	0.626	tINS	FF	4	R14C30[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s18/F
9.266	0.832	tNET	FF	1	R15C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n734_s10/I2
10.088	0.822	tINS	FF	2	R15C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n734_s10/F
10.897	0.809	tNET	FF	1	R14C30[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s6/I0
11.719	0.822	tINS	FF	6	R14C30[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s6/F
12.539	0.820	tNET	FF	1	R13C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s3/I2
13.638	1.099	tINS	FF	1	R13C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s3/F
13.638	0.000	tNET	FF	1	R13C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R13C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_5_s1/CLK
14.290	-0.400	tSu		1	R13C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 5.416, 49.255%; route: 5.122, 46.577%; tC2Q: 0.458, 4.168%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path3

Path Summary:

Slack	1.033
Data Arrival Time	13.257
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0
To	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_0_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R13C29[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/CLK
3.100	0.458	tC2Q	RF	1	R13C29[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/Q
3.903	0.803	tNET	FF	2	R11C29[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s16/I0
4.861	0.958	tINS	FF	1	R11C29[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s16/COUT
4.861	0.000	tNET	FF	2	R11C29[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s17/CIN
4.918	0.057	tINS	FF	1	R11C29[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s17/COUT
6.286	1.367	tNET	FF	1	R12C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s20/I0
7.318	1.032	tINS	FF	1	R12C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s20/F
7.808	0.490	tNET	FF	1	R14C30[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s18/I1
8.434	0.626	tINS	FF	4	R14C30[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s18/F
9.266	0.832	tNET	FF	1	R15C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n734_s10/I2
10.088	0.822	tINS	FF	2	R15C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n734_s10/F
10.897	0.809	tNET	FF	1	R14C30[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s6/I0
11.719	0.822	tINS	FF	6	R14C30[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s6/F
12.225	0.506	tNET	FF	1	R13C30[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n740_s4/I1
13.257	1.032	tINS	FF	1	R13C30[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n740_s4/F
13.257	0.000	tNET	FF	1	R13C30[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R13C30[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_0_s1/CLK
14.290	-0.400	tSu		1	R13C30[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 5.349, 50.393%; route: 4.807, 45.289%; tC2Q: 0.458, 4.318%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path4

Path Summary:

Slack	1.033
Data Arrival Time	13.257
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0
To	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_3_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R13C29[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/CLK
3.100	0.458	tC2Q	RF	1	R13C29[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/Q
3.903	0.803	tNET	FF	2	R11C29[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s16/I0
4.861	0.958	tINS	FF	1	R11C29[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s16/COUT
4.861	0.000	tNET	FF	2	R11C29[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s17/CIN
4.918	0.057	tINS	FF	1	R11C29[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s17/COUT
6.286	1.367	tNET	FF	1	R12C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s20/I0
7.318	1.032	tINS	FF	1	R12C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s20/F
7.808	0.490	tNET	FF	1	R14C30[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s18/I1
8.434	0.626	tINS	FF	4	R14C30[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s18/F
9.266	0.832	tNET	FF	1	R15C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n734_s10/I2
10.088	0.822	tINS	FF	2	R15C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n734_s10/F
10.897	0.809	tNET	FF	1	R14C30[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s6/I0
11.719	0.822	tINS	FF	6	R14C30[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s6/F
12.225	0.506	tNET	FF	1	R13C30[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n737_s3/I2
13.257	1.032	tINS	FF	1	R13C30[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n737_s3/F
13.257	0.000	tNET	FF	1	R13C30[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R13C30[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_3_s1/CLK
14.290	-0.400	tSu		1	R13C30[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 5.349, 50.393%; route: 4.807, 45.289%; tC2Q: 0.458, 4.318%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path5

Path Summary:

Slack	1.132
Data Arrival Time	13.158
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0
To	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_1_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R13C29[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/CLK
3.100	0.458	tC2Q	RF	1	R13C29[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/Q
3.903	0.803	tNET	FF	2	R11C29[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s16/I0
4.861	0.958	tINS	FF	1	R11C29[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s16/COUT
4.861	0.000	tNET	FF	2	R11C29[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s17/CIN
4.918	0.057	tINS	FF	1	R11C29[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s17/COUT
6.286	1.367	tNET	FF	1	R12C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s20/I0
7.318	1.032	tINS	FF	1	R12C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s20/F
7.808	0.490	tNET	FF	1	R14C30[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s18/I1
8.434	0.626	tINS	FF	4	R14C30[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s18/F
9.266	0.832	tNET	FF	1	R15C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n734_s10/I2
10.088	0.822	tINS	FF	2	R15C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n734_s10/F
10.897	0.809	tNET	FF	1	R14C30[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s6/I0
11.699	0.802	tINS	FR	6	R14C30[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s6/F
12.126	0.427	tNET	RR	1	R14C29[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n739_s3/I2
13.158	1.032	tINS	RF	1	R14C29[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n739_s3/F
13.158	0.000	tNET	FF	1	R14C29[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R14C29[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_1_s1/CLK
14.290	-0.400	tSu		1	R14C29[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 5.329, 50.676%; route: 4.728, 44.965%; tC2Q: 0.458, 4.359%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path6

Path Summary:

Slack	1.132
Data Arrival Time	13.158
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0
To	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R13C29[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/CLK
3.100	0.458	tC2Q	RF	1	R13C29[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].last_add_2_s0/Q
3.903	0.803	tNET	FF	2	R11C29[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s16/I0
4.861	0.958	tINS	FF	1	R11C29[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s16/COUT
4.861	0.000	tNET	FF	2	R11C29[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s17/CIN
4.918	0.057	tINS	FF	1	R11C29[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n505_s17/COUT
6.286	1.367	tNET	FF	1	R12C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s20/I0
7.318	1.032	tINS	FF	1	R12C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s20/F
7.808	0.490	tNET	FF	1	R14C30[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s18/I1
8.434	0.626	tINS	FF	4	R14C30[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n755_s18/F
9.266	0.832	tNET	FF	1	R15C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n734_s10/I2
10.088	0.822	tINS	FF	2	R15C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n734_s10/F
10.897	0.809	tNET	FF	1	R14C30[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s6/I0
11.699	0.802	tINS	FR	6	R14C30[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n735_s6/F
12.126	0.427	tNET	RR	1	R14C29[0][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n738_s3/I2
13.158	1.032	tINS	RF	1	R14C29[0][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n738_s3/F
13.158	0.000	tNET	FF	1	R14C29[0][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R14C29[0][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_2_s1/CLK
14.290	-0.400	tSu		1	R14C29[0][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[0].cnt_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 5.329, 50.676%; route: 4.728, 44.965%; tC2Q: 0.458, 4.359%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path7

Path Summary:

Slack	1.240
Data Arrival Time	13.406
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4
To	u_test/addr_add_w_7_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100	0.458	tC2Q	RF	5	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q
4.565	1.465	tNET	FF	1	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/I1
5.664	1.099	tINS	FF	4	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/F
7.602	1.938	tNET	FF	1	R16C37[2][A]	u_test/n497_s2/I1
8.404	0.802	tINS	FR	71	R16C37[2][A]	u_test/n497_s2/F
8.848	0.444	tNET	RR	1	R17C37[0][A]	u_test/n497_s0/I2
9.947	1.099	tINS	RF	31	R17C37[0][A]	u_test/n497_s0/F
11.205	1.258	tNET	FF	1	R16C38[3][A]	u_test/addr_add_w_20_s3/I3
12.266	1.061	tINS	FR	15	R16C38[3][A]	u_test/addr_add_w_20_s3/F
13.406	1.140	tNET	RR	1	R14C39[0][B]	u_test/addr_add_w_7_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R14C39[0][B]	u_test/addr_add_w_7_s1/CLK
14.647	-0.043	tSu		1	R14C39[0][B]	u_test/addr_add_w_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 4.061, 37.727%; route: 6.245, 58.016%; tC2Q: 0.458, 4.258%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path8

Path Summary:

Slack	1.240
Data Arrival Time	13.406
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4
To	u_test/addr_add_w_8_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100	0.458	tC2Q	RF	5	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q
4.565	1.465	tNET	FF	1	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/I1
5.664	1.099	tINS	FF	4	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/F
7.602	1.938	tNET	FF	1	R16C37[2][A]	u_test/n497_s2/I1
8.404	0.802	tINS	FR	71	R16C37[2][A]	u_test/n497_s2/F
8.848	0.444	tNET	RR	1	R17C37[0][A]	u_test/n497_s0/I2
9.947	1.099	tINS	RF	31	R17C37[0][A]	u_test/n497_s0/F
11.205	1.258	tNET	FF	1	R16C38[3][A]	u_test/addr_add_w_20_s3/I3
12.266	1.061	tINS	FR	15	R16C38[3][A]	u_test/addr_add_w_20_s3/F
13.406	1.140	tNET	RR	1	R14C39[2][A]	u_test/addr_add_w_8_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R14C39[2][A]	u_test/addr_add_w_8_s1/CLK
14.647	-0.043	tSu		1	R14C39[2][A]	u_test/addr_add_w_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 4.061, 37.727%; route: 6.245, 58.016%; tC2Q: 0.458, 4.258%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path9

Path Summary:

Slack	1.240
Data Arrival Time	13.406
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4
To	u_test/addr_add_w_9_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100	0.458	tC2Q	RF	5	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q
4.565	1.465	tNET	FF	1	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/I1
5.664	1.099	tINS	FF	4	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/F
7.602	1.938	tNET	FF	1	R16C37[2][A]	u_test/n497_s2/I1
8.404	0.802	tINS	FR	71	R16C37[2][A]	u_test/n497_s2/F
8.848	0.444	tNET	RR	1	R17C37[0][A]	u_test/n497_s0/I2
9.947	1.099	tINS	RF	31	R17C37[0][A]	u_test/n497_s0/F
11.205	1.258	tNET	FF	1	R16C38[3][A]	u_test/addr_add_w_20_s3/I3
12.266	1.061	tINS	FR	15	R16C38[3][A]	u_test/addr_add_w_20_s3/F
13.406	1.140	tNET	RR	1	R14C39[2][B]	u_test/addr_add_w_9_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R14C39[2][B]	u_test/addr_add_w_9_s1/CLK
14.647	-0.043	tSu		1	R14C39[2][B]	u_test/addr_add_w_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 4.061, 37.727%; route: 6.245, 58.016%; tC2Q: 0.458, 4.258%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path10

Path Summary:

Slack	1.282
Data Arrival Time	13.008
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_0_s1
To	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_5_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R18C30[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_0_s1/CLK
3.100	0.458	tC2Q	RF	10	R18C30[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_0_s1/Q
4.576	1.475	tNET	FF	2	R21C31[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s14/I1
5.126	0.550	tINS	FR	1	R21C31[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s14/COUT
5.126	0.000	tNET	RR	2	R21C31[0][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s15/CIN
5.183	0.057	tINS	RF	1	R21C31[0][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s15/COUT
5.183	0.000	tNET	FF	2	R21C31[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s16/CIN
5.240	0.057	tINS	FF	1	R21C31[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s16/COUT
5.240	0.000	tNET	FF	2	R21C31[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s17/CIN
5.297	0.057	tINS	FF	1	R21C31[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s17/COUT
5.297	0.000	tNET	FF	2	R21C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s18/CIN
5.354	0.057	tINS	FF	1	R21C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s18/COUT
6.891	1.538	tNET	FF	1	R18C31[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s18/I2
7.923	1.032	tINS	FF	3	R18C31[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s18/F
8.279	0.356	tNET	FF	1	R18C31[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s11/I0
9.305	1.026	tINS	FR	2	R18C31[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s11/F
9.726	0.421	tNET	RR	1	R18C30[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s7/I1
10.825	1.099	tINS	RF	6	R18C30[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s7/F
11.976	1.150	tNET	FF	1	R18C32[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1270_s3/I1
13.008	1.032	tINS	FF	1	R18C32[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1270_s3/F
13.008	0.000	tNET	FF	1	R18C32[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R18C32[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_5_s1/CLK
14.290	-0.400	tSu		1	R18C32[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 4.967, 47.918%; route: 4.940, 47.660%; tC2Q: 0.458, 4.422%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path11

Path Summary:

Slack	1.282
Data Arrival Time	13.008
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_0_s1
To	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_6_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R18C30[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_0_s1/CLK
3.100	0.458	tC2Q	RF	10	R18C30[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_0_s1/Q
4.576	1.475	tNET	FF	2	R21C31[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s14/I1
5.126	0.550	tINS	FR	1	R21C31[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s14/COUT
5.126	0.000	tNET	RR	2	R21C31[0][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s15/CIN
5.183	0.057	tINS	RF	1	R21C31[0][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s15/COUT
5.183	0.000	tNET	FF	2	R21C31[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s16/CIN
5.240	0.057	tINS	FF	1	R21C31[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s16/COUT
5.240	0.000	tNET	FF	2	R21C31[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s17/CIN
5.297	0.057	tINS	FF	1	R21C31[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s17/COUT
5.297	0.000	tNET	FF	2	R21C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s18/CIN
5.354	0.057	tINS	FF	1	R21C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s18/COUT
6.891	1.538	tNET	FF	1	R18C31[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s18/I2
7.923	1.032	tINS	FF	3	R18C31[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s18/F
8.279	0.356	tNET	FF	1	R18C31[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s11/I0
9.305	1.026	tINS	FR	2	R18C31[3][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s11/F
9.726	0.421	tNET	RR	1	R18C30[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s7/I1
10.825	1.099	tINS	RF	6	R18C30[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s7/F
11.976	1.150	tNET	FF	1	R18C32[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s5/I1
13.008	1.032	tINS	FF	1	R18C32[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s5/F
13.008	0.000	tNET	FF	1	R18C32[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R18C32[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_6_s1/CLK
14.290	-0.400	tSu		1	R18C32[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 4.967, 47.918%; route: 4.940, 47.660%; tC2Q: 0.458, 4.422%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path12

Path Summary:

Slack	1.289
Data Arrival Time	13.357
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4
To	u_test/addr_add_w_12_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100	0.458	tC2Q	RF	5	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q
4.565	1.465	tNET	FF	1	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/I1
5.664	1.099	tINS	FF	4	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/F
7.602	1.938	tNET	FF	1	R16C37[2][A]	u_test/n497_s2/I1
8.404	0.802	tINS	FR	71	R16C37[2][A]	u_test/n497_s2/F
8.848	0.444	tNET	RR	1	R17C37[0][A]	u_test/n497_s0/I2
9.947	1.099	tINS	RF	31	R17C37[0][A]	u_test/n497_s0/F
11.205	1.258	tNET	FF	1	R16C38[3][A]	u_test/addr_add_w_20_s3/I3
12.266	1.061	tINS	FR	15	R16C38[3][A]	u_test/addr_add_w_20_s3/F
13.357	1.091	tNET	RR	1	R17C40[0][A]	u_test/addr_add_w_12_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R17C40[0][A]	u_test/addr_add_w_12_s1/CLK
14.647	-0.043	tSu		1	R17C40[0][A]	u_test/addr_add_w_12_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 4.061, 37.898%; route: 6.196, 57.825%; tC2Q: 0.458, 4.277%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path13

Path Summary:

Slack	1.289
Data Arrival Time	13.357
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4
To	u_test/addr_add_w_13_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100	0.458	tC2Q	RF	5	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q
4.565	1.465	tNET	FF	1	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/I1
5.664	1.099	tINS	FF	4	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/F
7.602	1.938	tNET	FF	1	R16C37[2][A]	u_test/n497_s2/I1
8.404	0.802	tINS	FR	71	R16C37[2][A]	u_test/n497_s2/F
8.848	0.444	tNET	RR	1	R17C37[0][A]	u_test/n497_s0/I2
9.947	1.099	tINS	RF	31	R17C37[0][A]	u_test/n497_s0/F
11.205	1.258	tNET	FF	1	R16C38[3][A]	u_test/addr_add_w_20_s3/I3
12.266	1.061	tINS	FR	15	R16C38[3][A]	u_test/addr_add_w_20_s3/F
13.357	1.091	tNET	RR	1	R17C40[0][B]	u_test/addr_add_w_13_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R17C40[0][B]	u_test/addr_add_w_13_s1/CLK
14.647	-0.043	tSu		1	R17C40[0][B]	u_test/addr_add_w_13_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 4.061, 37.898%; route: 6.196, 57.825%; tC2Q: 0.458, 4.277%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path14

Path Summary:

Slack	1.289
Data Arrival Time	13.357
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4
To	u_test/addr_add_w_14_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100	0.458	tC2Q	RF	5	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q
4.565	1.465	tNET	FF	1	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/I1
5.664	1.099	tINS	FF	4	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/F
7.602	1.938	tNET	FF	1	R16C37[2][A]	u_test/n497_s2/I1
8.404	0.802	tINS	FR	71	R16C37[2][A]	u_test/n497_s2/F
8.848	0.444	tNET	RR	1	R17C37[0][A]	u_test/n497_s0/I2
9.947	1.099	tINS	RF	31	R17C37[0][A]	u_test/n497_s0/F
11.205	1.258	tNET	FF	1	R16C38[3][A]	u_test/addr_add_w_20_s3/I3
12.266	1.061	tINS	FR	15	R16C38[3][A]	u_test/addr_add_w_20_s3/F
13.357	1.091	tNET	RR	1	R17C40[1][A]	u_test/addr_add_w_14_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R17C40[1][A]	u_test/addr_add_w_14_s1/CLK
14.647	-0.043	tSu		1	R17C40[1][A]	u_test/addr_add_w_14_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 4.061, 37.898%; route: 6.196, 57.825%; tC2Q: 0.458, 4.277%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path15

Path Summary:

Slack	1.298
Data Arrival Time	13.348
Data Required Time	14.647
From	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
To	u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R8C11[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
3.100	0.458	tC2Q	RF	6	R8C11[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/Q
4.411	1.311	tNET	FF	1	R7C8[2][B]	u_la0_top/u_ao_mem_ctrl/n225_s12/I2
5.510	1.099	tINS	FF	1	R7C8[2][B]	u_la0_top/u_ao_mem_ctrl/n225_s12/F
6.799	1.289	tNET	FF	1	R7C7[1][B]	u_la0_top/u_ao_mem_ctrl/n225_s6/I3
7.860	1.061	tINS	FR	2	R7C7[1][B]	u_la0_top/u_ao_mem_ctrl/n225_s6/F
8.283	0.423	tNET	RR	1	R8C7[0][B]	u_la0_top/u_ao_mem_ctrl/n225_s4/I1
9.382	1.099	tINS	RF	10	R8C7[0][B]	u_la0_top/u_ao_mem_ctrl/n225_s4/F
11.167	1.784	tNET	FF	1	R7C7[0][B]	u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
12.228	1.061	tINS	FR	1	R7C7[0][B]	u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
13.348	1.121	tNET	RR	1	R8C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R8C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
14.647	-0.043	tSu		1	R8C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 4.320, 40.349%; route: 5.928, 55.370%; tC2Q: 0.458, 4.281%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path16

Path Summary:

Slack	1.320
Data Arrival Time	12.970
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4
To	u_test/addr_15_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100	0.458	tC2Q	RF	5	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q
4.565	1.465	tNET	FF	1	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/I1
5.664	1.099	tINS	FF	4	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/F
7.611	1.947	tNET	FF	1	R18C35[2][B]	u_test/wr_data_63_s4/I1
8.710	1.099	tINS	FF	20	R18C35[2][B]	u_test/wr_data_63_s4/F
10.046	1.336	tNET	FF	1	R16C38[0][B]	u_test/wr_data_63_s3/I2
10.672	0.626	tINS	FF	48	R16C38[0][B]	u_test/wr_data_63_s3/F
11.871	1.199	tNET	FF	1	R17C37[2][B]	u_test/n1007_s0/I0
12.970	1.099	tINS	FF	1	R17C37[2][B]	u_test/n1007_s0/F
12.970	0.000	tNET	FF	1	R17C37[2][B]	u_test/addr_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R17C37[2][B]	u_test/addr_15_s0/CLK
14.290	-0.400	tSu		1	R17C37[2][B]	u_test/addr_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 3.923, 37.984%; route: 5.947, 57.579%; tC2Q: 0.458, 4.438%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path17

Path Summary:

Slack	1.320
Data Arrival Time	12.970
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4
To	u_test/addr_16_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100	0.458	tC2Q	RF	5	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q
4.565	1.465	tNET	FF	1	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/I1
5.664	1.099	tINS	FF	4	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/F
7.611	1.947	tNET	FF	1	R18C35[2][B]	u_test/wr_data_63_s4/I1
8.710	1.099	tINS	FF	20	R18C35[2][B]	u_test/wr_data_63_s4/F
10.046	1.336	tNET	FF	1	R16C38[0][B]	u_test/wr_data_63_s3/I2
10.672	0.626	tINS	FF	48	R16C38[0][B]	u_test/wr_data_63_s3/F
11.871	1.199	tNET	FF	1	R17C37[2][A]	u_test/n1006_s0/I0
12.970	1.099	tINS	FF	1	R17C37[2][A]	u_test/n1006_s0/F
12.970	0.000	tNET	FF	1	R17C37[2][A]	u_test/addr_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R17C37[2][A]	u_test/addr_16_s0/CLK
14.290	-0.400	tSu		1	R17C37[2][A]	u_test/addr_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 3.923, 37.984%; route: 5.947, 57.579%; tC2Q: 0.458, 4.438%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path18

Path Summary:

Slack	1.322
Data Arrival Time	13.325
Data Required Time	14.647
From	u_test/rd_data_d_43_s0
To	u_test/error_d1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R9C17[1][A]	u_test/rd_data_d_43_s0/CLK
3.100	0.458	tC2Q	RF	1	R9C17[1][A]	u_test/rd_data_d_43_s0/Q
6.964	3.863	tNET	FF	2	R9C36[2][B]	u_test/n1616_s0/I1
8.009	1.045	tINS	FF	1	R9C36[2][B]	u_test/n1616_s0/COUT
8.009	0.000	tNET	FF	2	R9C37[0][A]	u_test/n1617_s0/CIN
8.066	0.057	tINS	FF	1	R9C37[0][A]	u_test/n1617_s0/COUT
8.066	0.000	tNET	FF	2	R9C37[0][B]	u_test/n1618_s0/CIN
8.123	0.057	tINS	FF	1	R9C37[0][B]	u_test/n1618_s0/COUT
8.123	0.000	tNET	FF	2	R9C37[1][A]	u_test/n1619_s0/CIN
8.180	0.057	tINS	FF	1	R9C37[1][A]	u_test/n1619_s0/COUT
8.180	0.000	tNET	FF	2	R9C37[1][B]	u_test/n1620_s0/CIN
8.237	0.057	tINS	FF	1	R9C37[1][B]	u_test/n1620_s0/COUT
8.237	0.000	tNET	FF	2	R9C37[2][A]	u_test/n1621_s0/CIN
8.294	0.057	tINS	FF	1	R9C37[2][A]	u_test/n1621_s0/COUT
8.294	0.000	tNET	FF	2	R9C37[2][B]	u_test/n1622_s0/CIN
8.351	0.057	tINS	FF	1	R9C37[2][B]	u_test/n1622_s0/COUT
8.351	0.000	tNET	FF	2	R9C38[0][A]	u_test/n1623_s0/CIN
8.408	0.057	tINS	FF	1	R9C38[0][A]	u_test/n1623_s0/COUT
8.408	0.000	tNET	FF	2	R9C38[0][B]	u_test/n1624_s0/CIN
8.465	0.057	tINS	FF	1	R9C38[0][B]	u_test/n1624_s0/COUT
8.465	0.000	tNET	FF	2	R9C38[1][A]	u_test/n1625_s0/CIN
8.522	0.057	tINS	FF	1	R9C38[1][A]	u_test/n1625_s0/COUT
8.522	0.000	tNET	FF	2	R9C38[1][B]	u_test/n1626_s0/CIN
8.579	0.057	tINS	FF	1	R9C38[1][B]	u_test/n1626_s0/COUT
8.579	0.000	tNET	FF	2	R9C38[2][A]	u_test/n1627_s0/CIN
8.636	0.057	tINS	FF	1	R9C38[2][A]	u_test/n1627_s0/COUT
8.636	0.000	tNET	FF	2	R9C38[2][B]	u_test/n1628_s0/CIN
8.693	0.057	tINS	FF	1	R9C38[2][B]	u_test/n1628_s0/COUT
8.693	0.000	tNET	FF	2	R9C39[0][A]	u_test/n1629_s0/CIN
8.750	0.057	tINS	FF	1	R9C39[0][A]	u_test/n1629_s0/COUT
8.750	0.000	tNET	FF	2	R9C39[0][B]	u_test/n1630_s0/CIN
8.807	0.057	tINS	FF	1	R9C39[0][B]	u_test/n1630_s0/COUT
8.807	0.000	tNET	FF	2	R9C39[1][A]	u_test/n1631_s0/CIN
8.864	0.057	tINS	FF	1	R9C39[1][A]	u_test/n1631_s0/COUT
8.864	0.000	tNET	FF	2	R9C39[1][B]	u_test/n1632_s0/CIN
8.921	0.057	tINS	FF	1	R9C39[1][B]	u_test/n1632_s0/COUT
8.921	0.000	tNET	FF	2	R9C39[2][A]	u_test/n1633_s0/CIN
8.978	0.057	tINS	FF	1	R9C39[2][A]	u_test/n1633_s0/COUT
8.978	0.000	tNET	FF	2	R9C39[2][B]	u_test/n1634_s0/CIN
9.035	0.057	tINS	FF	1	R9C39[2][B]	u_test/n1634_s0/COUT
9.035	0.000	tNET	FF	2	R9C40[0][A]	u_test/n1635_s0/CIN
9.092	0.057	tINS	FF	1	R9C40[0][A]	u_test/n1635_s0/COUT
11.928	2.836	tNET	FF	1	R8C25[1][A]	u_test/n1638_s1/I0
12.989	1.061	tINS	FR	1	R8C25[1][A]	u_test/n1638_s1/F
13.325	0.336	tNET	RR	1	R8C25[1][B]	u_test/error_d1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R8C25[1][B]	u_test/error_d1_s0/CLK
14.647	-0.043	tSu		1	R8C25[1][B]	u_test/error_d1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 3.189, 29.851%; route: 7.036, 65.858%; tC2Q: 0.458, 4.290%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path19

Path Summary:

Slack	1.365
Data Arrival Time	12.924
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4
To	u_test/addr_add_w_8_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100	0.458	tC2Q	RF	5	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q
4.565	1.465	tNET	FF	1	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/I1
5.664	1.099	tINS	FF	4	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/F
7.602	1.938	tNET	FF	1	R16C37[2][A]	u_test/n497_s2/I1
8.404	0.802	tINS	FR	71	R16C37[2][A]	u_test/n497_s2/F
8.848	0.444	tNET	RR	1	R17C37[0][A]	u_test/n497_s0/I2
9.947	1.099	tINS	RF	31	R17C37[0][A]	u_test/n497_s0/F
11.825	1.878	tNET	FF	1	R14C39[2][A]	u_test/n938_s1/I3
12.924	1.099	tINS	FF	1	R14C39[2][A]	u_test/n938_s1/F
12.924	0.000	tNET	FF	1	R14C39[2][A]	u_test/addr_add_w_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R14C39[2][A]	u_test/addr_add_w_8_s1/CLK
14.290	-0.400	tSu		1	R14C39[2][A]	u_test/addr_add_w_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 4.099, 39.864%; route: 5.725, 55.679%; tC2Q: 0.458, 4.457%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path20

Path Summary:

Slack	1.365
Data Arrival Time	12.924
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4
To	u_test/addr_add_w_9_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100	0.458	tC2Q	RF	5	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q
4.565	1.465	tNET	FF	1	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/I1
5.664	1.099	tINS	FF	4	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/F
7.602	1.938	tNET	FF	1	R16C37[2][A]	u_test/n497_s2/I1
8.404	0.802	tINS	FR	71	R16C37[2][A]	u_test/n497_s2/F
8.848	0.444	tNET	RR	1	R17C37[0][A]	u_test/n497_s0/I2
9.947	1.099	tINS	RF	31	R17C37[0][A]	u_test/n497_s0/F
11.825	1.878	tNET	FF	1	R14C39[2][B]	u_test/n937_s1/I2
12.924	1.099	tINS	FF	1	R14C39[2][B]	u_test/n937_s1/F
12.924	0.000	tNET	FF	1	R14C39[2][B]	u_test/addr_add_w_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R14C39[2][B]	u_test/addr_add_w_9_s1/CLK
14.290	-0.400	tSu		1	R14C39[2][B]	u_test/addr_add_w_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 4.099, 39.864%; route: 5.725, 55.679%; tC2Q: 0.458, 4.457%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path21

Path Summary:

Slack	1.443
Data Arrival Time	12.847
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_0_s1
To	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_1_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R18C30[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_0_s1/CLK
3.100	0.458	tC2Q	RF	10	R18C30[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_0_s1/Q
4.576	1.475	tNET	FF	2	R21C31[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s14/I1
5.126	0.550	tINS	FR	1	R21C31[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s14/COUT
5.126	0.000	tNET	RR	2	R21C31[0][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s15/CIN
5.183	0.057	tINS	RF	1	R21C31[0][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s15/COUT
5.183	0.000	tNET	FF	2	R21C31[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s16/CIN
5.240	0.057	tINS	FF	1	R21C31[1][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s16/COUT
5.240	0.000	tNET	FF	2	R21C31[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s17/CIN
5.297	0.057	tINS	FF	1	R21C31[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s17/COUT
5.297	0.000	tNET	FF	2	R21C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s18/CIN
5.354	0.057	tINS	FF	1	R21C31[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1187_s18/COUT
6.891	1.538	tNET	FF	1	R18C31[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s18/I2
7.923	1.032	tINS	FF	3	R18C31[0][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s18/F
8.279	0.356	tNET	FF	1	R18C31[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s10/I0
9.378	1.099	tINS	FF	3	R18C31[2][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s10/F
9.389	0.011	tNET	FF	1	R18C31[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s6/I3
10.421	1.032	tINS	FF	6	R18C31[1][B]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1269_s6/F
12.221	1.800	tNET	FF	1	R20C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1274_s3/I0
12.847	0.626	tINS	FF	1	R20C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/n1274_s3/F
12.847	0.000	tNET	FF	1	R20C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R20C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_1_s1/CLK
14.290	-0.400	tSu		1	R20C30[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/[1].cnt_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 4.567, 44.751%; route: 5.180, 50.757%; tC2Q: 0.458, 4.491%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path22

Path Summary:

Slack	1.469
Data Arrival Time	12.821
Data Required Time	14.290
From	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4
To	u_test/addr_add_w_7_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/CLK
3.100	0.458	tC2Q	RF	5	R12C27[2][A]	u_psram_top/u_psram_top_0/u_Temp_Auto_Adj/adj_done_s4/Q
4.565	1.465	tNET	FF	1	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/I1
5.664	1.099	tINS	FF	4	R15C28[3][B]	u_psram_top/u_psram_top_0/cmd_rdy_d_s/F
7.602	1.938	tNET	FF	1	R16C37[2][A]	u_test/n497_s2/I1
8.404	0.802	tINS	FR	71	R16C37[2][A]	u_test/n497_s2/F
8.848	0.444	tNET	RR	1	R17C37[0][A]	u_test/n497_s0/I2
9.947	1.099	tINS	RF	31	R17C37[0][A]	u_test/n497_s0/F
11.789	1.842	tNET	FF	1	R14C39[0][B]	u_test/n939_s1/I2
12.821	1.032	tINS	FF	1	R14C39[0][B]	u_test/n939_s1/F
12.821	0.000	tNET	FF	1	R14C39[0][B]	u_test/addr_add_w_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R14C39[0][B]	u_test/addr_add_w_7_s1/CLK
14.290	-0.400	tSu		1	R14C39[0][B]	u_test/addr_add_w_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 4.032, 39.609%; route: 5.689, 55.888%; tC2Q: 0.458, 4.503%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path23

Path Summary:

Slack	1.486
Data Arrival Time	13.159
Data Required Time	14.645
From	u_psram_top/u_psram_top_0/u_psram_init/timer_cnt_5_s5
To	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkneg.u_ck_gen
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R17C19[2][B]	u_psram_top/u_psram_top_0/u_psram_init/timer_cnt_5_s5/CLK
3.100	0.458	tC2Q	RF	7	R17C19[2][B]	u_psram_top/u_psram_top_0/u_psram_init/timer_cnt_5_s5/Q
3.942	0.842	tNET	FF	1	R16C19[2][B]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_15_s0/I1
4.974	1.032	tINS	FF	1	R16C19[2][B]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_15_s0/F
4.980	0.005	tNET	FF	1	R16C19[3][A]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_15_s/I2
6.012	1.032	tINS	FF	2	R16C19[3][A]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_15_s/F
7.157	1.145	tNET	FF	1	R16C15[3][A]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_62_s/I0
8.256	1.099	tINS	FF	3	R16C15[3][A]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_62_s/F
10.053	1.797	tNET	FF	1	R12C9[2][B]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/clk_d0_s1/I2
10.875	0.822	tINS	FF	4	R12C9[2][B]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/clk_d0_s1/F
13.159	2.283	tNET	FF	1	IOL23[A]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkneg.u_ck_gen/D2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	IOL23[A]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkneg.u_ck_gen/PCLK
14.645	-0.045	tSu		1	IOL23[A]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkneg.u_ck_gen

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 3.985, 37.891%; route: 6.074, 57.751%; tC2Q: 0.458, 4.358%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path24

Path Summary:

Slack	1.486
Data Arrival Time	13.159
Data Required Time	14.645
From	u_psram_top/u_psram_top_0/u_psram_init/timer_cnt_5_s5
To	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkneg.u_ck_gen
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R17C19[2][B]	u_psram_top/u_psram_top_0/u_psram_init/timer_cnt_5_s5/CLK
3.100	0.458	tC2Q	RF	7	R17C19[2][B]	u_psram_top/u_psram_top_0/u_psram_init/timer_cnt_5_s5/Q
3.942	0.842	tNET	FF	1	R16C19[2][B]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_15_s0/I1
4.974	1.032	tINS	FF	1	R16C19[2][B]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_15_s0/F
4.980	0.005	tNET	FF	1	R16C19[3][A]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_15_s/I2
6.012	1.032	tINS	FF	2	R16C19[3][A]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_15_s/F
7.157	1.145	tNET	FF	1	R16C15[3][A]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_62_s/I0
8.256	1.099	tINS	FF	3	R16C15[3][A]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_62_s/F
10.053	1.797	tNET	FF	1	R12C9[2][B]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/clk_d0_s1/I2
10.875	0.822	tINS	FF	4	R12C9[2][B]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/clk_d0_s1/F
13.159	2.283	tNET	FF	1	IOL23[A]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkneg.u_ck_gen/D0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	IOL23[A]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkneg.u_ck_gen/PCLK
14.645	-0.045	tSu		1	IOL23[A]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkneg.u_ck_gen

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 3.985, 37.891%; route: 6.074, 57.751%; tC2Q: 0.458, 4.358%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path25

Path Summary:

Slack	1.486
Data Arrival Time	13.159
Data Required Time	14.645
From	u_psram_top/u_psram_top_0/u_psram_init/timer_cnt_5_s5
To	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R17C19[2][B]	u_psram_top/u_psram_top_0/u_psram_init/timer_cnt_5_s5/CLK
3.100	0.458	tC2Q	RF	7	R17C19[2][B]	u_psram_top/u_psram_top_0/u_psram_init/timer_cnt_5_s5/Q
3.942	0.842	tNET	FF	1	R16C19[2][B]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_15_s0/I1
4.974	1.032	tINS	FF	1	R16C19[2][B]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_15_s0/F
4.980	0.005	tNET	FF	1	R16C19[3][A]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_15_s/I2
6.012	1.032	tINS	FF	2	R16C19[3][A]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_15_s/F
7.157	1.145	tNET	FF	1	R16C15[3][A]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_62_s/I0
8.256	1.099	tINS	FF	3	R16C15[3][A]	u_psram_top/u_psram_top_0/u_psram_init/out_dq_Z_62_s/F
10.053	1.797	tNET	FF	1	R12C9[2][B]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/clk_d0_s1/I2
10.875	0.822	tINS	FF	4	R12C9[2][B]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/clk_d0_s1/F
13.159	2.283	tNET	FF	1	IOL7[A]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/D2

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	IOL7[A]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/PCLK
14.645	-0.045	tSu		1	IOL7[A]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 3.985, 37.891%; route: 6.074, 57.751%; tC2Q: 0.458, 4.358%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.418
Data Arrival Time	2.340
Data Required Time	1.922
From	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_1_s5
To	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R11C14[0][A]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_1_s5/CLK
2.095	0.333	tC2Q	RF	5	R11C14[0][A]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_1_s5/Q
2.340	0.245	tNET	FF	1	BSRAM_R10[3]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s/ADB[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	BSRAM_R10[3]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s/CLKB
1.922	0.160	tHld		1	BSRAM_R10[3]	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.245, 42.337%; tC2Q: 0.333, 57.663%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path2

Path Summary:

Slack	0.479
Data Arrival Time	2.326
Data Required Time	1.848
From	u_psram_top/u_psram_top_0/rd_data_d_36_s0
To	u_psram_top/u_psram_top_0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R11C17[1][B]	u_psram_top/u_psram_top_0/rd_data_d_36_s0/CLK
2.095	0.333	tC2Q	RF	1	R11C17[1][B]	u_psram_top/u_psram_top_0/rd_data_d_36_s0/Q
2.326	0.231	tNET	FF	1	BSRAM_R10[4]	u_psram_top/u_psram_top_0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	BSRAM_R10[4]	u_psram_top/u_psram_top_0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
1.848	0.086	tHld		1	BSRAM_R10[4]	u_psram_top/u_psram_top_0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.231, 40.960%; tC2Q: 0.333, 59.040%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path3

Path Summary:

Slack	0.479
Data Arrival Time	2.326
Data Required Time	1.848
From	u_psram_top/u_psram_top_0/rd_data_d_6_s0
To	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R11C20[1][A]	u_psram_top/u_psram_top_0/rd_data_d_6_s0/CLK
2.095	0.333	tC2Q	RF	1	R11C20[1][A]	u_psram_top/u_psram_top_0/rd_data_d_6_s0/Q
2.326	0.231	tNET	FF	1	BSRAM_R10[5]	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	BSRAM_R10[5]	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
1.848	0.086	tHld		1	BSRAM_R10[5]	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.231, 40.960%; tC2Q: 0.333, 59.040%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path4

Path Summary:

Slack	0.479
Data Arrival Time	2.326
Data Required Time	1.848
From	u_psram_top/u_psram_top_0/rd_data_d_4_s0
To	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R9C20[1][B]	u_psram_top/u_psram_top_0/rd_data_d_4_s0/CLK
2.095	0.333	tC2Q	RF	1	R9C20[1][B]	u_psram_top/u_psram_top_0/rd_data_d_4_s0/Q
2.326	0.231	tNET	FF	1	BSRAM_R10[5]	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	BSRAM_R10[5]	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
1.848	0.086	tHld		1	BSRAM_R10[5]	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.231, 40.960%; tC2Q: 0.333, 59.040%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path5

Path Summary:

Slack	0.479
Data Arrival Time	2.326
Data Required Time	1.848
From	u_psram_top/u_psram_top_0/rd_data_d_2_s0
To	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R9C20[1][A]	u_psram_top/u_psram_top_0/rd_data_d_2_s0/CLK
2.095	0.333	tC2Q	RF	1	R9C20[1][A]	u_psram_top/u_psram_top_0/rd_data_d_2_s0/Q
2.326	0.231	tNET	FF	1	BSRAM_R10[5]	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	BSRAM_R10[5]	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
1.848	0.086	tHld		1	BSRAM_R10[5]	u_psram_top/u_psram_top_0/matched_rvld[0].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.231, 40.960%; tC2Q: 0.333, 59.040%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path6

Path Summary:

Slack	0.570
Data Arrival Time	2.331
Data Required Time	1.762
From	u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0
To	u_la0_top/u_ao_mem_ctrl/data_reg_3_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/CLK
2.095	0.333	tC2Q	RR	1	R8C10[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/Q
2.331	0.236	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/CLK
1.762	0.000	tHld		1	R8C10[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path7

Path Summary:

Slack	0.570
Data Arrival Time	2.331
Data Required Time	1.762
From	u_la0_top/internal_reg_start_syn_0_s0
To	u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C7[2][A]	u_la0_top/internal_reg_start_syn_0_s0/CLK
2.095	0.333	tC2Q	RR	1	R5C7[2][A]	u_la0_top/internal_reg_start_syn_0_s0/Q
2.331	0.236	tNET	RR	1	R5C7[2][B]	u_la0_top/internal_reg_start_syn_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C7[2][B]	u_la0_top/internal_reg_start_syn_1_s0/CLK
1.762	0.000	tHld		1	R5C7[2][B]	u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path8

Path Summary:

Slack	0.570
Data Arrival Time	2.331
Data Required Time	1.762
From	u_la0_top/internal_reg_force_triger_syn_0_s0
To	u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R3C6[1][A]	u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
2.095	0.333	tC2Q	RR	1	R3C6[1][A]	u_la0_top/internal_reg_force_triger_syn_0_s0/Q
2.331	0.236	tNET	RR	1	R3C6[1][B]	u_la0_top/internal_reg_force_triger_syn_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R3C6[1][B]	u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
1.762	0.000	tHld		1	R3C6[1][B]	u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path9

Path Summary:

Slack	0.570
Data Arrival Time	2.331
Data Required Time	1.762
From	u_la0_top/rst_ao_syn_s0
To	u_la0_top/rst_ao_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][A]	u_la0_top/rst_ao_syn_s0/CLK
2.095	0.333	tC2Q	RR	1	R5C6[0][A]	u_la0_top/rst_ao_syn_s0/Q
2.331	0.236	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
1.762	0.000	tHld		1	R5C6[0][B]	u_la0_top/rst_ao_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path10

Path Summary:

Slack	0.571
Data Arrival Time	7.085
Data Required Time	6.514
From	u_la0_top/data_register_30_s0
To	u_la0_top/internal_register_select_14_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_30_s0/CLK
6.847	0.333	tC2Q	RR	3		u_la0_top/data_register_30_s0/Q
7.085	0.238	tNET	RR	1		u_la0_top/internal_register_select_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/internal_register_select_14_s0/CLK
6.514	0.000	tHld		1		u_la0_top/internal_register_select_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path11

Path Summary:

Slack	0.571
Data Arrival Time	7.085
Data Required Time	6.514
From	u_la0_top/data_register_18_s0
To	u_la0_top/data_register_17_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_18_s0/CLK
6.847	0.333	tC2Q	RR	7		u_la0_top/data_register_18_s0/Q
7.085	0.238	tNET	RR	1		u_la0_top/data_register_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_17_s0/CLK
6.514	0.000	tHld		1		u_la0_top/data_register_17_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path12

Path Summary:

Slack	0.571
Data Arrival Time	7.085
Data Required Time	6.514
From	u_la0_top/data_register_29_s0
To	u_la0_top/data_register_28_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_29_s0/CLK
6.847	0.333	tC2Q	RR	3		u_la0_top/data_register_29_s0/Q
7.085	0.238	tNET	RR	1		u_la0_top/data_register_28_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_28_s0/CLK
6.514	0.000	tHld		1		u_la0_top/data_register_28_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path13

Path Summary:

Slack	0.571
Data Arrival Time	7.085
Data Required Time	6.514
From	u_la0_top/data_register_36_s0
To	u_la0_top/data_register_35_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_36_s0/CLK
6.847	0.333	tC2Q	RR	4		u_la0_top/data_register_36_s0/Q
7.085	0.238	tNET	RR	1		u_la0_top/data_register_35_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_35_s0/CLK
6.514	0.000	tHld		1		u_la0_top/data_register_35_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path14

Path Summary:

Slack	0.571
Data Arrival Time	7.085
Data Required Time	6.514
From	u_icon_top/input_shift_reg_3_s0
To	u_icon_top/input_shift_reg_2_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_icon_top/input_shift_reg_3_s0/CLK
6.847	0.333	tC2Q	RR	2		u_icon_top/input_shift_reg_3_s0/Q
7.085	0.238	tNET	RR	1		u_icon_top/input_shift_reg_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_icon_top/input_shift_reg_2_s0/CLK
6.514	0.000	tHld		1		u_icon_top/input_shift_reg_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path15

Path Summary:

Slack	0.571
Data Arrival Time	7.085
Data Required Time	6.514
From	u_icon_top/enable_reg_1_s0
To	u_icon_top/enable_reg_0_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_icon_top/enable_reg_1_s0/CLK
6.847	0.333	tC2Q	RR	3		u_icon_top/enable_reg_1_s0/Q
7.085	0.238	tNET	RR	1		u_icon_top/enable_reg_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_icon_top/enable_reg_0_s0/CLK
6.514	0.000	tHld		1		u_icon_top/enable_reg_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path16

Path Summary:

Slack	0.572
Data Arrival Time	7.086
Data Required Time	6.514
From	u_la0_top/data_register_28_s0
To	u_la0_top/internal_register_select_12_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_28_s0/CLK
6.847	0.333	tC2Q	RR	3		u_la0_top/data_register_28_s0/Q
7.086	0.239	tNET	RR	1		u_la0_top/internal_register_select_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/internal_register_select_12_s0/CLK
6.514	0.000	tHld		1		u_la0_top/internal_register_select_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path17

Path Summary:

Slack	0.572
Data Arrival Time	7.086
Data Required Time	6.514
From	u_la0_top/data_register_5_s0
To	u_la0_top/data_register_4_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_5_s0/CLK
6.847	0.333	tC2Q	RR	5		u_la0_top/data_register_5_s0/Q
7.086	0.239	tNET	RR	1		u_la0_top/data_register_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_4_s0/CLK
6.514	0.000	tHld		1		u_la0_top/data_register_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path18

Path Summary:

Slack	0.572
Data Arrival Time	7.086
Data Required Time	6.514
From	u_la0_top/data_register_11_s0
To	u_la0_top/data_register_10_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_11_s0/CLK
6.847	0.333	tC2Q	RR	4		u_la0_top/data_register_11_s0/Q
7.086	0.239	tNET	RR	1		u_la0_top/data_register_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_10_s0/CLK
6.514	0.000	tHld		1		u_la0_top/data_register_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path19

Path Summary:

Slack	0.572
Data Arrival Time	7.086
Data Required Time	6.514
From	u_la0_top/data_register_13_s0
To	u_la0_top/data_register_12_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_13_s0/CLK
6.847	0.333	tC2Q	RR	4		u_la0_top/data_register_13_s0/Q
7.086	0.239	tNET	RR	1		u_la0_top/data_register_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_12_s0/CLK
6.514	0.000	tHld		1		u_la0_top/data_register_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path20

Path Summary:

Slack	0.572
Data Arrival Time	7.086
Data Required Time	6.514
From	u_la0_top/data_register_14_s0
To	u_la0_top/data_register_13_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_14_s0/CLK
6.847	0.333	tC2Q	RR	4		u_la0_top/data_register_14_s0/Q
7.086	0.239	tNET	RR	1		u_la0_top/data_register_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_13_s0/CLK
6.514	0.000	tHld		1		u_la0_top/data_register_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path21

Path Summary:

Slack	0.572
Data Arrival Time	7.086
Data Required Time	6.514
From	u_la0_top/data_register_15_s0
To	u_la0_top/data_register_14_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_15_s0/CLK
6.847	0.333	tC2Q	RR	4		u_la0_top/data_register_15_s0/Q
7.086	0.239	tNET	RR	1		u_la0_top/data_register_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_14_s0/CLK
6.514	0.000	tHld		1		u_la0_top/data_register_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path22

Path Summary:

Slack	0.572
Data Arrival Time	7.086
Data Required Time	6.514
From	u_la0_top/data_register_20_s0
To	u_la0_top/data_register_19_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_20_s0/CLK
6.847	0.333	tC2Q	RR	4		u_la0_top/data_register_20_s0/Q
7.086	0.239	tNET	RR	1		u_la0_top/data_register_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_19_s0/CLK
6.514	0.000	tHld		1		u_la0_top/data_register_19_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path23

Path Summary:

Slack	0.572
Data Arrival Time	7.086
Data Required Time	6.514
From	u_la0_top/data_register_27_s0
To	u_la0_top/data_register_26_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_27_s0/CLK
6.847	0.333	tC2Q	RR	3		u_la0_top/data_register_27_s0/Q
7.086	0.239	tNET	RR	1		u_la0_top/data_register_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_26_s0/CLK
6.514	0.000	tHld		1		u_la0_top/data_register_26_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path24

Path Summary:

Slack	0.572
Data Arrival Time	7.086
Data Required Time	6.514
From	u_la0_top/data_register_34_s0
To	u_la0_top/data_register_33_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_34_s0/CLK
6.847	0.333	tC2Q	RR	4		u_la0_top/data_register_34_s0/Q
7.086	0.239	tNET	RR	1		u_la0_top/data_register_33_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_33_s0/CLK
6.514	0.000	tHld		1		u_la0_top/data_register_33_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 41.734%; tC2Q: 0.333, 58.266%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Path25

Path Summary:

Slack	0.573
Data Arrival Time	7.087
Data Required Time	6.514
From	u_la0_top/data_register_6_s0
To	u_la0_top/data_register_5_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_6_s0/CLK
6.847	0.333	tC2Q	RR	5		u_la0_top/data_register_6_s0/Q
7.087	0.240	tNET	RR	1		u_la0_top/data_register_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.971	0.844	tINS	RR	207		u_gw_jtag/tck_o
6.514	2.543	tNET	RR	1		u_la0_top/data_register_5_s0/CLK
6.514	0.000	tHld		1		u_la0_top/data_register_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.240, 41.854%; tC2Q: 0.333, 58.146%
Required Clock Path Delay	cell: 3.971, 60.960%; route: 2.543, 39.040%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	8.241
Data Arrival Time	6.406
Data Required Time	14.647
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
3.100	0.458	tC2Q	RF	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
6.406	3.305	tNET	FF	1	R4C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R4C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
14.647	-0.043	tSu		1	R4C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.305, 87.822%; tC2Q: 0.458, 12.178%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path2

Path Summary:

Slack	8.241
Data Arrival Time	6.406
Data Required Time	14.647
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
3.100	0.458	tC2Q	RF	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
6.406	3.305	tNET	FF	1	R4C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R4C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
14.647	-0.043	tSu		1	R4C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.305, 87.822%; tC2Q: 0.458, 12.178%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path3

Path Summary:

Slack	8.241
Data Arrival Time	6.406
Data Required Time	14.647
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
3.100	0.458	tC2Q	RF	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
6.406	3.305	tNET	FF	1	R4C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R4C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
14.647	-0.043	tSu		1	R4C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.305, 87.822%; tC2Q: 0.458, 12.178%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path4

Path Summary:

Slack	8.241
Data Arrival Time	6.406
Data Required Time	14.647
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
3.100	0.458	tC2Q	RF	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
6.406	3.305	tNET	FF	1	R4C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R4C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
14.647	-0.043	tSu		1	R4C10[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.305, 87.822%; tC2Q: 0.458, 12.178%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path5

Path Summary:

Slack	8.241
Data Arrival Time	6.406
Data Required Time	14.647
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
3.100	0.458	tC2Q	RF	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
6.406	3.305	tNET	FF	1	R4C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R4C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
14.647	-0.043	tSu		1	R4C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.305, 87.822%; tC2Q: 0.458, 12.178%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path6

Path Summary:

Slack	8.241
Data Arrival Time	6.406
Data Required Time	14.647
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
3.100	0.458	tC2Q	RF	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
6.406	3.305	tNET	FF	1	R4C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R4C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
14.647	-0.043	tSu		1	R4C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.305, 87.822%; tC2Q: 0.458, 12.178%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path7

Path Summary:

Slack	8.246
Data Arrival Time	6.401
Data Required Time	14.647
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
3.100	0.458	tC2Q	RF	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
6.401	3.301	tNET	FF	1	R5C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R5C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
14.647	-0.043	tSu		1	R5C10[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.301, 87.807%; tC2Q: 0.458, 12.193%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path8

Path Summary:

Slack	8.246
Data Arrival Time	6.401
Data Required Time	14.647
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
3.100	0.458	tC2Q	RF	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
6.401	3.301	tNET	FF	1	R5C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R5C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
14.647	-0.043	tSu		1	R5C10[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.301, 87.807%; tC2Q: 0.458, 12.193%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path9

Path Summary:

Slack	8.246
Data Arrival Time	6.401
Data Required Time	14.647
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
3.100	0.458	tC2Q	RF	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
6.401	3.301	tNET	FF	1	R5C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R5C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
14.647	-0.043	tSu		1	R5C10[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.301, 87.807%; tC2Q: 0.458, 12.193%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path10

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/check_data_0_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R11C34[0][B]	u_test/check_data_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R11C34[0][B]	u_test/check_data_0_s3/CLK
14.647	-0.043	tSu		1	R11C34[0][B]	u_test/check_data_0_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path11

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/check_data_1_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R11C34[0][A]	u_test/check_data_1_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R11C34[0][A]	u_test/check_data_1_s3/CLK
14.647	-0.043	tSu		1	R11C34[0][A]	u_test/check_data_1_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path12

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/check_data_3_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R12C34[1][B]	u_test/check_data_3_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R12C34[1][B]	u_test/check_data_3_s3/CLK
14.647	-0.043	tSu		1	R12C34[1][B]	u_test/check_data_3_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path13

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/check_data_4_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R12C33[2][B]	u_test/check_data_4_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R12C33[2][B]	u_test/check_data_4_s3/CLK
14.647	-0.043	tSu		1	R12C33[2][B]	u_test/check_data_4_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path14

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/check_data_6_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R12C33[0][B]	u_test/check_data_6_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R12C33[0][B]	u_test/check_data_6_s3/CLK
14.647	-0.043	tSu		1	R12C33[0][B]	u_test/check_data_6_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path15

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/check_data_10_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R11C33[1][A]	u_test/check_data_10_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R11C33[1][A]	u_test/check_data_10_s3/CLK
14.647	-0.043	tSu		1	R11C33[1][A]	u_test/check_data_10_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path16

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/check_data_13_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R12C39[2][A]	u_test/check_data_13_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R12C39[2][A]	u_test/check_data_13_s3/CLK
14.647	-0.043	tSu		1	R12C39[2][A]	u_test/check_data_13_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path17

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/check_data_15_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R12C39[2][B]	u_test/check_data_15_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R12C39[2][B]	u_test/check_data_15_s3/CLK
14.647	-0.043	tSu		1	R12C39[2][B]	u_test/check_data_15_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path18

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/check_data_18_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R12C38[0][B]	u_test/check_data_18_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R12C38[0][B]	u_test/check_data_18_s3/CLK
14.647	-0.043	tSu		1	R12C38[0][B]	u_test/check_data_18_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path19

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/check_data_20_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R11C37[2][B]	u_test/check_data_20_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R11C37[2][B]	u_test/check_data_20_s3/CLK
14.647	-0.043	tSu		1	R11C37[2][B]	u_test/check_data_20_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path20

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/check_data_23_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R12C40[0][A]	u_test/check_data_23_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R12C40[0][A]	u_test/check_data_23_s3/CLK
14.647	-0.043	tSu		1	R12C40[0][A]	u_test/check_data_23_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path21

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/check_data_30_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R12C37[1][A]	u_test/check_data_30_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R12C37[1][A]	u_test/check_data_30_s3/CLK
14.647	-0.043	tSu		1	R12C37[1][A]	u_test/check_data_30_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path22

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/wr_data_add_0_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R14C37[1][A]	u_test/wr_data_add_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R14C37[1][A]	u_test/wr_data_add_0_s3/CLK
14.647	-0.043	tSu		1	R14C37[1][A]	u_test/wr_data_add_0_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path23

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/RD_DONE_s7
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R21C37[1][A]	u_test/RD_DONE_s7/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R21C37[1][A]	u_test/RD_DONE_s7/CLK
14.647	-0.043	tSu		1	R21C37[1][A]	u_test/RD_DONE_s7

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path24

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/RD_CYC_CNT_0_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R20C34[2][B]	u_test/RD_CYC_CNT_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R20C34[2][B]	u_test/RD_CYC_CNT_0_s3/CLK
14.647	-0.043	tSu		1	R20C34[2][B]	u_test/RD_CYC_CNT_0_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Path25

Path Summary:

Slack	8.576
Data Arrival Time	6.071
Data Required Time	14.647
From	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0
To	u_test/WR_CYC_CNT_0_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
2.642	2.642	tNET	RR	1	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/CLK
3.100	0.458	tC2Q	RF	692	R14C23[0][A]	u_psram_top/u_psram_top_0/u_psram_init/init_calib_s0/Q
6.071	2.970	tNET	FF	1	R20C35[0][A]	u_test/WR_CYC_CNT_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.048	12.048					active clock edge time
12.048	0.000					clk_x1
12.048	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
14.690	2.642	tNET	RR	1	R20C35[0][A]	u_test/WR_CYC_CNT_0_s3/CLK
14.647	-0.043	tSu		1	R20C35[0][A]	u_test/WR_CYC_CNT_0_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.048
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.970, 86.632%; tC2Q: 0.458, 13.368%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.642, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.833
Data Arrival Time	2.607
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/trigger_seq_start_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.607	0.512	tNET	RR	1	R3C6[2][A]	u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R3C6[2][A]	u_la0_top/trigger_seq_start_s1/CLK
1.774	0.012	tHld		1	R3C6[2][A]	u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.512, 60.580%; tC2Q: 0.333, 39.420%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path2

Path Summary:

Slack	0.833
Data Arrival Time	2.607
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.607	0.512	tNET	RR	1	R3C6[1][A]	u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R3C6[1][A]	u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
1.774	0.012	tHld		1	R3C6[1][A]	u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.512, 60.580%; tC2Q: 0.333, 39.420%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path3

Path Summary:

Slack	0.833
Data Arrival Time	2.607
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.607	0.512	tNET	RR	1	R3C6[1][B]	u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R3C6[1][B]	u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
1.774	0.012	tHld		1	R3C6[1][B]	u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.512, 60.580%; tC2Q: 0.333, 39.420%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path4

Path Summary:

Slack	0.878
Data Arrival Time	2.652
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_0_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.652	0.557	tNET	RR	1	R9C5[0][A]	u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R9C5[0][A]	u_la0_top/capture_window_sel_0_s3/CLK
1.774	0.012	tHld		1	R9C5[0][A]	u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.557, 62.578%; tC2Q: 0.333, 37.422%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path5

Path Summary:

Slack	0.878
Data Arrival Time	2.652
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.652	0.557	tNET	RR	1	R9C5[0][B]	u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R9C5[0][B]	u_la0_top/triger_level_cnt_0_s3/CLK
1.774	0.012	tHld		1	R9C5[0][B]	u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.557, 62.578%; tC2Q: 0.333, 37.422%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path6

Path Summary:

Slack	0.878
Data Arrival Time	2.652
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.652	0.557	tNET	RR	1	R9C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R9C5[1][A]	u_la0_top/triger_level_cnt_1_s1/CLK
1.774	0.012	tHld		1	R9C5[1][A]	u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.557, 62.578%; tC2Q: 0.333, 37.422%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path7

Path Summary:

Slack	0.897
Data Arrival Time	2.671
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.671	0.576	tNET	RR	1	R6C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R6C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.774	0.012	tHld		1	R6C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.576, 63.355%; tC2Q: 0.333, 36.645%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path8

Path Summary:

Slack	0.897
Data Arrival Time	2.671
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.671	0.576	tNET	RR	1	R5C7[2][A]	u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C7[2][A]	u_la0_top/internal_reg_start_syn_0_s0/CLK
1.774	0.012	tHld		1	R5C7[2][A]	u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.576, 63.355%; tC2Q: 0.333, 36.645%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path9

Path Summary:

Slack	0.897
Data Arrival Time	2.671
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.671	0.576	tNET	RR	1	R5C7[2][B]	u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C7[2][B]	u_la0_top/internal_reg_start_syn_1_s0/CLK
1.774	0.012	tHld		1	R5C7[2][B]	u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.576, 63.355%; tC2Q: 0.333, 36.645%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path10

Path Summary:

Slack	0.911
Data Arrival Time	2.685
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.685	0.590	tNET	RR	1	R7C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R7C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.774	0.012	tHld		1	R7C6[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.590, 63.917%; tC2Q: 0.333, 36.083%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path11

Path Summary:

Slack	0.911
Data Arrival Time	2.685
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.685	0.590	tNET	RR	1	R7C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R7C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.774	0.012	tHld		1	R7C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.590, 63.917%; tC2Q: 0.333, 36.083%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path12

Path Summary:

Slack	0.911
Data Arrival Time	2.685
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.685	0.590	tNET	RR	1	R7C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R7C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.774	0.012	tHld		1	R7C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.590, 63.917%; tC2Q: 0.333, 36.083%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path13

Path Summary:

Slack	0.919
Data Arrival Time	2.693
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.693	0.598	tNET	RR	1	R8C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R8C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
1.774	0.012	tHld		1	R8C6[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.598, 64.207%; tC2Q: 0.333, 35.793%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path14

Path Summary:

Slack	0.919
Data Arrival Time	2.693
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.693	0.598	tNET	RR	1	R8C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R8C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.774	0.012	tHld		1	R8C6[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.598, 64.207%; tC2Q: 0.333, 35.793%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path15

Path Summary:

Slack	0.919
Data Arrival Time	2.693
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.693	0.598	tNET	RR	1	R8C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R8C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
1.774	0.012	tHld		1	R8C6[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.598, 64.207%; tC2Q: 0.333, 35.793%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path16

Path Summary:

Slack	0.919
Data Arrival Time	2.693
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.693	0.598	tNET	RR	1	R8C6[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R8C6[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
1.774	0.012	tHld		1	R8C6[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.598, 64.207%; tC2Q: 0.333, 35.793%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path17

Path Summary:

Slack	1.132
Data Arrival Time	2.906
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.906	0.812	tNET	RR	1	R4C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R4C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.774	0.012	tHld		1	R4C8[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.812, 70.884%; tC2Q: 0.333, 29.116%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path18

Path Summary:

Slack	1.171
Data Arrival Time	2.945
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.945	0.850	tNET	RR	1	R7C5[0][A]	u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R7C5[0][A]	u_la0_top/capture_window_sel_2_s1/CLK
1.774	0.012	tHld		1	R7C5[0][A]	u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.850, 71.842%; tC2Q: 0.333, 28.158%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path19

Path Summary:

Slack	1.171
Data Arrival Time	2.945
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_3_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.945	0.850	tNET	RR	1	R7C5[1][B]	u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R7C5[1][B]	u_la0_top/capture_window_sel_3_s1/CLK
1.774	0.012	tHld		1	R7C5[1][B]	u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.850, 71.842%; tC2Q: 0.333, 28.158%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path20

Path Summary:

Slack	1.171
Data Arrival Time	2.945
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_7_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.945	0.850	tNET	RR	1	R7C5[0][B]	u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R7C5[0][B]	u_la0_top/capture_window_sel_7_s1/CLK
1.774	0.012	tHld		1	R7C5[0][B]	u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.850, 71.842%; tC2Q: 0.333, 28.158%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path21

Path Summary:

Slack	1.171
Data Arrival Time	2.945
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_8_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.945	0.850	tNET	RR	1	R7C5[1][A]	u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R7C5[1][A]	u_la0_top/capture_window_sel_8_s1/CLK
1.774	0.012	tHld		1	R7C5[1][A]	u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.850, 71.842%; tC2Q: 0.333, 28.158%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path22

Path Summary:

Slack	1.171
Data Arrival Time	2.945
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.945	0.850	tNET	RR	1	R7C5[2][B]	u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R7C5[2][B]	u_la0_top/triger_level_cnt_2_s1/CLK
1.774	0.012	tHld		1	R7C5[2][B]	u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.850, 71.842%; tC2Q: 0.333, 28.158%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path23

Path Summary:

Slack	1.171
Data Arrival Time	2.945
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.945	0.850	tNET	RR	1	R7C5[2][A]	u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R7C5[2][A]	u_la0_top/triger_level_cnt_3_s1/CLK
1.774	0.012	tHld		1	R7C5[2][A]	u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.850, 71.842%; tC2Q: 0.333, 28.158%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path24

Path Summary:

Slack	1.179
Data Arrival Time	2.953
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
2.953	0.858	tNET	RR	1	R7C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R7C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.774	0.012	tHld		1	R7C8[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.858, 72.019%; tC2Q: 0.333, 27.981%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Path25

Path Summary:

Slack	1.418
Data Arrival Time	3.192
Data Required Time	1.774
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_end_dly_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R5C6[0][B]	u_la0_top/rst_ao_s0/CLK
2.095	0.333	tC2Q	RR	55	R5C6[0][B]	u_la0_top/rst_ao_s0/Q
3.192	1.097	tNET	RR	1	R4C6[1][A]	u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	1104	LEFTSIDE[0]	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
1.762	1.762	tNET	RR	1	R4C6[1][A]	u_la0_top/capture_end_dly_s0/CLK
1.774	0.012	tHld		1	R4C6[1][A]	u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.097, 76.699%; tC2Q: 0.333, 23.301%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.762, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.890
Actual Width:	5.140
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_top/u_psram_top_0/rd_data_valid_d_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.024	0.000			active clock edge time
6.024	0.000			clk_x1
6.024	0.000	tCL	FF	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
8.669	2.645	tNET	FF	u_psram_top/u_psram_top_0/rd_data_valid_d_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.048	0.000			active clock edge time
12.048	0.000			clk_x1
12.048	0.000	tCL	RR	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
13.810	1.762	tNET	RR	u_psram_top/u_psram_top_0/rd_data_valid_d_1_s0/CLK

MPW2

MPW Summary:

Slack:	3.890
Actual Width:	5.140
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_top/u_psram_top_0/rd_data_valid_d_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.024	0.000			active clock edge time
6.024	0.000			clk_x1
6.024	0.000	tCL	FF	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
8.669	2.645	tNET	FF	u_psram_top/u_psram_top_0/rd_data_valid_d_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.048	0.000			active clock edge time
12.048	0.000			clk_x1
12.048	0.000	tCL	RR	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
13.810	1.762	tNET	RR	u_psram_top/u_psram_top_0/rd_data_valid_d_0_s0/CLK

MPW3

MPW Summary:

Slack:	3.890
Actual Width:	5.140
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_top/u_psram_top_0/rd_data_d_31_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.024	0.000			active clock edge time
6.024	0.000			clk_x1
6.024	0.000	tCL	FF	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
8.669	2.645	tNET	FF	u_psram_top/u_psram_top_0/rd_data_d_31_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.048	0.000			active clock edge time
12.048	0.000			clk_x1
12.048	0.000	tCL	RR	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
13.810	1.762	tNET	RR	u_psram_top/u_psram_top_0/rd_data_d_31_s0/CLK

MPW4

MPW Summary:

Slack:	3.890
Actual Width:	5.140
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_top/u_psram_top_0/rd_data_d_28_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.024	0.000			active clock edge time
6.024	0.000			clk_x1
6.024	0.000	tCL	FF	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
8.669	2.645	tNET	FF	u_psram_top/u_psram_top_0/rd_data_d_28_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.048	0.000			active clock edge time
12.048	0.000			clk_x1
12.048	0.000	tCL	RR	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
13.810	1.762	tNET	RR	u_psram_top/u_psram_top_0/rd_data_d_28_s0/CLK

MPW5

MPW Summary:

Slack:	3.890
Actual Width:	5.140
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_top/u_psram_top_0/rd_data_d_26_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.024	0.000			active clock edge time
6.024	0.000			clk_x1
6.024	0.000	tCL	FF	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
8.669	2.645	tNET	FF	u_psram_top/u_psram_top_0/rd_data_d_26_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.048	0.000			active clock edge time
12.048	0.000			clk_x1
12.048	0.000	tCL	RR	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
13.810	1.762	tNET	RR	u_psram_top/u_psram_top_0/rd_data_d_26_s0/CLK

MPW6

MPW Summary:

Slack:	3.890
Actual Width:	5.140
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_top/u_psram_top_0/rd_data_d_25_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.024	0.000			active clock edge time
6.024	0.000			clk_x1
6.024	0.000	tCL	FF	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
8.669	2.645	tNET	FF	u_psram_top/u_psram_top_0/rd_data_d_25_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.048	0.000			active clock edge time
12.048	0.000			clk_x1
12.048	0.000	tCL	RR	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
13.810	1.762	tNET	RR	u_psram_top/u_psram_top_0/rd_data_d_25_s0/CLK

MPW7

MPW Summary:

Slack:	3.890
Actual Width:	5.140
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_top/u_psram_top_0/rd_data_d_57_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.024	0.000			active clock edge time
6.024	0.000			clk_x1
6.024	0.000	tCL	FF	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
8.669	2.645	tNET	FF	u_psram_top/u_psram_top_0/rd_data_d_57_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.048	0.000			active clock edge time
12.048	0.000			clk_x1
12.048	0.000	tCL	RR	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
13.810	1.762	tNET	RR	u_psram_top/u_psram_top_0/rd_data_d_57_s0/CLK

MPW8

MPW Summary:

Slack:	3.890
Actual Width:	5.140
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_w_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.024	0.000			active clock edge time
6.024	0.000			clk_x1
6.024	0.000	tCL	FF	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
8.669	2.645	tNET	FF	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_w_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.048	0.000			active clock edge time
12.048	0.000			clk_x1
12.048	0.000	tCL	RR	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
13.810	1.762	tNET	RR	u_psram_top/u_psram_top_0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_w_2_s0/CLK

MPW9

MPW Summary:

Slack:	3.890
Actual Width:	5.140
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_psram_top/u_psram_top_0/u_psram_init/wr_data_62_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.024	0.000			active clock edge time
6.024	0.000			clk_x1
6.024	0.000	tCL	FF	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
8.669	2.645	tNET	FF	u_psram_top/u_psram_top_0/u_psram_init/wr_data_62_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.048	0.000			active clock edge time
12.048	0.000			clk_x1
12.048	0.000	tCL	RR	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
13.810	1.762	tNET	RR	u_psram_top/u_psram_top_0/u_psram_init/wr_data_62_s1/CLK

MPW10

MPW Summary:

Slack:	3.890
Actual Width:	5.140
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_test/check_data_7_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.024	0.000			active clock edge time
6.024	0.000			clk_x1
6.024	0.000	tCL	FF	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
8.669	2.645	tNET	FF	u_test/check_data_7_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.048	0.000			active clock edge time
12.048	0.000			clk_x1
12.048	0.000	tCL	RR	u_psram_top/u_psram_top_0/clkdiv/CLKOUT
13.810	1.762	tNET	RR	u_test/check_data_7_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
1104	clk_x1	0.652	2.645
692	init_calib_d	2.571	3.800
71	u_test/n497_5	1.240	2.060
66	u_psram_top/u_psram_top_0/rd_data_valid_d0_0[1]	5.486	5.704
66	u_psram_top/u_psram_top_0/rd_data_valid_d0[0]	7.152	4.037
64	u_psram_top/u_psram_top_0/u_psram_wd/wr_dq_29_4	1.871	2.498
60	u_test/curr_state.CYC_DONE_WAITE	6.374	2.993
59	u_psram_top/u_psram_top_0/config_done_Z	1.597	2.506
55	clk_d	12.304	3.929
48	u_test/wr_data_63_5	1.320	2.968

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R11C12	63.89%
R10C11	62.50%
R10C17	61.11%
R10C12	52.78%
R13C30	50.00%
R10C13	48.61%
R10C14	48.61%
R12C17	47.22%
R12C29	47.22%
R11C11	47.22%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name clk_x1 -period 12.048 -waveform {0 6.024} [get_nets {clk_x1}]
TC_CLOCK	Actived	create_clock -name clk_x2 -period 6.024 -waveform {0 3.012} [get_nets {memory_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clk_x1}] -group [get_clocks {clk_x2}]