PnR Messages

Report Title PnR Report
Design File E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_refDesign\project\impl\gwsynthesis\psram_board_test.vg
Gao Design File E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_refDesign\project\impl\gao\gao.v
Physical Constraints File E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_refDesign\project\src\psram.cst
Timing Constraints File E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_refDesign\project\src\psram.sdc
Tool Version V1.9.12.02 (64-bit)
Part Number GW1NR-LV9LQ144PC6/I5
Device GW1NR-9
Device Version C
Created Time Mon Mar 9 10:44:54 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.737s, Elapsed time = 0h 0m 0.737s Placement Phase 1: CPU time = 0h 0m 0.033s, Elapsed time = 0h 0m 0.033s Placement Phase 2: CPU time = 0h 0m 0.611s, Elapsed time = 0h 0m 0.611s Placement Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s Placement Phase GAO : CPU time = 0h 0m 0.045s, Elapsed time = 0h 0m 0.045s Total Placement: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s Running routing: Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.509s, Elapsed time = 0h 0m 0.51s Routing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Routing Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Total Routing: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s Generate output files: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Time and Memory Usage CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 427MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 1764/8640 21%
    --LUT,ALU,ROM16 1764(1569 LUT, 195 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 1038/6999 15%
    --Logic Register as Latch 0/6480 0%
    --Logic Register as FF 1037/6480 16%
    --I/O Register as Latch 0/519 0%
    --I/O Register as FF 1/519 <1%
CLS 1098/4320 26%
I/O Port 4/121 4%
I/O Buf 4 -
    --Input Buf 2 -
    --Output Buf 2 -
    --Inout Buf 0 -
IOLOGIC 18 IDES4
23 OSER4
21 IODELAY
 28%
BSRAM 2 SDPB
2 SDPX9B
 16%

GAO Resource Usage Summary:

Resource Usage
Logic 406
    --LUT,ALU,ROM16 406(393 LUT, 13 ALU, 0 ROM16)
    --SSRAM(RAM16) 0
Register 276
I/O Port 9
I/O Buf 4
    --Input Buf 3
    --Output Buf 1
    --Inout Buf 0
BSRAM 1

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 0/180%
bank 1 2/327%
bank 2 2/405%
bank 3 0/310%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 2/8 25%
LW 2/8 25%
GCLK_PIN 0/4 0%
CLKDIV 1/8 13%
DHCEN 1/8 13%
DLL 1/4 25%
rPLL 1/2 50%

Global Clock Signals:

Signal Global Clock Location
clk_d PRIMARY TR TL BL
clk_x1 PRIMARY TR TL BR BL
init_calib_d LW -
u_psram_top/u_psram_top_0/ddr_rsti LW -
memory_clk HCLK BANK6_BANK7_HCLK0

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk - 106/1 Y in IOR5[A] RPLL_T_in LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
rst_n - 99/1 Y in IOR8[B] - LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
O_psram_ck[0] - p1-7/3 - out IOL8[A] - LVCMOS18 - UP - - - - - - -
O_psram_ck[1] O_psram_ck_n[1] p2-8/3 - out IOL23[A] - LVCMOS18D - NA - - - - - - -
O_psram_ck_n[0] - p1-8/3 - out IOL7[A] - LVCMOS18 - UP - - - - - - -
O_psram_ck_n[1] O_psram_ck[1] p2-7/3 - out IOL23[B] - LVCMOS18D - NA - - - - - - -
O_psram_reset_n[0] - p1-14/3 - out IOL2[A] - LVCMOS18 - UP - - - - - - -
O_psram_reset_n[1] - p2-14/3 - out IOL18[A] - LVCMOS18 - UP - - - - - - -
O_psram_cs_n[0] - p1-9/3 - out IOL6[B] LPLL_C_fb LVCMOS18 - UP - - - - - - -
O_psram_cs_n[1] - p2-9/3 - out IOL22[A] - LVCMOS18 - UP - - - - - - -
init_calib - 67/2 N out IOB35[B] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
error - 69/2 N out IOB37[B] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
IO_psram_rwds[0] - p1-2/3 - io IOL17[A] - LVCMOS18 - UP - - - - - - -
IO_psram_rwds[1] - p2-2/3 - io IOL27[B] - LVCMOS18 - UP - - - - - - -
IO_psram_dq[0] - p1-13/3 - io IOL2[B] - LVCMOS18 - UP - - - - - - -
IO_psram_dq[1] - p1-12/3 - io IOL3[A] - LVCMOS18 - UP - - - - - - -
IO_psram_dq[2] - p1-11/3 - io IOL4[A] - LVCMOS18 - UP - - - - - - -
IO_psram_dq[3] - p1-10/3 - io IOL6[A] LPLL_T_fb LVCMOS18 - UP - - - - - - -
IO_psram_dq[4] - p1-6/3 - io IOL9[A] GCLKT_7 LVCMOS18 - UP - - - - - - -
IO_psram_dq[5] - p1-5/3 - io IOL15[A] GCLKT_6 LVCMOS18 - UP - - - - - - -
IO_psram_dq[6] - p1-4/3 - io IOL16[A] - LVCMOS18 - UP - - - - - - -
IO_psram_dq[7] - p1-3/3 - io IOL17[B] - LVCMOS18 - UP - - - - - - -
IO_psram_dq[8] - p2-13/3 - io IOL18[B] - LVCMOS18 - UP - - - - - - -
IO_psram_dq[9] - p2-12/3 - io IOL20[A] - LVCMOS18 - UP - - - - - - -
IO_psram_dq[10] - p2-11/3 - io IOL20[B] - LVCMOS18 - UP - - - - - - -
IO_psram_dq[11] - p2-10/3 - io IOL21[A] - LVCMOS18 - UP - - - - - - -
IO_psram_dq[12] - p2-6/3 - io IOL25[A] - LVCMOS18 - UP - - - - - - -
IO_psram_dq[13] - p2-5/3 - io IOL26[A] - LVCMOS18 - UP - - - - - - -
IO_psram_dq[14] - p2-4/3 - io IOL26[B] - LVCMOS18 - UP - - - - - - -
IO_psram_dq[15] - p2-3/3 - io IOL27[A] - LVCMOS18 - UP - - - - - - -

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
3/3 - in IOT2[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
4/3 - in IOT2[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
144/3 - in IOT5[A] MODE0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
143/3 - in IOT6[B] MODE1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
142/3 - in IOT8[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
141/3 - in IOT8[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
140/3 - in IOT10[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
139/3 - in IOT10[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
138/3 - in IOT12[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
137/3 - in IOT12[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
136/0 - in IOT15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
135/0 - in IOT15[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
134/0 - in IOT17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
133/0 - in IOT17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
132/0 - in IOT20[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
131/0 - in IOT20[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
130/0 - in IOT22[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
129/0 - in IOT22[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
128/0 - in IOT24[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
126/0 - in IOT24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
125/0 - in IOT27[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
124/0 - in IOT27[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
123/0 - in IOT29[A] GCLKT_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
122/0 - in IOT29[B] GCLKC_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
121/0 - in IOT32[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
120/0 - in IOT32[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
119/0 - in IOT34[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
118/0 - in IOT34[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
117/1 - in IOT37[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
116/1 - in IOT37[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
115/1 - in IOT39[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
114/1 - in IOT39[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
113/1 - in IOT41[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
112/1 - in IOT41[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
111/1 - in IOT42[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
110/1 - in IOT42[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
29/2 - in IOB4[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
30/2 - in IOB4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/2 - in IOB6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
34/2 - in IOB6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
38/2 - in IOB8[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
39/2 - in IOB8[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
40/2 - in IOB9[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
41/2 - in IOB9[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
42/2 - in IOB11[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
43/2 - in IOB11[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
44/2 - in IOB12[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
45/2 - in IOB12[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
46/2 - in IOB13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
47/2 - in IOB13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
48/2 - in IOB15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
49/2 - in IOB15[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
50/2 - in IOB17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
51/2 - in IOB17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
52/2 - in IOB23[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
54/2 - in IOB23[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
56/2 - in IOB28[A] GCLKT_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
57/2 - in IOB28[B] GCLKC_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
58/2 - in IOB29[A] GCLKT_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
59/2 - in IOB29[B] GCLKC_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
60/2 - in IOB30[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
61/2 - in IOB30[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
62/2 - in IOB31[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
63/2 - in IOB31[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
64/2 - in IOB33[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
65/2 - in IOB33[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
66/2 - in IOB35[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
67/2 init_calib out IOB35[B] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
68/2 - in IOB37[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
69/2 error out IOB37[B] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
70/2 - in IOB39[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
71/2 - in IOB39[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
72/2 - in IOB41[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
75/2 - in IOB42[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
78/2 - in IOB43[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
76/2 - in IOB43[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-14/3 O_psram_reset_n[0] out IOL2[A] - LVCMOS18 - UP - - - - - - -
p1-13/3 IO_psram_dq[0] io IOL2[B] - LVCMOS18 - UP - - - - - - -
p1-12/3 IO_psram_dq[1] io IOL3[A] - LVCMOS18 - UP - - - - - - -
5/3 - in IOL3[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-11/3 IO_psram_dq[2] io IOL4[A] - LVCMOS18 - UP - - - - - - -
6/3 - in IOL4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
7/3 - in IOL5[A] JTAGSEL_N/LPLL_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
8/3 - in IOL5[B] LPLL_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-10/3 IO_psram_dq[3] io IOL6[A] LPLL_T_fb LVCMOS18 - UP - - - - - - -
p1-9/3 O_psram_cs_n[0] out IOL6[B] LPLL_C_fb LVCMOS18 - UP - - - - - - -
p1-8/3 O_psram_ck_n[0] out IOL7[A] - LVCMOS18 - UP - - - - - - -
10/3 - in IOL7[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-7/3 O_psram_ck[0] out IOL8[A] - LVCMOS18 - UP - - - - - - -
11/3 - in IOL8[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-6/3 IO_psram_dq[4] io IOL9[A] GCLKT_7 LVCMOS18 - UP - - - - - - -
12/3 - in IOL9[B] GCLKC_7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
13/3 tms_pad_i in IOL11[A] TMS LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/3 tck_pad_i in IOL11[B] TCK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/3 - in IOL12[A] SCLK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
16/3 tdi_pad_i in IOL12[B] TDI LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
18/3 tdo_pad_o out IOL13[A] TDO LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
20/3 - in IOL13[B] RECONFIG_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
21/3 - in IOL14[A] DONE LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
22/3 - in IOL14[B] READY LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-5/3 IO_psram_dq[5] io IOL15[A] GCLKT_6 LVCMOS18 - UP - - - - - - -
23/3 - in IOL15[B] GCLKC_6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-4/3 IO_psram_dq[6] io IOL16[A] - LVCMOS18 - UP - - - - - - -
24/3 - in IOL16[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-2/3 IO_psram_rwds[0] io IOL17[A] - LVCMOS18 - UP - - - - - - -
p1-3/3 IO_psram_dq[7] io IOL17[B] - LVCMOS18 - UP - - - - - - -
p2-14/3 O_psram_reset_n[1] out IOL18[A] - LVCMOS18 - UP - - - - - - -
p2-13/3 IO_psram_dq[8] io IOL18[B] - LVCMOS18 - UP - - - - - - -
p2-12/3 IO_psram_dq[9] io IOL20[A] - LVCMOS18 - UP - - - - - - -
p2-11/3 IO_psram_dq[10] io IOL20[B] - LVCMOS18 - UP - - - - - - -
p2-10/3 IO_psram_dq[11] io IOL21[A] - LVCMOS18 - UP - - - - - - -
25/3 - in IOL21[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p2-9/3 O_psram_cs_n[1] out IOL22[A] - LVCMOS18 - UP - - - - - - -
26/3 - in IOL22[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p2-8/3 O_psram_ck[1] out IOL23[A] - LVCMOS18D - NA - - - - - - -
p2-7/3 O_psram_ck_n[1] out IOL23[B] - LVCMOS18D - NA - - - - - - -
27/3 - in IOL24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p2-6/3 IO_psram_dq[12] io IOL25[A] - LVCMOS18 - UP - - - - - - -
28/3 - in IOL25[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p2-5/3 IO_psram_dq[13] io IOL26[A] - LVCMOS18 - UP - - - - - - -
p2-4/3 IO_psram_dq[14] io IOL26[B] - LVCMOS18 - UP - - - - - - -
p2-3/3 IO_psram_dq[15] io IOL27[A] - LVCMOS18 - UP - - - - - - -
p2-2/3 IO_psram_rwds[1] io IOL27[B] - LVCMOS18 - UP - - - - - - -
106/1 clk in IOR5[A] RPLL_T_in LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
104/1 - in IOR5[B] RPLL_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
102/1 - in IOR6[A] RPLL_T_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
101/1 - in IOR6[B] RPLL_C_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
100/1 - in IOR7[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
99/1 rst_n in IOR8[B] - LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
98/1 - in IOR9[A] GCLKT_2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
97/1 - in IOR9[B] GCLKC_2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
96/1 - in IOR11[A] MI/D7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
95/1 - in IOR11[B] MO/D6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
94/1 - in IOR12[A] MCS_N/D5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
93/1 - in IOR12[B] MCLK/D4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
92/1 - in IOR13[A] FASTRD_N/D3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
90/1 - in IOR13[B] SI/D2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
88/1 - in IOR14[A] SO/D1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
87/1 - in IOR14[B] SSPI_CS_N/D0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
86/1 - in IOR15[A] DIN/CLKHOLD_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
85/1 - in IOR15[B] DOUT/WE_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
84/1 - in IOR16[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
83/1 - in IOR17[B] GCLKC_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
82/1 - in IOR21[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
81/1 - in IOR22[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
80/1 - in IOR23[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
79/1 - in IOR24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8