Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_refDesign\project\src\gowin_rpll\gowin_rpll.v E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_refDesign\project\src\key_debounce.v E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_refDesign\project\src\psram_memory_interface_hs\psram_memory_interface_hs.v E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_refDesign\project\src\psram_syn_top.v E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_refDesign\project\src\psram_test.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW1NR-LV9LQ144PC6/I5 |
| Device | GW1NR-9 |
| Device Version | C |
| Created Time | Wed Mar 4 09:37:10 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | psram_syn_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.371s, Peak memory usage = 436.145MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 436.145MB Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.092s, Peak memory usage = 436.145MB Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.144s, Peak memory usage = 436.145MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 436.145MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 436.145MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 436.145MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 436.145MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 436.145MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 436.145MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 436.145MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 436.145MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.253s, Peak memory usage = 436.145MB Generate output files: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.176s, Peak memory usage = 436.145MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 436.145MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 4 |
| Embedded Port | 26 |
| I/O Buf | 29 |
| IBUF | 2 |
| OBUF | 8 |
| IOBUF | 18 |
| ELVDS_OBUF | 1 |
| Register | 1038 |
| DFF | 3 |
| DFFE | 1 |
| DFFSE | 12 |
| DFFR | 20 |
| DFFRE | 2 |
| DFFP | 5 |
| DFFPE | 6 |
| DFFC | 570 |
| DFFCE | 419 |
| LUT | 1561 |
| LUT2 | 338 |
| LUT3 | 483 |
| LUT4 | 740 |
| ALU | 167 |
| ALU | 167 |
| INV | 10 |
| INV | 10 |
| IOLOGIC | 62 |
| IDES4 | 18 |
| OSER4 | 23 |
| IODELAY | 21 |
| BSRAM | 4 |
| SDPB | 2 |
| SDPX9B | 2 |
| CLOCK | 3 |
| CLKDIV | 1 |
| DHCEN | 1 |
| rPLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1738(1571 LUT, 167 ALU) / 8640 | 21% |
| Register | 1038 / 6921 | 15% |
| --Register as Latch | 0 / 6921 | 0% |
| --Register as FF | 1038 / 6921 | 15% |
| BSRAM | 4 / 26 | 16% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | Generated | 6.038 | 165.625 | 0.000 | 3.019 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUT |
| 3 | your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.038 | 165.625 | 0.000 | 3.019 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTP |
| 4 | your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | Generated | 12.075 | 82.812 | 0.000 | 6.038 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD |
| 5 | your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 18.113 | 55.208 | 0.000 | 9.057 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD3 |
| 6 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 12.075 | 82.812 | 0.000 | 6.038 | your_instance_name/rpll_inst/CLKOUT | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | u_psram_top/u_psram_top/clkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 104.370(MHz) | 5 | TOP |
| 2 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | 82.812(MHz) | 72.055(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -1.803 |
| Data Arrival Time | 14.931 |
| Data Required Time | 13.128 |
| From | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1 |
| To | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1 |
| Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 1033 | u_psram_top/u_psram_top/clkdiv/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1/CLK |
| 1.911 | 0.458 | tC2Q | RF | 9 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1/Q |
| 2.871 | 0.960 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s14/I1 |
| 3.916 | 1.045 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s14/COUT |
| 3.916 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s15/CIN |
| 3.973 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s15/COUT |
| 3.973 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s16/CIN |
| 4.030 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s16/COUT |
| 4.030 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s17/CIN |
| 4.087 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s17/COUT |
| 5.047 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s20/I0 |
| 6.079 | 1.032 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s20/F |
| 7.039 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s18/I1 |
| 8.138 | 1.099 | tINS | FF | 4 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s18/F |
| 9.098 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n734_s10/I2 |
| 9.920 | 0.822 | tINS | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n734_s10/F |
| 10.880 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n735_s6/I0 |
| 11.912 | 1.032 | tINS | FF | 6 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n735_s6/F |
| 12.872 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n740_s4/I1 |
| 13.971 | 1.099 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n740_s4/F |
| 14.931 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.075 | 12.075 | active clock edge time | |||
| 12.075 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.802 | 0.727 | tCL | RR | 1033 | u_psram_top/u_psram_top/clkdiv/CLKOUT |
| 13.528 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1/CLK |
| 13.128 | -0.400 | tSu | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 12.075 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 6.300, 46.742%; route: 6.720, 49.857%; tC2Q: 0.458, 3.401% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:| Slack | -1.607 |
| Data Arrival Time | 14.735 |
| Data Required Time | 13.128 |
| From | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1 |
| To | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_1_s1 |
| Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 1033 | u_psram_top/u_psram_top/clkdiv/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1/CLK |
| 1.911 | 0.458 | tC2Q | RF | 9 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1/Q |
| 2.871 | 0.960 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s14/I1 |
| 3.916 | 1.045 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s14/COUT |
| 3.916 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s15/CIN |
| 3.973 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s15/COUT |
| 3.973 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s16/CIN |
| 4.030 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s16/COUT |
| 4.030 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s17/CIN |
| 4.087 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s17/COUT |
| 5.047 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s20/I0 |
| 6.079 | 1.032 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s20/F |
| 7.039 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s18/I1 |
| 8.138 | 1.099 | tINS | FF | 4 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s18/F |
| 9.098 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n734_s13/I3 |
| 9.724 | 0.626 | tINS | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n734_s13/F |
| 10.684 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n735_s4/I1 |
| 11.783 | 1.099 | tINS | FF | 6 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n735_s4/F |
| 12.743 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n739_s3/I0 |
| 13.775 | 1.032 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n739_s3/F |
| 14.735 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.075 | 12.075 | active clock edge time | |||
| 12.075 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.802 | 0.727 | tCL | RR | 1033 | u_psram_top/u_psram_top/clkdiv/CLKOUT |
| 13.528 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_1_s1/CLK |
| 13.128 | -0.400 | tSu | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 12.075 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 6.104, 45.956%; route: 6.720, 50.593%; tC2Q: 0.458, 3.451% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:| Slack | -1.607 |
| Data Arrival Time | 14.735 |
| Data Required Time | 13.128 |
| From | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1 |
| To | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_2_s1 |
| Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 1033 | u_psram_top/u_psram_top/clkdiv/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1/CLK |
| 1.911 | 0.458 | tC2Q | RF | 9 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1/Q |
| 2.871 | 0.960 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s14/I1 |
| 3.916 | 1.045 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s14/COUT |
| 3.916 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s15/CIN |
| 3.973 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s15/COUT |
| 3.973 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s16/CIN |
| 4.030 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s16/COUT |
| 4.030 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s17/CIN |
| 4.087 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s17/COUT |
| 5.047 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s20/I0 |
| 6.079 | 1.032 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s20/F |
| 7.039 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s18/I1 |
| 8.138 | 1.099 | tINS | FF | 4 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s18/F |
| 9.098 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n734_s13/I3 |
| 9.724 | 0.626 | tINS | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n734_s13/F |
| 10.684 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n735_s4/I1 |
| 11.783 | 1.099 | tINS | FF | 6 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n735_s4/F |
| 12.743 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n738_s3/I0 |
| 13.775 | 1.032 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n738_s3/F |
| 14.735 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.075 | 12.075 | active clock edge time | |||
| 12.075 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.802 | 0.727 | tCL | RR | 1033 | u_psram_top/u_psram_top/clkdiv/CLKOUT |
| 13.528 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_2_s1/CLK |
| 13.128 | -0.400 | tSu | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 12.075 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 6.104, 45.956%; route: 6.720, 50.593%; tC2Q: 0.458, 3.451% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:| Slack | -1.607 |
| Data Arrival Time | 14.735 |
| Data Required Time | 13.128 |
| From | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1 |
| To | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_3_s1 |
| Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 1033 | u_psram_top/u_psram_top/clkdiv/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1/CLK |
| 1.911 | 0.458 | tC2Q | RF | 9 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1/Q |
| 2.871 | 0.960 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s14/I1 |
| 3.916 | 1.045 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s14/COUT |
| 3.916 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s15/CIN |
| 3.973 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s15/COUT |
| 3.973 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s16/CIN |
| 4.030 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s16/COUT |
| 4.030 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s17/CIN |
| 4.087 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s17/COUT |
| 5.047 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s20/I0 |
| 6.079 | 1.032 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s20/F |
| 7.039 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s18/I1 |
| 8.138 | 1.099 | tINS | FF | 4 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s18/F |
| 9.098 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n734_s13/I3 |
| 9.724 | 0.626 | tINS | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n734_s13/F |
| 10.684 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n735_s4/I1 |
| 11.783 | 1.099 | tINS | FF | 6 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n735_s4/F |
| 12.743 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n737_s3/I0 |
| 13.775 | 1.032 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n737_s3/F |
| 14.735 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.075 | 12.075 | active clock edge time | |||
| 12.075 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.802 | 0.727 | tCL | RR | 1033 | u_psram_top/u_psram_top/clkdiv/CLKOUT |
| 13.528 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_3_s1/CLK |
| 13.128 | -0.400 | tSu | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 12.075 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 6.104, 45.956%; route: 6.720, 50.593%; tC2Q: 0.458, 3.451% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:| Slack | -1.607 |
| Data Arrival Time | 14.735 |
| Data Required Time | 13.128 |
| From | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1 |
| To | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_4_s1 |
| Launch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 1033 | u_psram_top/u_psram_top/clkdiv/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1/CLK |
| 1.911 | 0.458 | tC2Q | RF | 9 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_0_s1/Q |
| 2.871 | 0.960 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s14/I1 |
| 3.916 | 1.045 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s14/COUT |
| 3.916 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s15/CIN |
| 3.973 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s15/COUT |
| 3.973 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s16/CIN |
| 4.030 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s16/COUT |
| 4.030 | 0.000 | tNET | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s17/CIN |
| 4.087 | 0.057 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n505_s17/COUT |
| 5.047 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s20/I0 |
| 6.079 | 1.032 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s20/F |
| 7.039 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s18/I1 |
| 8.138 | 1.099 | tINS | FF | 4 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n755_s18/F |
| 9.098 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n734_s13/I3 |
| 9.724 | 0.626 | tINS | FF | 2 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n734_s13/F |
| 10.684 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n735_s4/I1 |
| 11.783 | 1.099 | tINS | FF | 6 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n735_s4/F |
| 12.743 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n736_s3/I0 |
| 13.775 | 1.032 | tINS | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/n736_s3/F |
| 14.735 | 0.960 | tNET | FF | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_4_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 12.075 | 12.075 | active clock edge time | |||
| 12.075 | 0.000 | u_psram_top/u_psram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 12.802 | 0.727 | tCL | RR | 1033 | u_psram_top/u_psram_top/clkdiv/CLKOUT |
| 13.528 | 0.726 | tNET | RR | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_4_s1/CLK |
| 13.128 | -0.400 | tSu | 1 | u_psram_top/u_psram_top/u_Temp_Auto_Adj/[0].cnt_4_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 12.075 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 6.104, 45.956%; route: 6.720, 50.593%; tC2Q: 0.458, 3.451% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |