Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\gw_jtag.v
E:\IP\PSRAM\PSRAM_Memory_Interface\RefDesign\GW1NR_LV9LQ144\Gowin_PSRAM_Memory_Interface_HS_refDesign\project\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.01 (64-bit)
Part Number GW1NR-LV9LQ144PC6/I5
Device GW1NR-9
Device Version C
Created Time Fri Jan 23 14:24:49 2026
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.241s, Peak memory usage = 65.918MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 65.918MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 65.918MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 65.918MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 65.918MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 65.918MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 65.918MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 65.918MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 65.918MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 65.918MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 65.918MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 65.918MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 95.766MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 95.766MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 95.766MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 95.766MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 9
I/O Buf 9
    IBUF 8
    OBUF 1
Register 276
    DFF 15
    DFFR 1
    DFFP 3
    DFFPE 33
    DFFC 27
    DFFCE 197
LUT 384
    LUT2 41
    LUT3 102
    LUT4 241
MUX 1
    MUX16 1
ALU 13
    ALU 13
INV 4
    INV 4
BSRAM 1
    SDPB 1
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 409(396 LUT, 13 ALU) / 8640 5%
Register 276 / 6843 5%
  --Register as Latch 0 / 6843 0%
  --Register as FF 276 / 6843 5%
BSRAM 1 / 26 4%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk_x1 Base 20.000 50.000 0.000 10.000 clk_x1_ibuf/I
2 u_icon_top/n19_6 Base 20.000 50.000 0.000 10.000 u_icon_top/n19_s2/F

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_x1 50.000(MHz) 88.524(MHz) 6 TOP
2 u_icon_top/n19_6 50.000(MHz) 549.954(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 8.704
Data Arrival Time 11.622
Data Required Time 20.326
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 71 clk_x1_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.184 0.458 tC2Q RF 5 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n232_s2/I1
3.243 1.099 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n232_s2/F
4.203 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n229_s2/I3
4.829 0.626 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n229_s2/F
5.789 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n227_s2/I2
6.611 0.822 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n227_s2/F
7.571 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n226_s2/I1
8.670 1.099 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n226_s2/F
9.630 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n226_s1/I0
10.662 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n226_s1/F
11.622 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 71 clk_x1_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.678, 42.932%; route: 5.760, 52.862%; tC2Q: 0.458, 4.206%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:
Slack 8.981
Data Arrival Time 11.345
Data Required Time 20.326
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 71 clk_x1_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.184 0.458 tC2Q RF 5 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n232_s2/I1
3.243 1.099 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n232_s2/F
4.203 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n229_s2/I3
4.829 0.626 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n229_s2/F
5.789 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n227_s2/I2
6.611 0.822 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n227_s2/F
7.571 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n225_s3/I2
8.393 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n225_s3/F
9.353 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n225_s2/I0
10.385 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n225_s2/F
11.345 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 71 clk_x1_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.401, 41.443%; route: 5.760, 54.241%; tC2Q: 0.458, 4.316%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:
Slack 10.290
Data Arrival Time 10.036
Data Required Time 20.326
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 71 clk_x1_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
1.184 0.458 tC2Q RF 3 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n225_s10/I0
3.176 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n225_s10/F
4.136 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n225_s6/I1
5.235 1.099 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n225_s6/F
6.195 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n225_s4/I1
7.294 1.099 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n225_s4/F
8.254 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n233_s1/I2
9.076 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n233_s1/F
10.036 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 71 clk_x1_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.052, 43.522%; route: 4.800, 51.555%; tC2Q: 0.458, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:
Slack 10.290
Data Arrival Time 10.036
Data Required Time 20.326
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 71 clk_x1_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
1.184 0.458 tC2Q RF 3 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n225_s10/I0
3.176 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n225_s10/F
4.136 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n225_s6/I1
5.235 1.099 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n225_s6/F
6.195 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n225_s4/I1
7.294 1.099 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n225_s4/F
8.254 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n231_s1/I2
9.076 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n231_s1/F
10.036 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 71 clk_x1_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.052, 43.522%; route: 4.800, 51.555%; tC2Q: 0.458, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:
Slack 10.290
Data Arrival Time 10.036
Data Required Time 20.326
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 71 clk_x1_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
1.184 0.458 tC2Q RF 3 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n225_s10/I0
3.176 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n225_s10/F
4.136 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n225_s6/I1
5.235 1.099 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n225_s6/F
6.195 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n225_s4/I1
7.294 1.099 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n225_s4/F
8.254 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n230_s1/I2
9.076 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n230_s1/F
10.036 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 71 clk_x1_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.052, 43.522%; route: 4.800, 51.555%; tC2Q: 0.458, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%