Power Messages

Report Title	Power Analysis Report
Design File	E:\IP\PSRAM\UHS2_Memory_Interface\RefDesign\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\IP\PSRAM\UHS2_Memory_Interface\RefDesign\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\psram.cst
Timing Constraints File	E:\IP\PSRAM\UHS2_Memory_Interface\RefDesign\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\psram.sdc
Tool Version	V1.9.11.02 (64-bit)
Part Number	GW5AR-LV25UG256PC2/I1
Device	GW5AR-25
Device Version	A
Created Time	Wed May 28 14:44:37 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade	Commercial
Process	Typical
Ambient Temperature	25.000
Use Custom Theta JA	false
Heat Sink	None
Air Flow	LFM_0
Use Custom Theta SA	false
Board Thermal Model	None
Use Custom Theta JB	false
Related Vcd File
Related Saif File
Filter Glitches	false
Default IO Toggle Rate	0.125
Default Remain Toggle Rate	0.125

Power Summary

Power Information:

Total Power (mW)	279.465
Quiescent Power (mW)	52.103
Dynamic Power (mW)	227.362

Thermal Information:

Junction Temperature	32.512
Theta JA	26.880
Max Allowed Ambient Temperature	77.488

Supply Information:

Voltage Source	Voltage	Dynamic Current(mA)	Quiescent Current(mA)	Power(mW)
VCC	0.900	184.590	29.998	193.129
VCCX	3.300	3.652	3.000	21.953
VCCIO18	1.800	3.508	0.847	7.839
VCCIO33	3.300	0.149	0.146	0.971
VCCLDO	3.300	12.840	4.000	55.572

Power Details

Power By Block Type:

Block Type	Total Power(mW)	Static Power(mW)	Average Toggle Rate(millions of transitions/sec)
Logic	2.122	NA	15.697
IO	29.018	6.423	82.880
BSRAM	116.037	NA	NA
PLL	42.372	NA	NA
DDRDLL	44.237	NA	NA
DQS	111.024	NA	NA

Power By Hierarchy:

Hierarchy Entity	Total Power(mW)	Block Dynamic Power(mW)
top	315.792	315.792(315.781)
top/inst_apm64_top/	272.656	272.656(272.656)
top/inst_apm64_top/u_apm64_top/	272.656	272.656(228.089)
top/inst_apm64_top/u_apm64_top/u_apsram_ctrl/	0.214	0.214(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_init/	0.456	0.456(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_sync/	0.015	0.015(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/	227.325	227.325(227.323)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/	113.628	113.628(57.888)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/	28.685	28.685(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/	29.203	29.203(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/	113.611	113.611(57.888)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/	28.685	28.685(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/	29.203	29.203(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/fifo_ctrl_in_gen[0].u_fifo_ctrl/	0.019	0.019(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/fifo_ctrl_in_gen[1].u_fifo_ctrl/	0.019	0.019(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/u_apm64_cmd_lane/	0.026	0.026(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/	0.020	0.020(0.000)
top/inst_apm64_top/u_apm64_top/u_cmd_fifo/	0.078	0.078(0.000)
top/u_Gowin_PLL/	42.691	42.691(42.691)
top/u_Gowin_PLL/u_pll/	42.372	42.372(0.000)
top/u_Gowin_PLL/u_pll_init/	0.319	0.319(0.000)
top/u_reset_key/	0.030	0.030(0.000)
top/u_test/	0.403	0.403(0.000)

Power By Clock Domain:

Clock Domain	Clock Frequency(Mhz)	Total Dynamic Power(mW)
clkin	50.000	42.748
userclk	133.333	117.683
mem_clk	533.333	155.361